Commit Graph

10 Commits

Author SHA1 Message Date
Ken Lin 22d358da0b board: ge: bx50v3: add the PMIC configuration support
Change the PMIC bulk configuration from auto mode to sync mode to avoid
voltage dropout issue seen in auto mode.

Signed-off-by: Ken Lin <ken.lin@advantech.com.tw>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
2016-11-29 16:42:53 +01:00
Masahiro Yamada 1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Fabio Estevam c6a51bab17 bx50v3: Use imx_ddr_size() for calculating the DDR size
imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-07-28 13:27:20 +02:00
Andrew Shadura 0c344e6e7a board: ge: bx50v3: don't configure the backlight when there's no display
Don't try to configure the backlight when CONFIG_VIDEO_IPUV3 isn't set.

Signed-off-by: Andrew Shadura <andrew.shadura@collabora.co.uk>
2016-06-07 18:13:05 +02:00
Akshay Bhat 8d293f49b4 board: ge: bx50v3: Fix to meet LVDS display power on timing
On a reset/reboot, the display power needs to be off for atleast 500ms
before turning it back on. So add a delay to the boot process to meet
the display timing requirement.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-04-19 16:05:51 +02:00
Akshay Bhat 54971ac6de board: ge: bx50v3: Use pwm for display backlight
Setup the LCD backlight brightness control pin to use PWM

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-04-19 16:05:51 +02:00
Akshay Bhat 494d43ec35 board: ge: bx50v3: Setup LDB_DI_CLK source
To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-04-19 16:05:13 +02:00
Akshay Bhat de708da0e8 board: ge: bx50v3: Split display setup function
B450v3/B650v3 uses single channel LVDS and does not support HDMI.
B850v3 uses dual channel LVDS and supports HDMI. Hence split the display
setup into two different functions.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-04-19 16:05:13 +02:00
Justin Waters 7d0b8cfeaa board: ge: bx50v3: Disable unused pins
Certain pins are not used on the i.MX6, and should have a neutral
pad configuration in order to reduce electrical interference on
the board. This commit defines these pins with a default value
rather than relying on the system defaults.

Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
2016-04-19 15:54:59 +02:00
Akshay Bhat f9162b15c1 arm: imx: Add support for GE Bx50v3 boards
Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
 - FEC Ethernet
 - USB Ports
 - SDHC and MMC boot
 - SPI NOR
 - LVDS and HDMI display

Basic information about the module:
 - Module manufacturer: Advantech
 - CPU: Freescale ARM Cortex-A9 i.MX6D
 - SPECS:
     Up to 2GB Onboard DDR3 Memory;
     Up to 16GB Onboard eMMC NAND Flash
     Supports OpenGL ES 2.0 and OpenVG 1.1
     HDMI, 24-bit LVDS
     1x UART, 2x I2C, 8x GPIO,
     4x Host USB 2.0 port, 1x USB OTG port,
     1x micro SD (SDHC),1x SDIO, 1x SATA II,
     1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-03-09 12:45:42 +01:00