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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

This commit is contained in:
Albert ARIBAUD 2013-04-04 15:44:57 +02:00
parent be08abc242 4fdebefa45
commit fed029f3c3
34 changed files with 1448 additions and 240 deletions
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1
Makefile
View File

@ -273,6 +273,7 @@ LIBS-y += disk/libdisk.o
LIBS-y += drivers/bios_emulator/libatibiosemu.o
LIBS-y += drivers/block/libblock.o
LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o
LIBS-y += drivers/crypto/libcrypto.o
LIBS-y += drivers/dma/libdma.o
LIBS-y += drivers/fpga/libfpga.o
LIBS-y += drivers/gpio/libgpio.o

167
arch/arm/cpu/armv7/exynos/clock.c
View File

@ -27,6 +27,49 @@
#include <asm/arch/clk.h>
#include <asm/arch/periph.h>
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
*/
struct clk_bit_info {
int8_t src_bit;
int8_t div_bit;
int8_t prediv_bit;
};
/* src_bit div_bit prediv_bit */
static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
{0, 0, -1},
{4, 4, -1},
{8, 8, -1},
{12, 12, -1},
{0, 0, 8},
{4, 16, 24},
{8, 0, 8},
{12, 16, 24},
{-1, -1, -1},
{16, 0, 8},
{20, 16, 24},
{24, 0, 8},
{0, 0, 4},
{4, 12, 16},
{-1, -1, -1},
{-1, -1, -1},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{-1, 24, 0},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
{24, 0, -1},
};
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
{ 192000000, 0, 48, 3, 1, 0 },
@ -201,6 +244,107 @@ static unsigned long exynos5_get_pll_clk(int pllreg)
return fout;
}
static unsigned long exynos5_get_periph_rate(int peripheral)
{
struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
unsigned long sclk, sub_clk;
unsigned int src, div, sub_div;
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
switch (peripheral) {
case PERIPH_ID_UART0:
case PERIPH_ID_UART1:
case PERIPH_ID_UART2:
case PERIPH_ID_UART3:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric0);
break;
case PERIPH_ID_PWM0:
case PERIPH_ID_PWM1:
case PERIPH_ID_PWM2:
case PERIPH_ID_PWM3:
case PERIPH_ID_PWM4:
src = readl(&clk->src_peric0);
div = readl(&clk->div_peric3);
break;
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric1);
break;
case PERIPH_ID_SPI2:
src = readl(&clk->src_peric1);
div = readl(&clk->div_peric2);
break;
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
src = readl(&clk->sclk_src_isp);
div = readl(&clk->sclk_div_isp);
break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
case PERIPH_ID_SDMMC3:
src = readl(&clk->src_fsys);
div = readl(&clk->div_fsys1);
break;
case PERIPH_ID_I2C0:
case PERIPH_ID_I2C1:
case PERIPH_ID_I2C2:
case PERIPH_ID_I2C3:
case PERIPH_ID_I2C4:
case PERIPH_ID_I2C5:
case PERIPH_ID_I2C6:
case PERIPH_ID_I2C7:
sclk = exynos5_get_pll_clk(MPLL);
sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
& 0x7) + 1;
div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
& 0x7) + 1;
return (sclk / sub_div) / div;
default:
debug("%s: invalid peripheral %d", __func__, peripheral);
return -1;
};
src = (src >> bit_info->src_bit) & 0xf;
switch (src) {
case EXYNOS_SRC_MPLL:
sclk = exynos5_get_pll_clk(MPLL);
break;
case EXYNOS_SRC_EPLL:
sclk = exynos5_get_pll_clk(EPLL);
break;
case EXYNOS_SRC_VPLL:
sclk = exynos5_get_pll_clk(VPLL);
break;
default:
return 0;
}
/* Ratio clock division for this peripheral */
sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1);
/* Pre-ratio clock division for SDMMC0 and 2 */
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1);
}
return sub_clk;
}
unsigned long clock_get_periph_rate(int peripheral)
{
if (cpu_is_exynos5())
return exynos5_get_periph_rate(peripheral);
else
return 0;
}
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
@ -324,27 +468,6 @@ static unsigned long exynos4x12_get_pwm_clk(void)
return pclk;
}
/* exynos5: return pwm clock frequency */
static unsigned long exynos5_get_pwm_clk(void)
{
struct exynos5_clock *clk =
(struct exynos5_clock *)samsung_get_base_clock();
unsigned long pclk, sclk;
unsigned int ratio;
/*
* CLK_DIV_PERIC3
* PWM_RATIO [3:0]
*/
ratio = readl(&clk->div_peric3);
ratio = ratio & 0xf;
sclk = get_pll_clk(MPLL);
pclk = sclk / (ratio + 1);
return pclk;
}
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
@ -1210,7 +1333,7 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5())
return exynos5_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
else {
if (proid_is_exynos4412())
return exynos4x12_get_pwm_clk();

36
arch/arm/cpu/armv7/exynos/soc.c
View File

@ -23,6 +23,14 @@
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
enum l2_cache_params {
CACHE_TAG_RAM_SETUP = (1 << 9),
CACHE_DATA_RAM_SETUP = (1 << 5),
CACHE_TAG_RAM_LATENCY = (2 << 6),
CACHE_DATA_RAM_LATENCY = (2 << 0)
};
void reset_cpu(ulong addr)
{
@ -36,3 +44,31 @@ void enable_caches(void)
dcache_enable();
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
/*
* Set L2 cache parameters
*/
static void exynos5_set_l2cache_params(void)
{
unsigned int val = 0;
asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
val |= CACHE_TAG_RAM_SETUP |
CACHE_DATA_RAM_SETUP |
CACHE_TAG_RAM_LATENCY |
CACHE_DATA_RAM_LATENCY;
asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
}
/*
* Sets L2 cache related parameters before enabling data cache
*/
void v7_outer_cache_enable(void)
{
if (cpu_is_exynos5())
exynos5_set_l2cache_params();
}
#endif

42
arch/arm/cpu/armv7/s5p-common/pwm.c
View File

@ -70,7 +70,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq)
return tin_parent_rate / 16;
}
#define NS_IN_HZ (1000000000UL)
#define NS_IN_SEC 1000000000UL
int pwm_config(int pwm_id, int duty_ns, int period_ns)
{
@ -79,7 +79,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
unsigned int offset;
unsigned long tin_rate;
unsigned long tin_ns;
unsigned long period;
unsigned long frequency;
unsigned long tcon;
unsigned long tcnt;
unsigned long tcmp;
@ -89,34 +89,24 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
* fact that anything faster than 1GHz is easily representable
* by 32bits.
*/
if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0)
return -ERANGE;
if (duty_ns > period_ns)
return -EINVAL;
period = NS_IN_HZ / period_ns;
frequency = NS_IN_SEC / period_ns;
/* Check to see if we are changing the clock rate of the PWM */
tin_rate = pwm_calc_tin(pwm_id, period);
tin_rate = pwm_calc_tin(pwm_id, frequency);
tin_ns = NS_IN_HZ / tin_rate;
tin_ns = NS_IN_SEC / tin_rate;
tcnt = period_ns / tin_ns;
/* Note, counters count down */
tcmp = duty_ns / tin_ns;
tcmp = tcnt - tcmp;
/*
* the pwm hw only checks the compare register after a decrement,
* so the pin never toggles if tcmp = tcnt
*/
if (tcmp == tcnt)
tcmp--;
if (tcmp < 0)
tcmp = 0;
/* Update the PWM register block. */
offset = pwm_id * 3;
if (pwm_id < 4) {
@ -143,7 +133,7 @@ int pwm_init(int pwm_id, int div, int invert)
u32 val;
const struct s5p_timer *pwm =
(struct s5p_timer *)samsung_get_base_timer();
unsigned long timer_rate_hz;
unsigned long ticks_per_period;
unsigned int offset, prescaler;
/*
@ -167,14 +157,24 @@ int pwm_init(int pwm_id, int div, int invert)
val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id);
writel(val, &pwm->tcfg1);
timer_rate_hz = get_pwm_clk() / ((prescaler + 1) *
(div + 1));
if (pwm_id == 4) {
/*
* TODO(sjg): Use this as a countdown timer for now. We count
* down from the maximum value to 0, then reset.
*/
ticks_per_period = -1UL;
} else {
const unsigned long pwm_hz = 1000;
unsigned long timer_rate_hz = get_pwm_clk() /
((prescaler + 1) * (1 << div));
timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ;
ticks_per_period = timer_rate_hz / pwm_hz;
}
/* set count value */
offset = pwm_id * 3;
writel(timer_rate_hz, &pwm->tcntb0 + offset);
writel(ticks_per_period, &pwm->tcntb0 + offset);
val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id));
if (invert && (pwm_id < 4))

115
arch/arm/cpu/armv7/s5p-common/timer.c
View File

@ -39,13 +39,33 @@ static inline struct s5p_timer *s5p_get_base_timer(void)
return (struct s5p_timer *)samsung_get_base_timer();
}
/**
* Read the countdown timer.
*
* This operates at 1MHz and counts downwards. It will wrap about every
* hour (2^32 microseconds).
*
* @return current value of timer
*/
static unsigned long timer_get_us_down(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
return readl(&timer->tcnto4);
}
int timer_init(void)
{
/* PWM Timer 4 */
pwm_init(4, MUX_DIV_2, 0);
pwm_config(4, 0, 0);
pwm_init(4, MUX_DIV_4, 0);
pwm_config(4, 100000, 100000);
pwm_enable(4);
/* Use this as the current monotonic time in us */
gd->arch.timer_reset_value = 0;
/* Use this as the last timer value we saw */
gd->arch.lastinc = timer_get_us_down();
reset_timer_masked();
return 0;
@ -56,48 +76,43 @@ int timer_init(void)
*/
unsigned long get_timer(unsigned long base)
{
return get_timer_masked() - base;
ulong now = timer_get_us_down();
/*
* Increment the time by the amount elapsed since the last read.
* The timer may have wrapped around, but it makes no difference to
* our arithmetic here.
*/
gd->arch.timer_reset_value += gd->arch.lastinc - now;
gd->arch.lastinc = now;
/* Divide by 1000 to convert from us to ms */
return gd->arch.timer_reset_value / 1000 - base;
}
unsigned long timer_get_us(void)
{
static unsigned long base_time_us;
struct s5p_timer *const timer =
(struct s5p_timer *)samsung_get_base_timer();
unsigned long now_downward_us = readl(&timer->tcnto4);
if (!base_time_us)
base_time_us = now_downward_us;
/* Note that this timer counts downward. */
return base_time_us - now_downward_us;
}
/* delay x useconds */
void __udelay(unsigned long usec)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long tmo, tmp, count_value;
unsigned long count_value;
count_value = readl(&timer->tcntb4);
if (usec >= 1000) {
/*
* if "big" number, spread normalization
* to seconds
* 1. start to normalize for usec to ticks per sec
* 2. find number of "ticks" to wait to achieve target
* 3. finish normalize.
*/
tmo = usec / 1000;
tmo *= (CONFIG_SYS_HZ * count_value);
tmo /= 1000;
} else {
/* else small number, don't kill it prior to HZ multiply */
tmo = usec * CONFIG_SYS_HZ * count_value;
tmo /= (1000 * 1000);
}
/* get current timestamp */
tmp = get_current_tick();
/* if setting this fordward will roll time stamp */
/* reset "advancing" timestamp to 0, set lastinc value */
/* else, set advancing stamp wake up time */
if ((tmo + tmp + 1) < tmp)
reset_timer_masked();
else
tmo += tmp;
/* loop till event */
while (get_current_tick() < tmo)
; /* nop */
count_value = timer_get_us_down();
while ((int)(count_value - timer_get_us_down()) < (int)usec)
;
}
void reset_timer_masked(void)
@ -109,30 +124,6 @@ void reset_timer_masked(void)
gd->arch.tbl = 0;
}
unsigned long get_timer_masked(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long count_value = readl(&timer->tcntb4);
return get_current_tick() / count_value;
}
unsigned long get_current_tick(void)
{
struct s5p_timer *const timer = s5p_get_base_timer();
unsigned long now = readl(&timer->tcnto4);
unsigned long count_value = readl(&timer->tcntb4);
if (gd->arch.lastinc >= now)
gd->arch.tbl += gd->arch.lastinc - now;
else
gd->arch.tbl += gd->arch.lastinc + count_value - now;
gd->arch.lastinc = now;
return gd->arch.tbl;
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.

13
arch/arm/dts/exynos5250.dtsi
View File

@ -156,4 +156,17 @@
reg = <0x10060000 0x10000>;
};
fimd@14400000 {
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
};

15
arch/arm/include/asm/arch-exynos/clk.h
View File

@ -29,6 +29,12 @@
#define VPLL 4
#define BPLL 5
enum pll_src_bit {
EXYNOS_SRC_MPLL = 6,
EXYNOS_SRC_EPLL,
EXYNOS_SRC_VPLL,
};
unsigned long get_pll_clk(int pllreg);
unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
@ -44,4 +50,13 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
/**
* get the clk frequency of the required peripheral
*
* @param peripheral Peripheral id
*
* @return frequency of the peripheral clk
*/
unsigned long clock_get_periph_rate(int peripheral);
#endif

10
arch/arm/include/asm/arch-exynos/cpu.h
View File

@ -62,6 +62,7 @@
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS4X12 */
#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
@ -92,9 +93,10 @@
#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
@ -106,6 +108,7 @@
#define EXYNOS5_SWRESET 0x10040400
#define EXYNOS5_SYSREG_BASE 0x10050000
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
#define EXYNOS5_ACE_SFR_BASE 0x10830000
#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
@ -205,6 +208,7 @@ static inline unsigned int samsung_get_base_##device(void) \
SAMSUNG_BASE(adc, ADC_BASE)
SAMSUNG_BASE(clock, CLOCK_BASE)
SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
SAMSUNG_BASE(dp, DP_BASE)
SAMSUNG_BASE(sysreg, SYSREG_BASE)
SAMSUNG_BASE(fimd, FIMD_BASE)

1
arch/arm/include/asm/arch-exynos/dp_info.h
View File

@ -199,7 +199,6 @@ enum {
struct exynos_dp_platform_data {
struct edp_device_info *edp_dev_info;
void (*phy_enable)(unsigned int);
};
#ifdef CONFIG_EXYNOS_DP

5
arch/arm/include/asm/arch-exynos/periph.h
View File

@ -61,6 +61,11 @@ enum periph_id {
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
PERIPH_ID_SDMMC4,
PERIPH_ID_PWM0,
PERIPH_ID_PWM1,
PERIPH_ID_PWM2,
PERIPH_ID_PWM3,
PERIPH_ID_PWM4,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,

40
board/samsung/dts/exynos5250-smdk5250.dts
View File

@ -79,4 +79,44 @@
samsung,slope = <274761730>;
samsung,dc-value = <25>;
};
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <2560>;
samsung,vl-row = <1600>;
samsung,vl-width = <2560>;
samsung,vl-height = <1600>;
samsung,vl-clkp;
samsung,vl-dp;
samsung,vl-bpix = <4>;
samsung,vl-hspw = <32>;
samsung,vl-hbpd = <80>;
samsung,vl-hfpd = <48>;
samsung,vl-vspw = <6>;
samsung,vl-vbpd = <37>;
samsung,vl-vfpd = <3>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,winid = <3>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
};
dp@145b0000 {
samsung,lt-status = <0>;
samsung,master-mode = <0>;
samsung,bist-mode = <0>;
samsung,bist-pattern = <0>;
samsung,h-sync-polarity = <0>;
samsung,v-sync-polarity = <0>;
samsung,interlaced = <0>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
};
};

22
board/samsung/smdk5250/clock_init.c
View File

@ -434,10 +434,10 @@ void system_clock_init()
val = readl(&clk->mux_stat_core1);
} while ((val | MUX_MPLL_SEL_MASK) != val);
clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK);
clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK);
clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK);
clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
| MUX_GPLL_SEL_MASK;
do {
@ -494,35 +494,35 @@ void system_clock_init()
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0);
while (readl(&clk->apll_con0) & APLL_CON0_LOCKED)
while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
;
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0);
while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED)
while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
;
/* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0);
while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED)
while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
;
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0);
while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED)
while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
;
/* Set GPLL */
writel(GPLL_CON1_VAL, &clk->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &clk->gpll_con0);
while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED)
while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
;
/* Set EPLL */
@ -530,7 +530,7 @@ void system_clock_init()
writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0);
while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED)
while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
;
/* Set VPLL */
@ -538,7 +538,7 @@ void system_clock_init()
writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0);
while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED)
while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
;
writel(CLK_SRC_CORE0_VAL, &clk->src_core0);

2
board/samsung/smdk5250/setup.h
View File

@ -343,7 +343,7 @@
#define TOP2_VAL 0x0110000
/* CLK_SRC_PERIC0 */
#define PWM_SEL 0
#define PWM_SEL 6
#define UART3_SEL 6
#define UART2_SEL 6
#define UART1_SEL 6

19
board/samsung/smdk5250/smdk5250.c
View File

@ -312,9 +312,10 @@ int board_eth_init(bd_t *bis)
u32 smc_bw_conf, smc_bc_conf;
struct fdt_sromc config;
fdt_addr_t base_addr;
int node;
#ifdef CONFIG_OF_CONTROL
int node;
node = decode_sromc(gd->fdt_blob, &config);
if (node < 0) {
debug("%s: Could not find sromc configuration\n", __func__);
@ -454,7 +455,7 @@ int board_early_init_f(void)
#endif
#ifdef CONFIG_LCD
void cfg_lcd_gpio(void)
void exynos_cfg_lcd_gpio(void)
{
struct exynos5_gpio_part1 *gpio1 =
(struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
@ -471,6 +472,12 @@ void cfg_lcd_gpio(void)
s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3));
}
void exynos_set_dp_phy(unsigned int onoff)
{
set_dp_phy_ctrl(onoff);
}
#ifndef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
.vl_freq = 60,
.vl_col = 2560,
@ -494,10 +501,6 @@ vidinfo_t panel_info = {
.vl_cmd_allow_len = 0xf,
.win_id = 3,
.cfg_gpio = cfg_lcd_gpio,
.backlight_on = NULL,
.lcd_power_on = NULL,
.reset_lcd = NULL,
.dual_lcd_enabled = 0,
.init_delay = 0,
@ -537,14 +540,16 @@ static struct edp_device_info edp_info = {
};
static struct exynos_dp_platform_data dp_platform_data = {
.phy_enable = set_dp_phy_ctrl,
.edp_dev_info = &edp_info,
};
#endif
void init_panel_info(vidinfo_t *vid)
{
#ifndef CONFIG_OF_CONTROL
vid->rgb_mode = MODE_RGB_P,
exynos_set_dp_platform_data(&dp_platform_data);
#endif
}
#endif

6
board/samsung/trats/trats.c
View File

@ -635,7 +635,7 @@ int board_early_init_f(void)
return 0;
}
static void lcd_reset(void)
void exynos_reset_lcd(void)
{
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
@ -755,10 +755,6 @@ vidinfo_t panel_info = {
.vl_cmd_allow_len = 0xf,
.win_id = 3,
.cfg_gpio = NULL,
.backlight_on = NULL,
.lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */
.reset_lcd = lcd_reset,
.dual_lcd_enabled = 0,
.init_delay = 0,

23
board/samsung/universal_c210/universal.c
View File

@ -384,7 +384,7 @@ static void init_pmic_lcd(void)
puts("LCD pmic initialisation error!\n");
}
static void lcd_cfg_gpio(void)
void exynos_cfg_lcd_gpio(void)
{
unsigned int i, f3_end = 4;
@ -423,7 +423,7 @@ static void lcd_cfg_gpio(void)
spi_init();
}
static void reset_lcd(void)
void exynos_reset_lcd(void)
{
s5p_gpio_set_value(&gpio2->y4, 5, 1);
udelay(10000);
@ -433,7 +433,7 @@ static void reset_lcd(void)
udelay(100);
}
static void lcd_power_on(void)
void exynos_lcd_power_on(void)
{
struct pmic *p = pmic_get("MAX8998_PMIC");
@ -471,10 +471,6 @@ vidinfo_t panel_info = {
.vl_cmd_allow_len = 0xf,
.win_id = 0,
.cfg_gpio = lcd_cfg_gpio,
.backlight_on = NULL,
.lcd_power_on = lcd_power_on,
.reset_lcd = reset_lcd,
.dual_lcd_enabled = 0,
.init_delay = 0,
@ -484,6 +480,16 @@ vidinfo_t panel_info = {
.mipi_enabled = 0,
};
void exynos_cfg_ldo(void)
{
ld9040_cfg_ldo();
}
void exynos_enable_ldo(unsigned int onoff)
{
ld9040_enable_ldo(onoff);
}
void init_panel_info(vidinfo_t *vid)
{
vid->logo_on = 1;
@ -498,9 +504,6 @@ void init_panel_info(vidinfo_t *vid)
vid->pclk_name = 1; /* MPLL */
vid->sclk_div = 1;
vid->cfg_ldo = ld9040_cfg_ldo;
vid->enable_ldo = ld9040_enable_ldo;
setenv("lcdinfo", "lcd=ld9040");
}

18
common/hash.c
View File

@ -25,6 +25,7 @@
#include <common.h>
#include <command.h>
#include <hw_sha.h>
#include <hash.h>
#include <sha1.h>
#include <sha256.h>
@ -36,6 +37,23 @@
* algorithm names must be in lower case.
*/
static struct hash_algo hash_algo[] = {
/*
* CONFIG_SHA_HW_ACCEL is defined if hardware acceleration is
* available.
*/
#ifdef CONFIG_SHA_HW_ACCEL
{
"sha1",
SHA1_SUM_LEN,
hw_sha1,
CHUNKSZ_SHA1,
}, {
"sha256",
SHA256_SUM_LEN,
hw_sha256,
CHUNKSZ_SHA256,
},
#endif
/*
* This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise
* it bloats the code for boards which use SHA1 but not the 'hash'

69
doc/device-tree-bindings/video/exynos-dp.txt Normal file
View File

@ -0,0 +1,69 @@
Exynos Display port controller
==============================
Required properties:
SOC specific:
compatible: should be "samsung,exynos5-dp"
reg: Base address of DP IP
Optional properties:
samsung,h-res: X resolution of the panel
samsung,h-sync-width: hsync value
samsung,h-back-porch: left margin
samsung,h-front-porch right margin
samsung,v-res: Y resolution of the panel
samsung,v-sync-width: vsync value
samsung,v-back-porch: upper margin
samsung,v-front-porch: lower margin
samsung,v-sync-rate: refresh rate
samsung,lt-status: Link training status
0(DP_LT_NONE), 1(DP_LT_START), 2(DP_LT_CR), 3(DP_LT_ET),
4(DP_LT_FINISHED), 5(DP_LT_FAIL)
samsung,master-mode: 1 if you want to run DP as master, else 0
samsung,bist-mode: 1 to enable video bist mode, else 0
samsung,bist-pattern: bist mode pattern type
0(NO_PATTERN), 1(COLOR_RAMP), 2(BALCK_WHITE_V_LINES),
3(COLOR_SQUARE), 4(INVALID_PATTERN), 5(COLORBAR_32),
6(COLORBAR_64),7(WHITE_GRAY_BALCKBAR_32),
8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32),
10(MOBILE_WHITEBAR_64)
samsung,h-sync-polarity: Horizontal Sync polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,v-sync-polarity: Vertical Sync polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,interlaced: Progressive if 0, else Interlaced
samsung,color-space: input video data format
COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
samsung,dynamic-range: dynamic range for input video data
VESA = 0, CEA = 1
samsung,ycbcr-coeff: YCbCr co-efficients for input video
COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
samsung,color-depth: number of bits per colour component
COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
Example:
SOC specific part:
dp@145b0000 {
compatible = "samsung,exynos5-dp";
reg = <0x145b0000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
};
Board(panel) specific part:
dp@145b0000 {
samsung,lt-status = <0>;
samsung,master-mode = <0>;
samsung,bist-mode = <0>;
samsung,bist-pattern = <0>;
samsung,h-sync-polarity = <0>;
samsung,v-sync-polarity = <0>;
samsung,interlaced = <0>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
};

92
doc/device-tree-bindings/video/exynos-fb.txt Normal file
View File

@ -0,0 +1,92 @@
Exynos Display Controller
=========================
Required properties:
SOC specific:
compatible: should be "samsung,exynos-fimd"
reg: Base address of FIMD IP.
Board(panel specific):
samsung,vl-col: X resolution of the panel
samsung,vl-row: Y resolution of the panel
samsung,vl-freq: Refresh rate
samsung,vl-bpix: Bits per pixel
samsung,vl-hspw: Hsync value
samsung,vl-hfpd: Right margin
samsung,vl-hbpd: Left margin
samsung,vl-vspw: Vsync value
samsung,vl-vfpd: Lower margin
samsung,vl-vbpd: Upper margin
Optional properties:
Board(panel specific):
samsung,vl-width: width of display area in mm
samsung,vl-height: Height of display area in mm
samsung,vl-clkp: Clock polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-oep: Output Enable polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-hsp: Horizontal Sync polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-vsp: Vertical Sync polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-dp: Data polarity
CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH
samsung,vl-cmd-allow-len: Wait end of frame
samsung,winid: Window number on which data is to be displayed
samsung,init-delay: Delay before LCD initialization starts
samsung,power-on-delay: Delay after LCD is powered on
samsung,reset-delay: Delay after LCD is reset
samsung,interface-mode: 1(FIMD_RGB_INTERFACE), 2(FIMD_CPU_INTERFACE)
samsung,mipi-enabled: 1 if you want to use MIPI, else 0
samsung,dp-enabled: 1is you want to use DP, else 0
samsung,cs-setup: cs_setup value in FIMD_CPU_INTERFACE mode.
samsung,wr-setup: wr_setup value in FIMD_CPU_INTERFACE mode.
samsung,wr-act: wr_act value in FIMD_CPU_INTERFACE mode.
samsung,wr-hold: wr_hold value in FIMD_CPU_INTERFACE mode.
samsung,logo-on: 1 if you want to use custom logo.
0 if you want LCD console.
samsung,logo-width: pixel width of logo image. Valid if logo_on = 1
samsung,logo-height: pixel height of logo image. Valid if logo_on = 1
samsung,logo-addr: Address of logo image. Valid if logo_on = 1
samsung,rgb-mode: 0(MODE_RGB_P), 1(MODE_BGR_P),
2(MODE_RGB_S), 3(MODE_BGR_S)
samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
samsung,sclk-div: parent_clock/source_clock ratio
samsung,dual-lcd-enabled: 1 if you support two LCD, else 0
Example:
SOC specific part:
fimd@14400000 {
compatible = "samsung,exynos-fimd";
reg = <0x14400000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
};
Board specific part:
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <2560>;
samsung,vl-row = <1600>;
samsung,vl-width = <2560>;
samsung,vl-height = <1600>;
samsung,vl-clkp;
samsung,vl-dp;
samsung,vl-bpix = <4>;
samsung,vl-hspw = <32>;
samsung,vl-hbpd = <80>;
samsung,vl-hfpd = <48>;
samsung,vl-vspw = <6>;
samsung,vl-vbpd = <37>;
samsung,vl-vfpd = <3>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,winid = <3>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
};

47
drivers/crypto/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# Copyright (c) 2013 Samsung Electronics Co., Ltd.
# http://www.samsung.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB := $(obj)libcrypto.o
COBJS-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
########################################################################

126
drivers/crypto/ace_sha.c Normal file
View File

@ -0,0 +1,126 @@
/*
* Advanced Crypto Engine - SHA Firmware
* Copyright (c) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <common.h>
#include <sha256.h>
#include <sha1.h>
#include <asm/errno.h>
#include "ace_sha.h"
/* SHA1 value for the message of zero length */
static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
0xAF, 0xD8, 0x07, 0x09};
/* SHA256 value for the message of zero length */
static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
unsigned char *pout, unsigned int hash_type)
{
unsigned int i, reg, len;
unsigned int *pdigest;
struct exynos_ace_sfr *ace_sha_reg =
(struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
if (buf_len == 0) {
/* ACE H/W cannot compute hash value for empty string */
if (hash_type == ACE_SHA_TYPE_SHA1)
memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
else
memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
return 0;
}
/* Flush HRDMA */
writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
/* Set byte swap of data in */
writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
&ace_sha_reg->hash_byteswap);
/* Select Hash input mux as external source */
reg = readl(&ace_sha_reg->fc_fifoctrl);
reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
writel(reg, &ace_sha_reg->fc_fifoctrl);
/* Set Hash as SHA1 or SHA256 and start Hash engine */
reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
reg |= ACE_HASH_STARTBIT_ON;
writel(reg, &ace_sha_reg->hash_control);
/* Enable FIFO mode */
writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
/* Set message length */
writel(buf_len, &ace_sha_reg->hash_msgsize_low);
writel(0, &ace_sha_reg->hash_msgsize_high);
/* Set HRDMA */
writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
writel(buf_len, &ace_sha_reg->fc_hrdmal);
while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
ACE_HASH_MSGDONE_OFF) {
/*
* PRNG error bit goes HIGH if a PRNG request occurs without
* a complete seed setup. We are using this bit to check h/w
* fault because proper setup is not expected in that case.
*/
if ((readl(&ace_sha_reg->hash_status)
& ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
return -EBUSY;
}
/* Clear MSG_DONE bit */
writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
/* Read hash result */
pdigest = (unsigned int *)pout;
len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
for (i = 0; i < len / 4; i++)
pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
/* Clear HRDMA pending bit */
writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
return 0;
}
void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
unsigned char *pout, unsigned int chunk_size)
{
if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
debug("ACE was not setup properly or it is faulty\n");
}
void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
unsigned char *pout, unsigned int chunk_size)
{
if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
debug("ACE was not setup properly or it is faulty\n");
}

325
drivers/crypto/ace_sha.h Normal file
View File

@ -0,0 +1,325 @@
/*
* Header file for Advanced Crypto Engine - SFR definitions
*
* Copyright (c) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __ACE_SHA_H
#define __ACE_SHA_H
struct exynos_ace_sfr {
unsigned int fc_intstat; /* base + 0 */
unsigned int fc_intenset;
unsigned int fc_intenclr;
unsigned int fc_intpend;
unsigned int fc_fifostat;
unsigned int fc_fifoctrl;
unsigned int fc_global;
unsigned int res1;
unsigned int fc_brdmas;
unsigned int fc_brdmal;
unsigned int fc_brdmac;
unsigned int res2;
unsigned int fc_btdmas;
unsigned int fc_btdmal;
unsigned int fc_btdmac;
unsigned int res3;
unsigned int fc_hrdmas;
unsigned int fc_hrdmal;
unsigned int fc_hrdmac;
unsigned int res4;
unsigned int fc_pkdmas;
unsigned int fc_pkdmal;
unsigned int fc_pkdmac;
unsigned int fc_pkdmao;
unsigned char res5[0x1a0];
unsigned int aes_control; /* base + 0x200 */
unsigned int aes_status;
unsigned char res6[0x8];
unsigned int aes_in[4];
unsigned int aes_out[4];
unsigned int aes_iv[4];
unsigned int aes_cnt[4];
unsigned char res7[0x30];
unsigned int aes_key[8];
unsigned char res8[0x60];
unsigned int tdes_control; /* base + 0x300 */
unsigned int tdes_status;
unsigned char res9[0x8];
unsigned int tdes_key[6];
unsigned int tdes_iv[2];
unsigned int tdes_in[2];
unsigned int tdes_out[2];
unsigned char res10[0xc0];
unsigned int hash_control; /* base + 0x400 */
unsigned int hash_control2;
unsigned int hash_fifo_mode;
unsigned int hash_byteswap;
unsigned int hash_status;
unsigned char res11[0xc];
unsigned int hash_msgsize_low;
unsigned int hash_msgsize_high;
unsigned int hash_prelen_low;
unsigned int hash_prelen_high;
unsigned int hash_in[16];
unsigned int hash_key_in[16];
unsigned int hash_iv[8];
unsigned char res12[0x30];
unsigned int hash_result[8];
unsigned char res13[0x20];
unsigned int hash_seed[8];
unsigned int hash_prng[8];
unsigned char res14[0x180];
unsigned int pka_sfr[5]; /* base + 0x700 */
};
/* ACE_FC_INT */
#define ACE_FC_PKDMA (1 << 0)
#define ACE_FC_HRDMA (1 << 1)
#define ACE_FC_BTDMA (1 << 2)
#define ACE_FC_BRDMA (1 << 3)
#define ACE_FC_PRNG_ERROR (1 << 4)
#define ACE_FC_MSG_DONE (1 << 5)
#define ACE_FC_PRNG_DONE (1 << 6)
#define ACE_FC_PARTIAL_DONE (1 << 7)
/* ACE_FC_FIFOSTAT */
#define ACE_FC_PKFIFO_EMPTY (1 << 0)
#define ACE_FC_PKFIFO_FULL (1 << 1)
#define ACE_FC_HRFIFO_EMPTY (1 << 2)
#define ACE_FC_HRFIFO_FULL (1 << 3)
#define ACE_FC_BTFIFO_EMPTY (1 << 4)
#define ACE_FC_BTFIFO_FULL (1 << 5)
#define ACE_FC_BRFIFO_EMPTY (1 << 6)
#define ACE_FC_BRFIFO_FULL (1 << 7)
/* ACE_FC_FIFOCTRL */
#define ACE_FC_SELHASH_MASK (3 << 0)
#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */
#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */
#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */
#define ACE_FC_SELBC_MASK (1 << 2)
#define ACE_FC_SELBC_AES (0 << 2)
#define ACE_FC_SELBC_DES (1 << 2)
/* ACE_FC_GLOBAL */
#define ACE_FC_SSS_RESET (1 << 0)
#define ACE_FC_DMA_RESET (1 << 1)
#define ACE_FC_AES_RESET (1 << 2)
#define ACE_FC_DES_RESET (1 << 3)
#define ACE_FC_HASH_RESET (1 << 4)
#define ACE_FC_AXI_ENDIAN_MASK (3 << 6)
#define ACE_FC_AXI_ENDIAN_LE (0 << 6)
#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6)
#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6)
/* Feed control - BRDMA control */
#define ACE_FC_BRDMACFLUSH_OFF (0 << 0)
#define ACE_FC_BRDMACFLUSH_ON (1 << 0)
#define ACE_FC_BRDMACSWAP_ON (1 << 1)
#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2)
#define ACE_FC_BRDMACARPROT_OFS 2
#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5)
#define ACE_FC_BRDMACARCACHE_OFS 5
/* Feed control - BTDMA control */
#define ACE_FC_BTDMACFLUSH_OFF (0 << 0)
#define ACE_FC_BTDMACFLUSH_ON (1 << 0)
#define ACE_FC_BTDMACSWAP_ON (1 << 1)
#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2)
#define ACE_FC_BTDMACAWPROT_OFS 2
#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5)
#define ACE_FC_BTDMACAWCACHE_OFS 5
/* Feed control - HRDMA control */
#define ACE_FC_HRDMACFLUSH_OFF (0 << 0)
#define ACE_FC_HRDMACFLUSH_ON (1 << 0)
#define ACE_FC_HRDMACSWAP_ON (1 << 1)
#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2)
#define ACE_FC_HRDMACARPROT_OFS 2
#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5)
#define ACE_FC_HRDMACARCACHE_OFS 5
/* Feed control - PKDMA control */
#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3)
#define ACE_FC_PKDMACDESEND_ON (1 << 2)
#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1)
#define ACE_FC_PKDMACFLUSH_ON (1 << 0)
/* Feed control - PKDMA offset */
#define ACE_FC_SRAMOFFSET_MASK 0xfff
/* AES control */
#define ACE_AES_MODE_MASK (1 << 0)
#define ACE_AES_MODE_ENC (0 << 0)
#define ACE_AES_MODE_DEC (1 << 0)
#define ACE_AES_OPERMODE_MASK (3 << 1)
#define ACE_AES_OPERMODE_ECB (0 << 1)
#define ACE_AES_OPERMODE_CBC (1 << 1)
#define ACE_AES_OPERMODE_CTR (2 << 1)
#define ACE_AES_FIFO_MASK (1 << 3)
#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */
#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */
#define ACE_AES_KEYSIZE_MASK (3 << 4)
#define ACE_AES_KEYSIZE_128 (0 << 4)
#define ACE_AES_KEYSIZE_192 (1 << 4)
#define ACE_AES_KEYSIZE_256 (2 << 4)
#define ACE_AES_KEYCNGMODE_MASK (1 << 6)
#define ACE_AES_KEYCNGMODE_OFF (0 << 6)
#define ACE_AES_KEYCNGMODE_ON (1 << 6)
#define ACE_AES_SWAP_MASK (0x1f << 7)
#define ACE_AES_SWAPKEY_OFF (0 << 7)
#define ACE_AES_SWAPKEY_ON (1 << 7)
#define ACE_AES_SWAPCNT_OFF (0 << 8)
#define ACE_AES_SWAPCNT_ON (1 << 8)
#define ACE_AES_SWAPIV_OFF (0 << 9)
#define ACE_AES_SWAPIV_ON (1 << 9)
#define ACE_AES_SWAPDO_OFF (0 << 10)
#define ACE_AES_SWAPDO_ON (1 << 10)
#define ACE_AES_SWAPDI_OFF (0 << 11)
#define ACE_AES_SWAPDI_ON (1 << 11)
#define ACE_AES_COUNTERSIZE_MASK (3 << 12)
#define ACE_AES_COUNTERSIZE_128 (0 << 12)
#define ACE_AES_COUNTERSIZE_64 (1 << 12)
#define ACE_AES_COUNTERSIZE_32 (2 << 12)
#define ACE_AES_COUNTERSIZE_16 (3 << 12)
/* AES status */
#define ACE_AES_OUTRDY_MASK (1 << 0)
#define ACE_AES_OUTRDY_OFF (0 << 0)
#define ACE_AES_OUTRDY_ON (1 << 0)
#define ACE_AES_INRDY_MASK (1 << 1)
#define ACE_AES_INRDY_OFF (0 << 1)
#define ACE_AES_INRDY_ON (1 << 1)
#define ACE_AES_BUSY_MASK (1 << 2)
#define ACE_AES_BUSY_OFF (0 << 2)
#define ACE_AES_BUSY_ON (1 << 2)
/* TDES control */
#define ACE_TDES_MODE_MASK (1 << 0)
#define ACE_TDES_MODE_ENC (0 << 0)
#define ACE_TDES_MODE_DEC (1 << 0)
#define ACE_TDES_OPERMODE_MASK (1 << 1)
#define ACE_TDES_OPERMODE_ECB (0 << 1)
#define ACE_TDES_OPERMODE_CBC (1 << 1)
#define ACE_TDES_SEL_MASK (3 << 3)
#define ACE_TDES_SEL_DES (0 << 3)
#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */
#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */
#define ACE_TDES_FIFO_MASK (1 << 5)
#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */
#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */
#define ACE_TDES_SWAP_MASK (0xf << 6)
#define ACE_TDES_SWAPKEY_OFF (0 << 6)
#define ACE_TDES_SWAPKEY_ON (1 << 6)
#define ACE_TDES_SWAPIV_OFF (0 << 7)
#define ACE_TDES_SWAPIV_ON (1 << 7)
#define ACE_TDES_SWAPDO_OFF (0 << 8)
#define ACE_TDES_SWAPDO_ON (1 << 8)
#define ACE_TDES_SWAPDI_OFF (0 << 9)
#define ACE_TDES_SWAPDI_ON (1 << 9)
/* TDES status */
#define ACE_TDES_OUTRDY_MASK (1 << 0)
#define ACE_TDES_OUTRDY_OFF (0 << 0)
#define ACE_TDES_OUTRDY_ON (1 << 0)
#define ACE_TDES_INRDY_MASK (1 << 1)
#define ACE_TDES_INRDY_OFF (0 << 1)
#define ACE_TDES_INRDY_ON (1 << 1)
#define ACE_TDES_BUSY_MASK (1 << 2)
#define ACE_TDES_BUSY_OFF (0 << 2)
#define ACE_TDES_BUSY_ON (1 << 2)
/* Hash control */
#define ACE_HASH_ENGSEL_MASK (0xf << 0)
#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0)
#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0)
#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0)
#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0)
#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0)
#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0)
#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0)
#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0)
#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0)
#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0)
#define ACE_HASH_ENGSEL_PRNG (0x8 << 0)
#define ACE_HASH_STARTBIT_ON (1 << 4)
#define ACE_HASH_USERIV_EN (1 << 5)
#define ACE_HASH_PAUSE_ON (1 << 0)
/* Hash control - FIFO mode */
#define ACE_HASH_FIFO_MASK (1 << 0)
#define ACE_HASH_FIFO_OFF (0 << 0)
#define ACE_HASH_FIFO_ON (1 << 0)
/* Hash control - byte swap */
#define ACE_HASH_SWAP_MASK (0xf << 0)
#define ACE_HASH_SWAPKEY_OFF (0 << 0)
#define ACE_HASH_SWAPKEY_ON (1 << 0)
#define ACE_HASH_SWAPIV_OFF (0 << 1)
#define ACE_HASH_SWAPIV_ON (1 << 1)
#define ACE_HASH_SWAPDO_OFF (0 << 2)
#define ACE_HASH_SWAPDO_ON (1 << 2)
#define ACE_HASH_SWAPDI_OFF (0 << 3)
#define ACE_HASH_SWAPDI_ON (1 << 3)
/* Hash status */
#define ACE_HASH_BUFRDY_MASK (1 << 0)
#define ACE_HASH_BUFRDY_OFF (0 << 0)
#define ACE_HASH_BUFRDY_ON (1 << 0)
#define ACE_HASH_SEEDSETTING_MASK (1 << 1)
#define ACE_HASH_SEEDSETTING_OFF (0 << 1)
#define ACE_HASH_SEEDSETTING_ON (1 << 1)
#define ACE_HASH_PRNGBUSY_MASK (1 << 2)
#define ACE_HASH_PRNGBUSY_OFF (0 << 2)
#define ACE_HASH_PRNGBUSY_ON (1 << 2)
#define ACE_HASH_PARTIALDONE_MASK (1 << 4)
#define ACE_HASH_PARTIALDONE_OFF (0 << 4)
#define ACE_HASH_PARTIALDONE_ON (1 << 4)
#define ACE_HASH_PRNGDONE_MASK (1 << 5)
#define ACE_HASH_PRNGDONE_OFF (0 << 5)
#define ACE_HASH_PRNGDONE_ON (1 << 5)
#define ACE_HASH_MSGDONE_MASK (1 << 6)
#define ACE_HASH_MSGDONE_OFF (0 << 6)
#define ACE_HASH_MSGDONE_ON (1 << 6)
#define ACE_HASH_PRNGERROR_MASK (1 << 7)
#define ACE_HASH_PRNGERROR_OFF (0 << 7)
#define ACE_HASH_PRNGERROR_ON (1 << 7)
#define ACE_SHA_TYPE_SHA1 1
#define ACE_SHA_TYPE_SHA256 2
/**
* Computes hash value of input pbuf using ACE
*
* @param in_addr A pointer to the input buffer
* @param bufleni Byte length of input buffer
* @param out_addr A pointer to the output buffer. When complete
* 32 bytes are copied to pout[0]...pout[31]. Thus, a user
* should allocate at least 32 bytes at pOut in advance.
* @param hash_type SHA1 or SHA256
*
* @return 0 on Success, -1 on Failure (Timeout)
*/
int ace_sha_hash_digest(const uchar * in_addr, uint buflen,
uchar * out_addr, uint hash_type);
#endif

2
drivers/spi/exynos_spi.c
View File

@ -358,6 +358,7 @@ static inline struct exynos_spi *get_spi_base(int dev_index)
* @param bus SPI bus structure to fill with information
* @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
*/
#ifdef CONFIG_OF_CONTROL
static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
{
bus->node = node;
@ -413,6 +414,7 @@ static int process_nodes(const void *blob, int node_list[], int count)
return 0;
}
#endif
/* Sadly there is no error return from this function */
void spi_init(void)

76
drivers/video/exynos_dp.c
View File

@ -27,11 +27,21 @@
#include <asm/arch/cpu.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/dp.h>
#include <fdtdec.h>
#include <libfdt.h>
#include "exynos_dp_lowlevel.h"
DECLARE_GLOBAL_DATA_PTR;
static struct exynos_dp_platform_data *dp_pd;
void __exynos_set_dp_phy(unsigned int onoff)
{
}
void exynos_set_dp_phy(unsigned int onoff)
__attribute__((weak, alias("__exynos_set_dp_phy")));
static void exynos_dp_disp_info(struct edp_disp_info *disp_info)
{
disp_info->h_total = disp_info->h_res + disp_info->h_sync_width +
@ -853,6 +863,62 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info)
return ret;
}
#ifdef CONFIG_OF_CONTROL
int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info)
{
unsigned int node = fdtdec_next_compatible(blob, 0,
COMPAT_SAMSUNG_EXYNOS5_DP);
if (node <= 0) {
debug("exynos_dp: Can't get device node for dp\n");
return -ENODEV;
}
edp_info->disp_info.h_res = fdtdec_get_int(blob, node,
"samsung,h-res", 0);
edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node,
"samsung,h-sync-width", 0);
edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node,
"samsung,h-back-porch", 0);
edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node,
"samsung,h-front-porch", 0);
edp_info->disp_info.v_res = fdtdec_get_int(blob, node,
"samsung,v-res", 0);
edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node,
"samsung,v-sync-width", 0);
edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node,
"samsung,v-back-porch", 0);
edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node,
"samsung,v-front-porch", 0);
edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node,
"samsung,v-sync-rate", 0);
edp_info->lt_info.lt_status = fdtdec_get_int(blob, node,
"samsung,lt-status", 0);
edp_info->video_info.master_mode = fdtdec_get_int(blob, node,
"samsung,master-mode", 0);
edp_info->video_info.bist_mode = fdtdec_get_int(blob, node,
"samsung,bist-mode", 0);
edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node,
"samsung,bist-pattern", 0);
edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node,
"samsung,h-sync-polarity", 0);
edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node,
"samsung,v-sync-polarity", 0);
edp_info->video_info.interlaced = fdtdec_get_int(blob, node,
"samsung,interlaced", 0);
edp_info->video_info.color_space = fdtdec_get_int(blob, node,
"samsung,color-space", 0);
edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node,
"samsung,dynamic-range", 0);
edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node,
"samsung,ycbcr-coeff", 0);
edp_info->video_info.color_depth = fdtdec_get_int(blob, node,
"samsung,color-depth", 0);
return 0;
}
#endif
unsigned int exynos_init_dp(void)
{
unsigned int ret;
@ -864,16 +930,22 @@ unsigned int exynos_init_dp(void)
return -EFAULT;
}
#ifdef CONFIG_OF_CONTROL
if (exynos_dp_parse_dt(gd->fdt_blob, edp_info))
debug("unable to parse DP DT node\n");
#else
edp_info = dp_pd->edp_dev_info;
if (edp_info == NULL) {
debug("failed to get edp_info data.\n");
return -EFAULT;
}
#endif
exynos_dp_set_base_addr();
exynos_dp_disp_info(&edp_info->disp_info);
if (dp_pd->phy_enable)
dp_pd->phy_enable(1);
exynos_set_dp_phy(1);
ret = exynos_dp_init_dp();
if (ret != EXYNOS_DP_SUCCESS) {

69
drivers/video/exynos_dp_lowlevel.c
View File

@ -25,11 +25,34 @@
#include <asm/arch/cpu.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/dp.h>
#include <fdtdec.h>
#include <libfdt.h>
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
struct exynos_dp *dp_regs;
void exynos_dp_set_base_addr(void)
{
#ifdef CONFIG_OF_CONTROL
unsigned int node = fdtdec_next_compatible(gd->fdt_blob,
0, COMPAT_SAMSUNG_EXYNOS5_DP);
if (node <= 0)
debug("exynos_dp: Can't get device node for dp\n");
dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob,
node, "reg");
if (dp_regs == NULL)
debug("Can't get the DP base address\n");
#else
dp_regs = (struct exynos_dp *)samsung_get_base_dp();
#endif
}
static void exynos_dp_enable_video_input(unsigned int enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl1);
reg &= ~VIDEO_EN_MASK;
@ -47,7 +70,6 @@ void exynos_dp_enable_video_bist(unsigned int enable)
{
/*enable video bist*/
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl4);
reg &= ~VIDEO_BIST_MASK;
@ -64,7 +86,6 @@ void exynos_dp_enable_video_bist(unsigned int enable)
void exynos_dp_enable_video_mute(unsigned int enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl1);
reg &= ~(VIDEO_MUTE_MASK);
@ -80,7 +101,6 @@ void exynos_dp_enable_video_mute(unsigned int enable)
static void exynos_dp_init_analog_param(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/*
* Set termination
@ -129,7 +149,6 @@ static void exynos_dp_init_analog_param(void)
static void exynos_dp_init_interrupt(void)
{
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Set interrupt registers to initial states */
/*
@ -158,7 +177,6 @@ static void exynos_dp_init_interrupt(void)
void exynos_dp_reset(void)
{
unsigned int reg_func_1;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/*dp tx sw reset*/
writel(RESET_DP_TX, &dp_regs->tx_sw_reset);
@ -186,7 +204,6 @@ void exynos_dp_reset(void)
void exynos_dp_enable_sw_func(unsigned int enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->func_en1);
reg &= ~(SW_FUNC_EN_N);
@ -202,7 +219,6 @@ void exynos_dp_enable_sw_func(unsigned int enable)
unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->phy_pd);
switch (block) {
@ -256,7 +272,6 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable)
unsigned int exynos_dp_get_pll_lock_status(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->debug_ctl);
@ -269,7 +284,6 @@ unsigned int exynos_dp_get_pll_lock_status(void)
static void exynos_dp_set_pll_power(unsigned int enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->pll_ctl);
reg &= ~(DP_PLL_PD);
@ -285,7 +299,6 @@ int exynos_dp_init_analog_func(void)
int ret = EXYNOS_DP_SUCCESS;
unsigned int retry_cnt = 10;
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/*Power On All Analog block */
exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE);
@ -335,7 +348,6 @@ int exynos_dp_init_analog_func(void)
void exynos_dp_init_hpd(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear interrupts releated to Hot Plug Dectect */
reg = HOTPLUG_CHG | HPD_LOST | PLUG;
@ -354,7 +366,6 @@ void exynos_dp_init_hpd(void)
static inline void exynos_dp_reset_aux(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Disable AUX channel module */
reg = readl(&dp_regs->func_en2);
@ -367,7 +378,6 @@ static inline void exynos_dp_reset_aux(void)
void exynos_dp_init_aux(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear inerrupts related to AUX channel */
reg = RPLY_RECEIV | AUX_ERR;
@ -395,7 +405,6 @@ void exynos_dp_init_aux(void)
void exynos_dp_config_interrupt(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* 0: mask, 1: unmask */
reg = COMMON_INT_MASK_1;
@ -419,7 +428,6 @@ void exynos_dp_config_interrupt(void)
unsigned int exynos_dp_get_plug_in_status(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->sys_ctl3);
if (reg & HPD_STATUS)
@ -449,7 +457,6 @@ unsigned int exynos_dp_start_aux_transaction(void)
unsigned int reg;
unsigned int ret = 0;
unsigned int retry_cnt;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Enable AUX CH operation */
reg = readl(&dp_regs->aux_ch_ctl2);
@ -498,7 +505,6 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr,
unsigned char data)
{
unsigned int reg, ret;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
@ -539,7 +545,6 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr,
{
unsigned int reg;
int retval;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
@ -583,7 +588,6 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr,
unsigned int cur_data_idx;
unsigned int retry_cnt;
unsigned int ret = 0;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
@ -649,7 +653,6 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr,
unsigned int cur_data_idx;
unsigned int retry_cnt;
unsigned int ret = 0;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear AUX CH data buffer */
reg = BUF_CLR;
@ -711,7 +714,6 @@ int exynos_dp_select_i2c_device(unsigned int device_addr,
{
unsigned int reg;
int retval;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Set EDID device address */
reg = device_addr;
@ -746,7 +748,6 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr,
unsigned int reg;
int i;
int retval;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
for (i = 0; i < 10; i++) {
/* Clear AUX CH data buffer */
@ -790,7 +791,6 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
unsigned int cur_data_idx;
unsigned int defer = 0;
int retval = 0;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
for (i = 0; i < count; i += 16) { /* use 16 burst */
for (j = 0; j < 100; j++) {
@ -854,7 +854,6 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr,
void exynos_dp_reset_macro(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->phy_test);
reg |= MACRO_RST;
@ -870,7 +869,6 @@ void exynos_dp_reset_macro(void)
void exynos_dp_set_link_bandwidth(unsigned char bwtype)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = (unsigned int)bwtype;
@ -883,7 +881,6 @@ unsigned char exynos_dp_get_link_bandwidth(void)
{
unsigned char ret;
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->link_bw_set);
ret = (unsigned char)reg;
@ -894,7 +891,6 @@ unsigned char exynos_dp_get_link_bandwidth(void)
void exynos_dp_set_lane_count(unsigned char count)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = (unsigned int)count;
@ -906,7 +902,6 @@ void exynos_dp_set_lane_count(unsigned char count)
unsigned int exynos_dp_get_lane_count(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->lane_count_set);
@ -915,7 +910,6 @@ unsigned int exynos_dp_get_lane_count(void)
unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
{
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
(unsigned int)&dp_regs->ln1_link_training_ctl,
@ -929,7 +923,6 @@ unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt)
void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val,
unsigned char lanecnt)
{
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
(unsigned int)&dp_regs->ln1_link_training_ctl,
@ -944,7 +937,6 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
{
unsigned char i;
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
unsigned int reg_list[DP_LANE_CNT_4] = {
(unsigned int)&dp_regs->ln0_link_training_ctl,
(unsigned int)&dp_regs->ln1_link_training_ctl,
@ -967,7 +959,6 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt)
void exynos_dp_set_training_pattern(unsigned int pattern)
{
unsigned int reg = 0;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
switch (pattern) {
case PRBS7:
@ -996,7 +987,6 @@ void exynos_dp_set_training_pattern(unsigned int pattern)
void exynos_dp_enable_enhanced_mode(unsigned char enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->sys_ctl4);
reg &= ~ENHANCED;
@ -1010,7 +1000,6 @@ void exynos_dp_enable_enhanced_mode(unsigned char enable)
void exynos_dp_enable_scrambling(unsigned int enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->training_ptn_set);
reg &= ~(SCRAMBLING_DISABLE);
@ -1024,7 +1013,6 @@ void exynos_dp_enable_scrambling(unsigned int enable)
int exynos_dp_init_video(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */
reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
@ -1040,7 +1028,6 @@ int exynos_dp_init_video(void)
void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Video Slave mode setting */
reg = readl(&dp_regs->func_en1);
@ -1074,7 +1061,6 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info)
void exynos_dp_set_video_color_format(struct edp_video_info *video_info)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Configure the input color depth, color space, dynamic range */
reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) |
@ -1097,7 +1083,6 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
unsigned int reg;
unsigned int bist_type = 0;
struct edp_video_info video_info = edp_info->video_info;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* For master mode, you don't need to set the video format */
if (video_info.master_mode == 0) {
@ -1186,7 +1171,6 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info)
unsigned int exynos_dp_is_slave_video_stream_clock_on(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Update Video stream clk detect status */
reg = readl(&dp_regs->sys_ctl1);
@ -1206,7 +1190,6 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
unsigned int n_value)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
if (type == REGISTER_M) {
reg = readl(&dp_regs->sys_ctl4);
@ -1235,7 +1218,6 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value,
void exynos_dp_set_video_timing_mode(unsigned int type)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->video_ctl10);
reg &= ~FORMAT_SEL;
@ -1249,7 +1231,6 @@ void exynos_dp_set_video_timing_mode(unsigned int type)
void exynos_dp_enable_video_master(unsigned int enable)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
reg = readl(&dp_regs->soc_general_ctl);
if (enable) {
@ -1266,7 +1247,6 @@ void exynos_dp_enable_video_master(unsigned int enable)
void exynos_dp_start_video(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Enable Video input and disable Mute */
reg = readl(&dp_regs->video_ctl1);
@ -1277,7 +1257,6 @@ void exynos_dp_start_video(void)
unsigned int exynos_dp_is_video_stream_on(void)
{
unsigned int reg;
struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp();
/* Update STRM_VALID */
reg = readl(&dp_regs->sys_ctl3);

1
drivers/video/exynos_dp_lowlevel.h
View File

@ -76,5 +76,6 @@ void exynos_dp_set_video_timing_mode(unsigned int type);
void exynos_dp_enable_video_master(unsigned int enable);
void exynos_dp_start_video(void);
unsigned int exynos_dp_is_video_stream_on(void);
void exynos_dp_set_base_addr(void);
#endif /* _EXYNOS_DP_LOWLEVEL_H */

230
drivers/video/exynos_fb.c
View File

@ -23,6 +23,8 @@
#include <config.h>
#include <common.h>
#include <lcd.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
@ -30,9 +32,12 @@
#include <asm/arch/mipi_dsim.h>
#include <asm/arch/dp_info.h>
#include <asm/arch/system.h>
#include <asm-generic/errno.h>
#include "exynos_fb.h"
DECLARE_GLOBAL_DATA_PTR;
int lcd_line_length;
int lcd_color_fg;
int lcd_color_bg;
@ -45,6 +50,20 @@ short console_row;
static unsigned int panel_width, panel_height;
/*
* board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs
* panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve
* FB memory at a very early stage, i.e even before exynos_fimd_parse_dt()
* is called. So, we are forced to statically assign it.
*/
#ifdef CONFIG_OF_CONTROL
vidinfo_t panel_info = {
.vl_col = LCD_XRES,
.vl_row = LCD_YRES,
.vl_bpix = LCD_COLOR16,
};
#endif
static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid)
{
unsigned long palette_size;
@ -93,47 +112,226 @@ static void draw_logo(void)
}
#endif
void __exynos_cfg_lcd_gpio(void)
{
}
void exynos_cfg_lcd_gpio(void)
__attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
void __exynos_backlight_on(unsigned int onoff)
{
}
void exynos_backlight_on(unsigned int onoff)
__attribute__((weak, alias("__exynos_cfg_lcd_gpio")));
void __exynos_reset_lcd(void)
{
}
void exynos_reset_lcd(void)
__attribute__((weak, alias("__exynos_reset_lcd")));
void __exynos_lcd_power_on(void)
{
}
void exynos_lcd_power_on(void)
__attribute__((weak, alias("__exynos_lcd_power_on")));
void __exynos_cfg_ldo(void)
{
}
void exynos_cfg_ldo(void)
__attribute__((weak, alias("__exynos_cfg_ldo")));
void __exynos_enable_ldo(unsigned int onoff)
{
}
void exynos_enable_ldo(unsigned int onoff)
__attribute__((weak, alias("__exynos_enable_ldo")));
void __exynos_backlight_reset(void)
{
}
void exynos_backlight_reset(void)
__attribute__((weak, alias("__exynos_backlight_reset")));
static void lcd_panel_on(vidinfo_t *vid)
{
udelay(vid->init_delay);
if (vid->backlight_reset)
vid->backlight_reset();
exynos_backlight_reset();
if (vid->cfg_gpio)
vid->cfg_gpio();
exynos_cfg_lcd_gpio();
if (vid->lcd_power_on)
vid->lcd_power_on();
exynos_lcd_power_on();
udelay(vid->power_on_delay);
if (vid->dp_enabled)
exynos_init_dp();
if (vid->reset_lcd) {
vid->reset_lcd();
udelay(vid->reset_delay);
}
exynos_reset_lcd();
if (vid->backlight_on)
vid->backlight_on(1);
udelay(vid->reset_delay);
if (vid->cfg_ldo)
vid->cfg_ldo();
exynos_backlight_on(1);
if (vid->enable_ldo)
vid->enable_ldo(1);
exynos_cfg_ldo();
exynos_enable_ldo(1);
if (vid->mipi_enabled)
exynos_mipi_dsi_init();
}
#ifdef CONFIG_OF_CONTROL
int exynos_fimd_parse_dt(const void *blob)
{
unsigned int node;
node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0) {
debug("exynos_fb: Can't get device node for fimd\n");
return -ENODEV;
}
panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0);
if (panel_info.vl_col == 0) {
debug("Can't get XRES\n");
return -ENXIO;
}
panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0);
if (panel_info.vl_row == 0) {
debug("Can't get YRES\n");
return -ENXIO;
}
panel_info.vl_width = fdtdec_get_int(blob, node,
"samsung,vl-width", 0);
panel_info.vl_height = fdtdec_get_int(blob, node,
"samsung,vl-height", 0);
panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0);
if (panel_info.vl_freq == 0) {
debug("Can't get refresh rate\n");
return -ENXIO;
}
if (fdtdec_get_bool(blob, node, "samsung,vl-clkp"))
panel_info.vl_clkp = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-oep"))
panel_info.vl_oep = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-hsp"))
panel_info.vl_hsp = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-vsp"))
panel_info.vl_vsp = CONFIG_SYS_LOW;
if (fdtdec_get_bool(blob, node, "samsung,vl-dp"))
panel_info.vl_dp = CONFIG_SYS_LOW;
panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0);
if (panel_info.vl_bpix == 0) {
debug("Can't get bits per pixel\n");
return -ENXIO;
}
panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0);
if (panel_info.vl_hspw == 0) {
debug("Can't get hsync width\n");
return -ENXIO;
}
panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0);
if (panel_info.vl_hfpd == 0) {
debug("Can't get right margin\n");
return -ENXIO;
}
panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node,
"samsung,vl-hbpd", 0);
if (panel_info.vl_hbpd == 0) {
debug("Can't get left margin\n");
return -ENXIO;
}
panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node,
"samsung,vl-vspw", 0);
if (panel_info.vl_vspw == 0) {
debug("Can't get vsync width\n");
return -ENXIO;
}
panel_info.vl_vfpd = fdtdec_get_int(blob, node,
"samsung,vl-vfpd", 0);
if (panel_info.vl_vfpd == 0) {
debug("Can't get lower margin\n");
return -ENXIO;
}
panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0);
if (panel_info.vl_vbpd == 0) {
debug("Can't get upper margin\n");
return -ENXIO;
}
panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node,
"samsung,vl-cmd-allow-len", 0);
panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0);
panel_info.init_delay = fdtdec_get_int(blob, node,
"samsung,init-delay", 0);
panel_info.power_on_delay = fdtdec_get_int(blob, node,
"samsung,power-on-delay", 0);
panel_info.reset_delay = fdtdec_get_int(blob, node,
"samsung,reset-delay", 0);
panel_info.interface_mode = fdtdec_get_int(blob, node,
"samsung,interface-mode", 0);
panel_info.mipi_enabled = fdtdec_get_int(blob, node,
"samsung,mipi-enabled", 0);
panel_info.dp_enabled = fdtdec_get_int(blob, node,
"samsung,dp-enabled", 0);
panel_info.cs_setup = fdtdec_get_int(blob, node,
"samsung,cs-setup", 0);
panel_info.wr_setup = fdtdec_get_int(blob, node,
"samsung,wr-setup", 0);
panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0);
panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0);
panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0);
if (panel_info.logo_on) {
panel_info.logo_width = fdtdec_get_int(blob, node,
"samsung,logo-width", 0);
panel_info.logo_height = fdtdec_get_int(blob, node,
"samsung,logo-height", 0);
panel_info.logo_addr = fdtdec_get_int(blob, node,
"samsung,logo-addr", 0);
}
panel_info.rgb_mode = fdtdec_get_int(blob, node,
"samsung,rgb-mode", 0);
panel_info.pclk_name = fdtdec_get_int(blob, node,
"samsung,pclk-name", 0);
panel_info.sclk_div = fdtdec_get_int(blob, node,
"samsung,sclk-div", 0);
panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node,
"samsung,dual-lcd-enabled", 0);
return 0;
}
#endif
void lcd_ctrl_init(void *lcdbase)
{
set_system_display_ctrl();
set_lcd_clk();
#ifdef CONFIG_OF_CONTROL
if (exynos_fimd_parse_dt(gd->fdt_blob))
debug("Can't get proper panel info\n");
#endif
/* initialize parameters which is specific to panel. */
init_panel_info(&panel_info);

44
drivers/video/exynos_fimd.c
View File

@ -25,13 +25,18 @@
#include <asm/io.h>
#include <lcd.h>
#include <div64.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <asm/arch/clk.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include "exynos_fb.h"
DECLARE_GLOBAL_DATA_PTR;
static unsigned long *lcd_base_addr;
static vidinfo_t *pvid;
static struct exynos_fb *fimd_ctrl;
void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
u_long palette_size)
@ -41,8 +46,6 @@ void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
static void exynos_fimd_set_dualrgb(unsigned int enabled)
{
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
unsigned int cfg = 0;
if (enabled) {
@ -59,9 +62,6 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled)
static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
{
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
unsigned int cfg = 0;
if (enabled)
@ -73,8 +73,6 @@ static void exynos_fimd_set_dp_clkcon(unsigned int enabled)
static void exynos_fimd_set_par(unsigned int win_id)
{
unsigned int cfg = 0;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
/* set window control */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
@ -126,8 +124,6 @@ static void exynos_fimd_set_par(unsigned int win_id)
static void exynos_fimd_set_buffer_address(unsigned int win_id)
{
unsigned long start_addr, end_addr;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
start_addr = (unsigned long)lcd_base_addr;
end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) *
@ -144,8 +140,6 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid)
unsigned int cfg = 0, div = 0, remainder, remainder_div;
unsigned long pixel_clock;
unsigned long long src_clock;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
if (pvid->dual_lcd_enabled) {
pixel_clock = pvid->vl_freq *
@ -197,8 +191,6 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid)
void exynos_set_trigger(void)
{
unsigned int cfg = 0;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->trigcon);
@ -211,8 +203,6 @@ int exynos_is_i80_frame_done(void)
{
unsigned int cfg = 0;
int status;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->trigcon);
@ -226,8 +216,6 @@ int exynos_is_i80_frame_done(void)
static void exynos_fimd_lcd_on(void)
{
unsigned int cfg = 0;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
/* display on */
cfg = readl(&fimd_ctrl->vidcon0);
@ -238,8 +226,6 @@ static void exynos_fimd_lcd_on(void)
static void exynos_fimd_window_on(unsigned int win_id)
{
unsigned int cfg = 0;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
/* enable window */
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
@ -256,8 +242,6 @@ static void exynos_fimd_window_on(unsigned int win_id)
void exynos_fimd_lcd_off(void)
{
unsigned int cfg = 0;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
cfg = readl(&fimd_ctrl->vidcon0);
cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE);
@ -267,8 +251,6 @@ void exynos_fimd_lcd_off(void)
void exynos_fimd_window_off(unsigned int win_id)
{
unsigned int cfg = 0;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
cfg = readl((unsigned int)&fimd_ctrl->wincon0 +
EXYNOS_WINCON(win_id));
@ -286,8 +268,20 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
{
unsigned int cfg = 0, rgb_mode;
unsigned int offset;
struct exynos_fb *fimd_ctrl =
(struct exynos_fb *)samsung_get_base_fimd();
#ifdef CONFIG_OF_CONTROL
unsigned int node;
node = fdtdec_next_compatible(gd->fdt_blob,
0, COMPAT_SAMSUNG_EXYNOS_FIMD);
if (node <= 0)
debug("exynos_fb: Can't get device node for fimd\n");
fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob,
node, "reg");
if (fimd_ctrl == NULL)
debug("Can't get the FIMD base address\n");
#endif
fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
offset = exynos_fimd_get_base_offset();

8
include/configs/exynos5250-dt.h
View File

@ -46,6 +46,10 @@
/* Keep L2 Cache Disabled */
#define CONFIG_SYS_DCACHE_OFF
/* Enable ACE acceleration for SHA1 and SHA256 */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_SHA_HW_ACCEL
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x43E00000
@ -114,6 +118,7 @@
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NET
#define CONFIG_CMD_HASH
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
@ -325,4 +330,7 @@
#define LCD_BPP LCD_COLOR16
#endif
/* Enable Time Command */
#define CONFIG_CMD_TIME
#endif /* __CONFIG_H */

1
include/configs/trats.h
View File

@ -199,6 +199,7 @@
"splfile=falcon.bin\0" \
"spl_export=" \
"setexpr spl_imgsize ${splsize} + 8 ;" \
"setenv spl_imgsize 0x${spl_imgsize};" \
"setexpr spl_imgaddr ${spladdr} - 8 ;" \
"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \

2
include/fdtdec.h
View File

@ -87,6 +87,8 @@ enum fdt_compat_id {
COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */
COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */
COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */
COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */
COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */
COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */
COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */
COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */

50
include/hw_sha.h Normal file
View File

@ -0,0 +1,50 @@
/*
* Header file for SHA hardware acceleration
*
* Copyright (c) 2012 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __HW_SHA_H
#define __HW_SHA_H
/**
* Computes hash value of input pbuf using h/w acceleration
*
* @param in_addr A pointer to the input buffer
* @param bufleni Byte length of input buffer
* @param out_addr A pointer to the output buffer. When complete
* 32 bytes are copied to pout[0]...pout[31]. Thus, a user
* should allocate at least 32 bytes at pOut in advance.
* @param chunk_size chunk size for sha256
*/
void hw_sha256(const uchar * in_addr, uint buflen,
uchar * out_addr, uint chunk_size);
/**
* Computes hash value of input pbuf using h/w acceleration
*
* @param in_addr A pointer to the input buffer
* @param bufleni Byte length of input buffer
* @param out_addr A pointer to the output buffer. When complete
* 32 bytes are copied to pout[0]...pout[31]. Thus, a user
* should allocate at least 32 bytes at pOut in advance.
* @param chunk_size chunk_size for sha1
*/
void hw_sha1(const uchar * in_addr, uint buflen,
uchar * out_addr, uint chunk_size);
#endif

9
include/lcd.h
View File

@ -234,15 +234,6 @@ typedef struct vidinfo {
u_char vl_vbpd; /* Wait end of frame */
u_char vl_cmd_allow_len; /* Wait end of frame */
void (*cfg_gpio)(void);
void (*backlight_on)(unsigned int onoff);
void (*reset_lcd)(void);
void (*lcd_power_on)(void);
void (*cfg_ldo)(void);
void (*enable_ldo)(unsigned int onoff);
void (*mipi_power)(void);
void (*backlight_reset)(void);
unsigned int win_id;
unsigned int init_delay;
unsigned int power_on_delay;

2
lib/fdtdec.c
View File

@ -60,6 +60,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"),
COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"),
COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"),
COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"),
COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"),
COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"),
COMPAT(GENERIC_SPI_FLASH, "spi-flash"),
COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"),