rockchip: Bring in RK3036 device tree file includes and bindings
Since rk3036 device tree file still in reviewing, bring it from https://patchwork.kernel.org/patch/7203371/ and add some aliases we need in uboot Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
huang lin
Simon Glass
parent
a51dbebf30
commit
fc0fada094
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@ -0,0 +1,427 @@
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/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3036-cru.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "rockchip,rk3036";
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interrupt-parent = <&gic>;
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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i2c1 = &i2c1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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mmc0 = &emmc;
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};
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memory {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3036-smp";
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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resets = <&cru SRST_CORE0>;
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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resets = <&cru SRST_CORE1>;
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};
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@20078000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20078000 0x4000>;
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arm,pl330-broken-no-flushp;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC2>;
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clock-names = "apb_pclk";
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};
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3036-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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};
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uart0: serial@20060000 {
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compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
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reg = <0x20060000 0x100>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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};
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uart1: serial@20064000 {
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compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
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reg = <0x20064000 0x100>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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};
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uart2: serial@20068000 {
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compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
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reg = <0x20068000 0x100>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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};
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pwm0: pwm@20050000 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20050000 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm1: pwm@20050010 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20050010 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm2: pwm@20050020 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20050020 0x10>;
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#pwm-cells = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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pwm3: pwm@20050030 {
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compatible = "rockchip,rk2928-pwm";
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reg = <0x20050030 0x10>;
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#pwm-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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status = "disabled";
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};
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sram: sram@10080000 {
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compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
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reg = <0x10080000 0x2000>;
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};
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gic: interrupt-controller@10139000 {
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compatible = "arm,gic-400";
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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reg = <0x10139000 0x1000>,
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<0x1013a000 0x1000>,
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<0x1013c000 0x2000>,
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<0x1013e000 0x2000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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grf: syscon@20008000 {
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compatible = "rockchip,rk3036-grf", "syscon";
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reg = <0x20008000 0x1000>;
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};
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usb_otg: usb@10180000 {
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compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
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reg = <0x10180000 0x40000>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG0>;
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clock-names = "otg";
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dr_mode = "otg";
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g-np-tx-fifo-size = <16>;
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g-rx-fifo-size = <275>;
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g-tx-fifo-size = <256 128 128 64 64 32>;
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g-use-dma;
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status = "disabled";
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};
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usb_host: usb@101c0000 {
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compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
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reg = <0x101c0000 0x40000>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_OTG1>;
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clock-names = "otg";
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dr_mode = "host";
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status = "disabled";
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};
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emmc: dwmmc@1021c000 {
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compatible = "rockchip,rk3288-dw-mshc";
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clock-frequency = <37500000>;
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clock-freq-min-max = <400000 37500000>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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dmas = <&pdma 12>;
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dma-names = "rx-tx";
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fifo-depth = <0x100>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x1021c000 0x4000>;
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broken-cd;
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bus-width = <8>;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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disable-wp;
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non-removable;
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num-slots = <1>;
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default-sample-phase = <158>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3036-pinctrl";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@2007c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2007c000 0x100>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@20084000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20084000 0x100>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg-pull-up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg-pull-down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg-pull-none {
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bias-disable;
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};
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emmc {
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/*
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* We run eMMC at max speed; bump up drive strength.
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* We also have external pulls, so disable the internal ones.
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*/
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emmc_clk: emmc-clk {
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rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
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};
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emmc_bus8: emmc-bus8 {
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rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
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<1 25 RK_FUNC_2 &pcfg_pull_none>,
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<1 26 RK_FUNC_2 &pcfg_pull_none>,
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<1 27 RK_FUNC_2 &pcfg_pull_none>;
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/*
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<1 28 RK_FUNC_2 &pcfg_pull_up>,
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<1 29 RK_FUNC_2 &pcfg_pull_up>,
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<1 30 RK_FUNC_2 &pcfg_pull_up>,
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<1 31 RK_FUNC_2 &pcfg_pull_up>;
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*/
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};
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
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<0 17 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
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<2 23 RK_FUNC_1 &pcfg_pull_none>;
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};
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/* no rts / cts for uart1 */
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
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<1 19 RK_FUNC_2 &pcfg_pull_none>;
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};
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/* no rts / cts for uart2 */
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};
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pwm0 {
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pwm0_pin: pwm0-pin {
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rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_pin: pwm1-pin {
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rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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pwm2 {
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pwm2_pin: pwm2-pin {
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rockchip,pins = <0 1 2 &pcfg_pull_none>;
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};
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};
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pwm3 {
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pwm3_pin: pwm3-pin {
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rockchip,pins = <0 27 1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
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<0 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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};
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i2c1: i2c@20056000 {
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compatible = "rockchip,rk3288-i2c";
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reg = <0x20056000 0x1000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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};
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@ -0,0 +1,186 @@
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/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_GPLL 3
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#define ARMCLK 4
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/* sclk gates (special clocks) */
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#define SCLK_GPU 64
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#define SCLK_SPI 65
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_NANDC 76
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_I2S 82
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#define SCLK_SPDIF 83
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_OTGPHY0 93
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#define SCLK_LCDC 100
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#define SCLK_HDMI 109
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||||
#define SCLK_HEVC 111
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_PVTM_VIDEO 125
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF 152
|
||||
#define SCLK_SFC 160
|
||||
|
||||
#define DCLK_LCDC 190
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC2 194
|
||||
#define ACLK_LCDC 197
|
||||
#define ACLK_VIO 203
|
||||
#define ACLK_VCODEC 208
|
||||
#define ACLK_CPU 209
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_SPI 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_HDMI 360
|
||||
#define PCLK_CPU 362
|
||||
#define PCLK_PERI 363
|
||||
#define PCLK_DDRUPCTL 364
|
||||
#define PCLK_WDT 368
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_OTG0 449
|
||||
#define HCLK_OTG1 450
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_I2S 462
|
||||
#define HCLK_LCDC 465
|
||||
#define HCLK_ROM 467
|
||||
#define HCLK_VIO_BUS 472
|
||||
#define HCLK_VCODEC 476
|
||||
#define HCLK_CPU 477
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0 0
|
||||
#define SRST_CORE1 1
|
||||
#define SRST_CORE0_DBG 4
|
||||
#define SRST_CORE1_DBG 5
|
||||
#define SRST_CORE0_POR 8
|
||||
#define SRST_CORE1_POR 9
|
||||
#define SRST_L2C 12
|
||||
#define SRST_TOPDBG 13
|
||||
#define SRST_STRC_SYS_A 14
|
||||
#define SRST_PD_CORE_NIU 15
|
||||
|
||||
#define SRST_TIMER2 16
|
||||
#define SRST_CPUSYS_H 17
|
||||
#define SRST_AHB2APB_H 19
|
||||
#define SRST_TIMER3 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_PERI_NIU 23
|
||||
#define SRST_I2S 24
|
||||
#define SRST_DDR_PLL 25
|
||||
#define SRST_GPU_DLL 26
|
||||
#define SRST_TIMER0 27
|
||||
#define SRST_TIMER1 28
|
||||
#define SRST_CORE_DLL 29
|
||||
#define SRST_EFUSE_P 30
|
||||
#define SRST_ACODEC_P 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_SFC 47
|
||||
|
||||
#define SRST_PWM0 48
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_SYS 52
|
||||
#define SRST_GRF 55
|
||||
#define SRST_PERIPHSYS_A 57
|
||||
#define SRST_PERIPHSYS_H 58
|
||||
#define SRST_PERIPHSYS_P 59
|
||||
#define SRST_CPU_PERI 61
|
||||
#define SRST_EMEM_PERI 62
|
||||
#define SRST_USB_PERI 63
|
||||
|
||||
#define SRST_DMA2 64
|
||||
#define SRST_MAC 66
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG0 69
|
||||
#define SRST_OTGC0 71
|
||||
#define SRST_USBOTG1 72
|
||||
#define SRST_OTGC1 74
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_MMC0 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI0 84
|
||||
#define SRST_WDT 86
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_BUS_H 99
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_USBPOR 105
|
||||
|
||||
#define SRST_VCODEC_A 112
|
||||
#define SRST_VCODEC_H 113
|
||||
#define SRST_VIO1_A 114
|
||||
#define SRST_HEVC 115
|
||||
#define SRST_VCODEC_NIU_A 116
|
||||
#define SRST_LCDC1_A 117
|
||||
#define SRST_LCDC1_H 118
|
||||
#define SRST_LCDC1_D 119
|
||||
#define SRST_GPU 120
|
||||
#define SRST_GPU_NIU_A 122
|
||||
|
||||
#define SRST_DBG_P 131
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue