ARM: uniphier: clean up UMC init for PXs2 SoC
Just cosmetic changes: - Rename prefix DMPHY_ to MPHY_ for consistency - Move UMC parameters below for complete decouple of PHY and UMC - Remove redundant whitespaces Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
bf52091786
commit
fada9eafe1
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@ -55,13 +55,13 @@ static void dump_loop(void (*callback)(void __iomem *))
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nr_ch = get_nr_ch();
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for (ch = 0; ch < nr_ch; ch++) {
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dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
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dx_base = get_phy_base(ch) + MPHY_DX_BASE;
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nr_dx = get_nr_datx8(ch);
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for (dx = 0; dx < nr_dx; dx++) {
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printf("CH%dDX%d:", ch, dx);
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(*callback)(dx_base);
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dx_base += DMPHY_DX_STRIDE;
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dx_base += MPHY_DX_STRIDE;
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printf("\n");
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}
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}
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@ -79,25 +79,25 @@ static void zq_dump(void)
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nr_ch = get_nr_ch();
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for (ch = 0; ch < nr_ch; ch++) {
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zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
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zq_base = get_phy_base(ch) + MPHY_ZQ_BASE;
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nr_zq = 3;
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for (zq = 0; zq < nr_zq; zq++) {
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printf("CH%dZQ%d:", ch, zq);
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dr = readl(zq_base + DMPHY_ZQ_DR);
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dr = readl(zq_base + MPHY_ZQ_DR);
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for (i = 0; i < 4; i++) {
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printf(FS PRINTF_FORMAT, dr & 0x7f);
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dr >>= 7;
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}
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pr = readl(zq_base + DMPHY_ZQ_PR);
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pr = readl(zq_base + MPHY_ZQ_PR);
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for (i = 0; i < 2; i++) {
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printf(FS PRINTF_FORMAT, pr & 0xf);
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pr >>= 4;
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}
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zq_base += DMPHY_ZQ_STRIDE;
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zq_base += MPHY_ZQ_STRIDE;
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printf("\n");
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}
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}
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@ -105,12 +105,12 @@ static void zq_dump(void)
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static void __wbdl_dump(void __iomem *dx_base)
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{
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print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
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print_bdl(dx_base + MPHY_DX_BDLR0, 4);
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print_bdl(dx_base + MPHY_DX_BDLR1, 4);
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print_bdl(dx_base + MPHY_DX_BDLR2, 2);
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printf(FS "(+" PRINTF_FORMAT ")",
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readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
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readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
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}
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static void wbdl_dump(void)
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@ -123,15 +123,15 @@ static void wbdl_dump(void)
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static void __rbdl_dump(void __iomem *dx_base)
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{
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print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
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print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
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print_bdl(dx_base + MPHY_DX_BDLR3, 4);
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print_bdl(dx_base + MPHY_DX_BDLR4, 4);
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print_bdl(dx_base + MPHY_DX_BDLR5, 1);
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
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(readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
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(readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
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}
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static void rbdl_dump(void)
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@ -145,8 +145,8 @@ static void rbdl_dump(void)
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static void __wld_dump(void __iomem *dx_base)
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{
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int rank;
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u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
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u32 gtr = readl(dx_base + DMPHY_DX_GTR);
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u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
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u32 gtr = readl(dx_base + MPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
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@ -168,8 +168,8 @@ static void wld_dump(void)
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static void __dqsgd_dump(void __iomem *dx_base)
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{
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int rank;
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u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
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u32 gtr = readl(dx_base + DMPHY_DX_GTR);
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u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
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u32 gtr = readl(dx_base + MPHY_DX_GTR);
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for (rank = 0; rank < 4; rank++) {
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u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
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@ -190,7 +190,7 @@ static void dqsgd_dump(void)
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static void __mdl_dump(void __iomem *dx_base)
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{
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int i;
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u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
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u32 mdl = readl(dx_base + MPHY_DX_MDLR);
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for (i = 0; i < 3; i++)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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@ -205,16 +205,16 @@ static void mdl_dump(void)
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}
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#define REG_DUMP(x) \
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{ int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst; \
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{ int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
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printf("%3d: %-10s: %p : %08x\n", \
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ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
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ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
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#define DX_REG_DUMP(dx, x) \
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{ int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) + \
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DMPHY_DX_## x; \
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{ int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
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MPHY_DX_## x; \
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void __iomem *reg = phy_base + ofst; \
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
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ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
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static void reg_dump(void)
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{
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@ -1,146 +1,146 @@
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/*
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* UniPhier DDR MultiPHY registers
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2015-2017 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef ARCH_DDRMPHY_REGS_H
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#define ARCH_DDRMPHY_REGS_H
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#ifndef UNIPHIER_DDRMPHY_REGS_H
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#define UNIPHIER_DDRMPHY_REGS_H
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#include <linux/bitops.h>
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#define DMPHY_SHIFT 2
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#define MPHY_SHIFT 2
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#define DMPHY_RIDR (0x000 << DMPHY_SHIFT)
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#define DMPHY_PIR (0x001 << DMPHY_SHIFT)
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#define DMPHY_PIR_INIT BIT(0) /* Initialization Trigger */
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#define DMPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
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#define DMPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
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#define DMPHY_PIR_DCAL BIT(5) /* DDL Calibration */
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#define DMPHY_PIR_PHYRST BIT(6) /* PHY Reset */
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#define DMPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
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#define DMPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
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#define DMPHY_PIR_WL BIT(9) /* Write Leveling */
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#define DMPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
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#define DMPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
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#define DMPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
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#define DMPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
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#define DMPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
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#define DMPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
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#define DMPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
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#define DMPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
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#define DMPHY_PGCR0 (0x002 << DMPHY_SHIFT)
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#define DMPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
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#define DMPHY_PGCR1 (0x003 << DMPHY_SHIFT)
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#define DMPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
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#define DMPHY_PGCR2 (0x004 << DMPHY_SHIFT)
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#define DMPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
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#define DMPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
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#define DMPHY_PGCR3 (0x005 << DMPHY_SHIFT)
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#define DMPHY_PGSR0 (0x006 << DMPHY_SHIFT)
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#define DMPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
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#define DMPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
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#define DMPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
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#define DMPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
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#define DMPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
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#define DMPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
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#define DMPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
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#define DMPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
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#define DMPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
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#define DMPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
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#define DMPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
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#define DMPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
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#define DMPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
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#define DMPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
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#define DMPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
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#define DMPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
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#define DMPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
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#define DMPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
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#define DMPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
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#define DMPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
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#define DMPHY_PGSR1 (0x007 << DMPHY_SHIFT)
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#define DMPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
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#define DMPHY_PLLCR (0x008 << DMPHY_SHIFT)
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#define DMPHY_PTR0 (0x009 << DMPHY_SHIFT)
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#define DMPHY_PTR1 (0x00A << DMPHY_SHIFT)
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#define DMPHY_PTR2 (0x00B << DMPHY_SHIFT)
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#define DMPHY_PTR3 (0x00C << DMPHY_SHIFT)
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#define DMPHY_PTR4 (0x00D << DMPHY_SHIFT)
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#define DMPHY_ACMDLR (0x00E << DMPHY_SHIFT)
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#define DMPHY_ACLCDLR (0x00F << DMPHY_SHIFT)
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#define DMPHY_ACBDLR0 (0x010 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR1 (0x011 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR2 (0x012 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR3 (0x013 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR4 (0x014 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR5 (0x015 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR6 (0x016 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR7 (0x017 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR8 (0x018 << DMPHY_SHIFT)
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#define DMPHY_ACBDLR9 (0x019 << DMPHY_SHIFT)
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#define DMPHY_ACIOCR0 (0x01A << DMPHY_SHIFT)
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#define DMPHY_ACIOCR1 (0x01B << DMPHY_SHIFT)
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#define DMPHY_ACIOCR2 (0x01C << DMPHY_SHIFT)
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#define DMPHY_ACIOCR3 (0x01D << DMPHY_SHIFT)
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#define DMPHY_ACIOCR4 (0x01E << DMPHY_SHIFT)
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#define DMPHY_ACIOCR5 (0x01F << DMPHY_SHIFT)
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#define DMPHY_DXCCR (0x020 << DMPHY_SHIFT)
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#define DMPHY_DSGCR (0x021 << DMPHY_SHIFT)
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#define DMPHY_DCR (0x022 << DMPHY_SHIFT)
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#define DMPHY_DTPR0 (0x023 << DMPHY_SHIFT)
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#define DMPHY_DTPR1 (0x024 << DMPHY_SHIFT)
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#define DMPHY_DTPR2 (0x025 << DMPHY_SHIFT)
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#define DMPHY_DTPR3 (0x026 << DMPHY_SHIFT)
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#define DMPHY_MR0 (0x027 << DMPHY_SHIFT)
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#define DMPHY_MR1 (0x028 << DMPHY_SHIFT)
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#define DMPHY_MR2 (0x029 << DMPHY_SHIFT)
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#define DMPHY_MR3 (0x02A << DMPHY_SHIFT)
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#define DMPHY_ODTCR (0x02B << DMPHY_SHIFT)
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#define DMPHY_DTCR (0x02C << DMPHY_SHIFT)
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#define DMPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
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#define DMPHY_DTCR_RANKEN_MASK (0xf << (DMPHY_DTCR_RANKEN_SHIFT))
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#define DMPHY_DTAR0 (0x02D << DMPHY_SHIFT)
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#define DMPHY_DTAR1 (0x02E << DMPHY_SHIFT)
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#define DMPHY_DTAR2 (0x02F << DMPHY_SHIFT)
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#define DMPHY_DTAR3 (0x030 << DMPHY_SHIFT)
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#define DMPHY_DTDR0 (0x031 << DMPHY_SHIFT)
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#define DMPHY_DTDR1 (0x032 << DMPHY_SHIFT)
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#define DMPHY_DTEDR0 (0x033 << DMPHY_SHIFT)
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#define DMPHY_DTEDR1 (0x034 << DMPHY_SHIFT)
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#define DMPHY_ZQCR (0x090 << DMPHY_SHIFT)
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#define DMPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
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#define DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
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#define MPHY_RIDR (0x000 << MPHY_SHIFT)
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#define MPHY_PIR (0x001 << MPHY_SHIFT)
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#define MPHY_PIR_INIT BIT(0) /* Initialization Trigger */
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#define MPHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
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#define MPHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
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#define MPHY_PIR_DCAL BIT(5) /* DDL Calibration */
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#define MPHY_PIR_PHYRST BIT(6) /* PHY Reset */
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#define MPHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
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#define MPHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
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#define MPHY_PIR_WL BIT(9) /* Write Leveling */
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#define MPHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
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#define MPHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
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#define MPHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
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#define MPHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
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#define MPHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
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#define MPHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
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#define MPHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
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#define MPHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
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#define MPHY_PGCR0 (0x002 << MPHY_SHIFT)
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#define MPHY_PGCR0_PHYFRST BIT(26) /* PHY FIFO Reset */
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#define MPHY_PGCR1 (0x003 << MPHY_SHIFT)
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#define MPHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
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#define MPHY_PGCR2 (0x004 << MPHY_SHIFT)
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#define MPHY_PGCR2_DUALCHN BIT(28) /* Dual Channel Configuration*/
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#define MPHY_PGCR2_ACPDDC BIT(29) /* AC Power-Down with Dual Ch*/
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#define MPHY_PGCR3 (0x005 << MPHY_SHIFT)
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#define MPHY_PGSR0 (0x006 << MPHY_SHIFT)
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#define MPHY_PGSR0_IDONE BIT(0) /* Initialization Done */
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#define MPHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
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#define MPHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
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#define MPHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
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#define MPHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
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#define MPHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
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#define MPHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
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#define MPHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
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#define MPHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
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#define MPHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
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#define MPHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
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#define MPHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
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#define MPHY_PGSR0_ZCERR BIT(20) /* Impedance Calib Error */
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#define MPHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
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#define MPHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
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#define MPHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
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#define MPHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
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#define MPHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
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#define MPHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
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#define MPHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
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#define MPHY_PGSR1 (0x007 << MPHY_SHIFT)
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#define MPHY_PGSR1_VTSTOP BIT(30) /* VT Stop */
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#define MPHY_PLLCR (0x008 << MPHY_SHIFT)
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#define MPHY_PTR0 (0x009 << MPHY_SHIFT)
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#define MPHY_PTR1 (0x00A << MPHY_SHIFT)
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#define MPHY_PTR2 (0x00B << MPHY_SHIFT)
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#define MPHY_PTR3 (0x00C << MPHY_SHIFT)
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#define MPHY_PTR4 (0x00D << MPHY_SHIFT)
|
||||
#define MPHY_ACMDLR (0x00E << MPHY_SHIFT)
|
||||
#define MPHY_ACLCDLR (0x00F << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR0 (0x010 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR1 (0x011 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR2 (0x012 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR3 (0x013 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR4 (0x014 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR5 (0x015 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR6 (0x016 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR7 (0x017 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR8 (0x018 << MPHY_SHIFT)
|
||||
#define MPHY_ACBDLR9 (0x019 << MPHY_SHIFT)
|
||||
#define MPHY_ACIOCR0 (0x01A << MPHY_SHIFT)
|
||||
#define MPHY_ACIOCR1 (0x01B << MPHY_SHIFT)
|
||||
#define MPHY_ACIOCR2 (0x01C << MPHY_SHIFT)
|
||||
#define MPHY_ACIOCR3 (0x01D << MPHY_SHIFT)
|
||||
#define MPHY_ACIOCR4 (0x01E << MPHY_SHIFT)
|
||||
#define MPHY_ACIOCR5 (0x01F << MPHY_SHIFT)
|
||||
#define MPHY_DXCCR (0x020 << MPHY_SHIFT)
|
||||
#define MPHY_DSGCR (0x021 << MPHY_SHIFT)
|
||||
#define MPHY_DCR (0x022 << MPHY_SHIFT)
|
||||
#define MPHY_DTPR0 (0x023 << MPHY_SHIFT)
|
||||
#define MPHY_DTPR1 (0x024 << MPHY_SHIFT)
|
||||
#define MPHY_DTPR2 (0x025 << MPHY_SHIFT)
|
||||
#define MPHY_DTPR3 (0x026 << MPHY_SHIFT)
|
||||
#define MPHY_MR0 (0x027 << MPHY_SHIFT)
|
||||
#define MPHY_MR1 (0x028 << MPHY_SHIFT)
|
||||
#define MPHY_MR2 (0x029 << MPHY_SHIFT)
|
||||
#define MPHY_MR3 (0x02A << MPHY_SHIFT)
|
||||
#define MPHY_ODTCR (0x02B << MPHY_SHIFT)
|
||||
#define MPHY_DTCR (0x02C << MPHY_SHIFT)
|
||||
#define MPHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
|
||||
#define MPHY_DTCR_RANKEN_MASK (0xf << (MPHY_DTCR_RANKEN_SHIFT))
|
||||
#define MPHY_DTAR0 (0x02D << MPHY_SHIFT)
|
||||
#define MPHY_DTAR1 (0x02E << MPHY_SHIFT)
|
||||
#define MPHY_DTAR2 (0x02F << MPHY_SHIFT)
|
||||
#define MPHY_DTAR3 (0x030 << MPHY_SHIFT)
|
||||
#define MPHY_DTDR0 (0x031 << MPHY_SHIFT)
|
||||
#define MPHY_DTDR1 (0x032 << MPHY_SHIFT)
|
||||
#define MPHY_DTEDR0 (0x033 << MPHY_SHIFT)
|
||||
#define MPHY_DTEDR1 (0x034 << MPHY_SHIFT)
|
||||
#define MPHY_ZQCR (0x090 << MPHY_SHIFT)
|
||||
#define MPHY_ZQCR_AVGEN BIT(16) /* Average Algorithm */
|
||||
#define MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE BIT(27) /* force VT update */
|
||||
/* ZQ */
|
||||
#define DMPHY_ZQ_BASE (0x091 << DMPHY_SHIFT)
|
||||
#define DMPHY_ZQ_STRIDE (0x004 << DMPHY_SHIFT)
|
||||
#define DMPHY_ZQ_PR (0x000 << DMPHY_SHIFT)
|
||||
#define DMPHY_ZQ_DR (0x001 << DMPHY_SHIFT)
|
||||
#define DMPHY_ZQ_SR (0x002 << DMPHY_SHIFT)
|
||||
#define MPHY_ZQ_BASE (0x091 << MPHY_SHIFT)
|
||||
#define MPHY_ZQ_STRIDE (0x004 << MPHY_SHIFT)
|
||||
#define MPHY_ZQ_PR (0x000 << MPHY_SHIFT)
|
||||
#define MPHY_ZQ_DR (0x001 << MPHY_SHIFT)
|
||||
#define MPHY_ZQ_SR (0x002 << MPHY_SHIFT)
|
||||
/* DATX8 */
|
||||
#define DMPHY_DX_BASE (0x0A0 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_STRIDE (0x020 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GCR0 (0x000 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
|
||||
#define DMPHY_DX_GCR0_WLRKEN_MASK (0xf << (DMPHY_DX_GCR0_WLRKEN_SHIFT))
|
||||
#define DMPHY_DX_GCR1 (0x001 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GCR2 (0x002 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GCR3 (0x003 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GSR0 (0x004 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GSR1 (0x005 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GSR2 (0x006 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR0 (0x007 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR1 (0x008 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR2 (0x009 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR3 (0x00A << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR4 (0x00B << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR5 (0x00C << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_BDLR6 (0x00D << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_LCDLR0 (0x00E << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_LCDLR1 (0x00F << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_LCDLR2 (0x010 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_MDLR (0x011 << DMPHY_SHIFT)
|
||||
#define DMPHY_DX_GTR (0x012 << DMPHY_SHIFT)
|
||||
#define MPHY_DX_BASE (0x0A0 << MPHY_SHIFT)
|
||||
#define MPHY_DX_STRIDE (0x020 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GCR0 (0x000 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GCR0_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
|
||||
#define MPHY_DX_GCR0_WLRKEN_MASK (0xf << (MPHY_DX_GCR0_WLRKEN_SHIFT))
|
||||
#define MPHY_DX_GCR1 (0x001 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GCR2 (0x002 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GCR3 (0x003 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GSR0 (0x004 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GSR1 (0x005 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GSR2 (0x006 << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR0 (0x007 << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR1 (0x008 << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR2 (0x009 << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR3 (0x00A << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR4 (0x00B << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR5 (0x00C << MPHY_SHIFT)
|
||||
#define MPHY_DX_BDLR6 (0x00D << MPHY_SHIFT)
|
||||
#define MPHY_DX_LCDLR0 (0x00E << MPHY_SHIFT)
|
||||
#define MPHY_DX_LCDLR1 (0x00F << MPHY_SHIFT)
|
||||
#define MPHY_DX_LCDLR2 (0x010 << MPHY_SHIFT)
|
||||
#define MPHY_DX_MDLR (0x011 << MPHY_SHIFT)
|
||||
#define MPHY_DX_GTR (0x012 << MPHY_SHIFT)
|
||||
|
||||
#endif /* ARCH_DDRMPHY_REGS_H */
|
||||
#endif /* UNIPHIER_DDRMPHY_REGS_H */
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ enum dram_size {
|
|||
DRAM_SZ_NR,
|
||||
};
|
||||
|
||||
/* PHY */
|
||||
static u32 ddrphy_pgcr2[DRAM_FREQ_NR] = {0x00FC7E5D, 0x00FC90AB};
|
||||
static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0EA09205, 0x10C0A6C6};
|
||||
static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x0DAC041B, 0x0FA104B1};
|
||||
|
|
@ -48,23 +49,6 @@ static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x000002a0, 0x000002a8};
|
|||
/* dependent on package and board design */
|
||||
static u32 ddrphy_acbdlr0[DRAM_CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
|
||||
|
||||
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
|
||||
/*
|
||||
* The ch2 is a different generation UMC core.
|
||||
* The register spec is different, unfortunately.
|
||||
*/
|
||||
static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
|
||||
static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
|
||||
static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
||||
{0x004A071D, 0x0078071D},
|
||||
{0x0055081E, 0x0089081E},
|
||||
};
|
||||
|
||||
static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
|
||||
/* The ch2 is different for some reason only hardware guys know... */
|
||||
static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
|
||||
static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
|
||||
|
||||
/* DDR multiPHY */
|
||||
static inline int ddrphy_get_rank(int dx)
|
||||
{
|
||||
|
|
@ -75,14 +59,14 @@ static void ddrphy_fifo_reset(void __iomem *phy_base)
|
|||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(phy_base + DMPHY_PGCR0);
|
||||
tmp &= ~DMPHY_PGCR0_PHYFRST;
|
||||
writel(tmp, phy_base + DMPHY_PGCR0);
|
||||
tmp = readl(phy_base + MPHY_PGCR0);
|
||||
tmp &= ~MPHY_PGCR0_PHYFRST;
|
||||
writel(tmp, phy_base + MPHY_PGCR0);
|
||||
|
||||
udelay(1);
|
||||
|
||||
tmp |= DMPHY_PGCR0_PHYFRST;
|
||||
writel(tmp, phy_base + DMPHY_PGCR0);
|
||||
tmp |= MPHY_PGCR0_PHYFRST;
|
||||
writel(tmp, phy_base + MPHY_PGCR0);
|
||||
|
||||
udelay(1);
|
||||
}
|
||||
|
|
@ -91,17 +75,17 @@ static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
|
|||
{
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(phy_base + DMPHY_PGCR1);
|
||||
tmp = readl(phy_base + MPHY_PGCR1);
|
||||
|
||||
if (enable)
|
||||
tmp &= ~DMPHY_PGCR1_INHVT;
|
||||
tmp &= ~MPHY_PGCR1_INHVT;
|
||||
else
|
||||
tmp |= DMPHY_PGCR1_INHVT;
|
||||
tmp |= MPHY_PGCR1_INHVT;
|
||||
|
||||
writel(tmp, phy_base + DMPHY_PGCR1);
|
||||
writel(tmp, phy_base + MPHY_PGCR1);
|
||||
|
||||
if (!enable) {
|
||||
while (!(readl(phy_base + DMPHY_PGSR1) & DMPHY_PGSR1_VTSTOP))
|
||||
while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP))
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
|
@ -110,18 +94,18 @@ static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
|
|||
{
|
||||
int dx;
|
||||
u32 lcdlr1, rdqsd;
|
||||
void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
|
||||
void __iomem *dx_base = phy_base + MPHY_DX_BASE;
|
||||
|
||||
ddrphy_vt_ctrl(phy_base, 0);
|
||||
|
||||
for (dx = 0; dx < nr_dx; dx++) {
|
||||
lcdlr1 = readl(dx_base + DMPHY_DX_LCDLR1);
|
||||
lcdlr1 = readl(dx_base + MPHY_DX_LCDLR1);
|
||||
rdqsd = (lcdlr1 >> 8) & 0xff;
|
||||
rdqsd = clamp(rdqsd + step, 0U, 0xffU);
|
||||
lcdlr1 = (lcdlr1 & ~(0xff << 8)) | (rdqsd << 8);
|
||||
writel(lcdlr1, dx_base + DMPHY_DX_LCDLR1);
|
||||
readl(dx_base + DMPHY_DX_LCDLR1); /* relax */
|
||||
dx_base += DMPHY_DX_STRIDE;
|
||||
writel(lcdlr1, dx_base + MPHY_DX_LCDLR1);
|
||||
readl(dx_base + MPHY_DX_LCDLR1); /* relax */
|
||||
dx_base += MPHY_DX_STRIDE;
|
||||
}
|
||||
|
||||
ddrphy_vt_ctrl(phy_base, 1);
|
||||
|
|
@ -129,14 +113,14 @@ static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step)
|
|||
|
||||
static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
|
||||
{
|
||||
void __iomem *dx_base = phy_base + DMPHY_DX_BASE;
|
||||
void __iomem *dx_base = phy_base + MPHY_DX_BASE;
|
||||
const int nr_dx = width / 8;
|
||||
int dx, rank;
|
||||
u32 gtr;
|
||||
int dgsl, dgsl_min = INT_MAX, dgsl_max = 0;
|
||||
|
||||
for (dx = 0; dx < nr_dx; dx++) {
|
||||
gtr = readl(dx_base + DMPHY_DX_GTR);
|
||||
gtr = readl(dx_base + MPHY_DX_GTR);
|
||||
for (rank = 0; rank < 4; rank++) {
|
||||
dgsl = gtr & 0x7;
|
||||
/* if dgsl is zero, this rank was not trained. skip. */
|
||||
|
|
@ -146,7 +130,7 @@ static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
|
|||
}
|
||||
gtr >>= 3;
|
||||
}
|
||||
dx_base += DMPHY_DX_STRIDE;
|
||||
dx_base += MPHY_DX_STRIDE;
|
||||
}
|
||||
|
||||
if (dgsl_min != dgsl_max)
|
||||
|
|
@ -165,86 +149,86 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
|
|||
|
||||
nr_dx = width / 8;
|
||||
|
||||
writel(DMPHY_PIR_ZCALBYP, phy_base + DMPHY_PIR);
|
||||
writel(MPHY_PIR_ZCALBYP, phy_base + MPHY_PIR);
|
||||
/*
|
||||
* Disable RGLVT bit (Read DQS Gating LCDL Delay VT Compensation)
|
||||
* to avoid read error issue.
|
||||
*/
|
||||
writel(0x07d81e37, phy_base + DMPHY_PGCR0);
|
||||
writel(0x0200c4e0, phy_base + DMPHY_PGCR1);
|
||||
writel(0x07d81e37, phy_base + MPHY_PGCR0);
|
||||
writel(0x0200c4e0, phy_base + MPHY_PGCR1);
|
||||
|
||||
tmp = ddrphy_pgcr2[freq];
|
||||
if (width >= 32)
|
||||
tmp |= DMPHY_PGCR2_DUALCHN | DMPHY_PGCR2_ACPDDC;
|
||||
writel(tmp, phy_base + DMPHY_PGCR2);
|
||||
tmp |= MPHY_PGCR2_DUALCHN | MPHY_PGCR2_ACPDDC;
|
||||
writel(tmp, phy_base + MPHY_PGCR2);
|
||||
|
||||
writel(ddrphy_ptr0[freq], phy_base + DMPHY_PTR0);
|
||||
writel(ddrphy_ptr1[freq], phy_base + DMPHY_PTR1);
|
||||
writel(0x00083def, phy_base + DMPHY_PTR2);
|
||||
writel(ddrphy_ptr3[freq], phy_base + DMPHY_PTR3);
|
||||
writel(ddrphy_ptr4[freq], phy_base + DMPHY_PTR4);
|
||||
writel(ddrphy_ptr0[freq], phy_base + MPHY_PTR0);
|
||||
writel(ddrphy_ptr1[freq], phy_base + MPHY_PTR1);
|
||||
writel(0x00083def, phy_base + MPHY_PTR2);
|
||||
writel(ddrphy_ptr3[freq], phy_base + MPHY_PTR3);
|
||||
writel(ddrphy_ptr4[freq], phy_base + MPHY_PTR4);
|
||||
|
||||
writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
|
||||
writel(ddrphy_acbdlr0[ch], phy_base + MPHY_ACBDLR0);
|
||||
|
||||
writel(0x55555555, phy_base + DMPHY_ACIOCR1);
|
||||
writel(0x00000000, phy_base + DMPHY_ACIOCR2);
|
||||
writel(0x55555555, phy_base + DMPHY_ACIOCR3);
|
||||
writel(0x00000000, phy_base + DMPHY_ACIOCR4);
|
||||
writel(0x00000055, phy_base + DMPHY_ACIOCR5);
|
||||
writel(0x00181aa4, phy_base + DMPHY_DXCCR);
|
||||
writel(0x55555555, phy_base + MPHY_ACIOCR1);
|
||||
writel(0x00000000, phy_base + MPHY_ACIOCR2);
|
||||
writel(0x55555555, phy_base + MPHY_ACIOCR3);
|
||||
writel(0x00000000, phy_base + MPHY_ACIOCR4);
|
||||
writel(0x00000055, phy_base + MPHY_ACIOCR5);
|
||||
writel(0x00181aa4, phy_base + MPHY_DXCCR);
|
||||
|
||||
writel(0x0024641e, phy_base + DMPHY_DSGCR);
|
||||
writel(0x0000040b, phy_base + DMPHY_DCR);
|
||||
writel(ddrphy_dtpr0[freq], phy_base + DMPHY_DTPR0);
|
||||
writel(ddrphy_dtpr1[freq], phy_base + DMPHY_DTPR1);
|
||||
writel(ddrphy_dtpr2[freq], phy_base + DMPHY_DTPR2);
|
||||
writel(ddrphy_dtpr3[freq], phy_base + DMPHY_DTPR3);
|
||||
writel(ddrphy_mr0[freq], phy_base + DMPHY_MR0);
|
||||
writel(0x00000006, phy_base + DMPHY_MR1);
|
||||
writel(ddrphy_mr2[freq], phy_base + DMPHY_MR2);
|
||||
writel(0x00000000, phy_base + DMPHY_MR3);
|
||||
writel(0x0024641e, phy_base + MPHY_DSGCR);
|
||||
writel(0x0000040b, phy_base + MPHY_DCR);
|
||||
writel(ddrphy_dtpr0[freq], phy_base + MPHY_DTPR0);
|
||||
writel(ddrphy_dtpr1[freq], phy_base + MPHY_DTPR1);
|
||||
writel(ddrphy_dtpr2[freq], phy_base + MPHY_DTPR2);
|
||||
writel(ddrphy_dtpr3[freq], phy_base + MPHY_DTPR3);
|
||||
writel(ddrphy_mr0[freq], phy_base + MPHY_MR0);
|
||||
writel(0x00000006, phy_base + MPHY_MR1);
|
||||
writel(ddrphy_mr2[freq], phy_base + MPHY_MR2);
|
||||
writel(0x00000000, phy_base + MPHY_MR3);
|
||||
|
||||
tmp = 0;
|
||||
for (dx = 0; dx < nr_dx; dx++)
|
||||
tmp |= BIT(DMPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
|
||||
writel(0x90003087 | tmp, phy_base + DMPHY_DTCR);
|
||||
tmp |= BIT(MPHY_DTCR_RANKEN_SHIFT + ddrphy_get_rank(dx));
|
||||
writel(0x90003087 | tmp, phy_base + MPHY_DTCR);
|
||||
|
||||
writel(0x00000000, phy_base + DMPHY_DTAR0);
|
||||
writel(0x00000008, phy_base + DMPHY_DTAR1);
|
||||
writel(0x00000010, phy_base + DMPHY_DTAR2);
|
||||
writel(0x00000018, phy_base + DMPHY_DTAR3);
|
||||
writel(0xdd22ee11, phy_base + DMPHY_DTDR0);
|
||||
writel(0x7788bb44, phy_base + DMPHY_DTDR1);
|
||||
writel(0x00000000, phy_base + MPHY_DTAR0);
|
||||
writel(0x00000008, phy_base + MPHY_DTAR1);
|
||||
writel(0x00000010, phy_base + MPHY_DTAR2);
|
||||
writel(0x00000018, phy_base + MPHY_DTAR3);
|
||||
writel(0xdd22ee11, phy_base + MPHY_DTDR0);
|
||||
writel(0x7788bb44, phy_base + MPHY_DTDR1);
|
||||
|
||||
/* impedance control settings */
|
||||
writel(0x04048900, phy_base + DMPHY_ZQCR);
|
||||
writel(0x04048900, phy_base + MPHY_ZQCR);
|
||||
|
||||
zq_base = phy_base + DMPHY_ZQ_BASE;
|
||||
zq_base = phy_base + MPHY_ZQ_BASE;
|
||||
for (zq = 0; zq < 4; zq++) {
|
||||
/*
|
||||
* board-dependent
|
||||
* PXS2: CH0ZQ0=0x5B, CH1ZQ0=0x5B, CH2ZQ0=0x59, others=0x5D
|
||||
*/
|
||||
writel(0x0007BB5D, zq_base + DMPHY_ZQ_PR);
|
||||
zq_base += DMPHY_ZQ_STRIDE;
|
||||
writel(0x0007BB5D, zq_base + MPHY_ZQ_PR);
|
||||
zq_base += MPHY_ZQ_STRIDE;
|
||||
}
|
||||
|
||||
/* DATX8 settings */
|
||||
dx_base = phy_base + DMPHY_DX_BASE;
|
||||
dx_base = phy_base + MPHY_DX_BASE;
|
||||
for (dx = 0; dx < 4; dx++) {
|
||||
tmp = readl(dx_base + DMPHY_DX_GCR0);
|
||||
tmp &= ~DMPHY_DX_GCR0_WLRKEN_MASK;
|
||||
tmp |= BIT(DMPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
|
||||
DMPHY_DX_GCR0_WLRKEN_MASK;
|
||||
writel(tmp, dx_base + DMPHY_DX_GCR0);
|
||||
tmp = readl(dx_base + MPHY_DX_GCR0);
|
||||
tmp &= ~MPHY_DX_GCR0_WLRKEN_MASK;
|
||||
tmp |= BIT(MPHY_DX_GCR0_WLRKEN_SHIFT + ddrphy_get_rank(dx)) &
|
||||
MPHY_DX_GCR0_WLRKEN_MASK;
|
||||
writel(tmp, dx_base + MPHY_DX_GCR0);
|
||||
|
||||
writel(0x00000000, dx_base + DMPHY_DX_GCR1);
|
||||
writel(0x00000000, dx_base + DMPHY_DX_GCR2);
|
||||
writel(0x00000000, dx_base + DMPHY_DX_GCR3);
|
||||
dx_base += DMPHY_DX_STRIDE;
|
||||
writel(0x00000000, dx_base + MPHY_DX_GCR1);
|
||||
writel(0x00000000, dx_base + MPHY_DX_GCR2);
|
||||
writel(0x00000000, dx_base + MPHY_DX_GCR3);
|
||||
dx_base += MPHY_DX_STRIDE;
|
||||
}
|
||||
|
||||
while (!(readl(phy_base + DMPHY_PGSR0) & DMPHY_PGSR0_IDONE))
|
||||
while (!(readl(phy_base + MPHY_PGSR0) & MPHY_PGSR0_IDONE))
|
||||
cpu_relax();
|
||||
|
||||
ddrphy_dqs_delay_fixup(phy_base, nr_dx, -4);
|
||||
|
|
@ -260,9 +244,9 @@ struct ddrphy_init_sequence {
|
|||
static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
|
||||
{
|
||||
"Impedance Calibration",
|
||||
DMPHY_PIR_ZCAL,
|
||||
DMPHY_PGSR0_ZCDONE,
|
||||
DMPHY_PGSR0_ZCERR,
|
||||
MPHY_PIR_ZCAL,
|
||||
MPHY_PGSR0_ZCDONE,
|
||||
MPHY_PGSR0_ZCERR,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
@ -270,8 +254,8 @@ static const struct ddrphy_init_sequence impedance_calibration_sequence[] = {
|
|||
static const struct ddrphy_init_sequence dram_init_sequence[] = {
|
||||
{
|
||||
"DRAM Initialization",
|
||||
DMPHY_PIR_DRAMRST | DMPHY_PIR_DRAMINIT,
|
||||
DMPHY_PGSR0_DIDONE,
|
||||
MPHY_PIR_DRAMRST | MPHY_PIR_DRAMINIT,
|
||||
MPHY_PGSR0_DIDONE,
|
||||
0,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
|
|
@ -280,45 +264,45 @@ static const struct ddrphy_init_sequence dram_init_sequence[] = {
|
|||
static const struct ddrphy_init_sequence training_sequence[] = {
|
||||
{
|
||||
"Write Leveling",
|
||||
DMPHY_PIR_WL,
|
||||
DMPHY_PGSR0_WLDONE,
|
||||
DMPHY_PGSR0_WLERR,
|
||||
MPHY_PIR_WL,
|
||||
MPHY_PGSR0_WLDONE,
|
||||
MPHY_PGSR0_WLERR,
|
||||
},
|
||||
{
|
||||
"Read DQS Gate Training",
|
||||
DMPHY_PIR_QSGATE,
|
||||
DMPHY_PGSR0_QSGDONE,
|
||||
DMPHY_PGSR0_QSGERR,
|
||||
MPHY_PIR_QSGATE,
|
||||
MPHY_PGSR0_QSGDONE,
|
||||
MPHY_PGSR0_QSGERR,
|
||||
},
|
||||
{
|
||||
"Write Leveling Adjustment",
|
||||
DMPHY_PIR_WLADJ,
|
||||
DMPHY_PGSR0_WLADONE,
|
||||
DMPHY_PGSR0_WLAERR,
|
||||
MPHY_PIR_WLADJ,
|
||||
MPHY_PGSR0_WLADONE,
|
||||
MPHY_PGSR0_WLAERR,
|
||||
},
|
||||
{
|
||||
"Read Bit Deskew",
|
||||
DMPHY_PIR_RDDSKW,
|
||||
DMPHY_PGSR0_RDDONE,
|
||||
DMPHY_PGSR0_RDERR,
|
||||
MPHY_PIR_RDDSKW,
|
||||
MPHY_PGSR0_RDDONE,
|
||||
MPHY_PGSR0_RDERR,
|
||||
},
|
||||
{
|
||||
"Write Bit Deskew",
|
||||
DMPHY_PIR_WRDSKW,
|
||||
DMPHY_PGSR0_WDDONE,
|
||||
DMPHY_PGSR0_WDERR,
|
||||
MPHY_PIR_WRDSKW,
|
||||
MPHY_PGSR0_WDDONE,
|
||||
MPHY_PGSR0_WDERR,
|
||||
},
|
||||
{
|
||||
"Read Eye Training",
|
||||
DMPHY_PIR_RDEYE,
|
||||
DMPHY_PGSR0_REDONE,
|
||||
DMPHY_PGSR0_REERR,
|
||||
MPHY_PIR_RDEYE,
|
||||
MPHY_PGSR0_REDONE,
|
||||
MPHY_PGSR0_REERR,
|
||||
},
|
||||
{
|
||||
"Write Eye Training",
|
||||
DMPHY_PIR_WREYE,
|
||||
DMPHY_PGSR0_WEDONE,
|
||||
DMPHY_PGSR0_WEERR,
|
||||
MPHY_PIR_WREYE,
|
||||
MPHY_PGSR0_WEDONE,
|
||||
MPHY_PGSR0_WEERR,
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
|
@ -328,8 +312,8 @@ static int __ddrphy_training(void __iomem *phy_base,
|
|||
{
|
||||
const struct ddrphy_init_sequence *s;
|
||||
u32 pgsr0;
|
||||
u32 init_flag = DMPHY_PIR_INIT;
|
||||
u32 done_flag = DMPHY_PGSR0_IDONE;
|
||||
u32 init_flag = MPHY_PIR_INIT;
|
||||
u32 done_flag = MPHY_PGSR0_IDONE;
|
||||
int timeout = 50000; /* 50 msec is long enough */
|
||||
#ifdef DISPLAY_ELAPSED_TIME
|
||||
ulong start = get_timer(0);
|
||||
|
|
@ -340,7 +324,7 @@ static int __ddrphy_training(void __iomem *phy_base,
|
|||
done_flag |= s->done_flag;
|
||||
}
|
||||
|
||||
writel(init_flag, phy_base + DMPHY_PIR);
|
||||
writel(init_flag, phy_base + MPHY_PIR);
|
||||
|
||||
do {
|
||||
if (--timeout < 0) {
|
||||
|
|
@ -349,7 +333,7 @@ static int __ddrphy_training(void __iomem *phy_base,
|
|||
return -ETIMEDOUT;
|
||||
}
|
||||
udelay(1);
|
||||
pgsr0 = readl(phy_base + DMPHY_PGSR0);
|
||||
pgsr0 = readl(phy_base + MPHY_PGSR0);
|
||||
} while ((pgsr0 & done_flag) != done_flag);
|
||||
|
||||
for (s = seq; s->description; s++) {
|
||||
|
|
@ -384,12 +368,12 @@ static int ddrphy_impedance_calibration(void __iomem *phy_base)
|
|||
udelay(1);
|
||||
|
||||
/* reflect ZQ settings and enable average algorithm*/
|
||||
tmp = readl(phy_base + DMPHY_ZQCR);
|
||||
tmp |= DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
|
||||
writel(tmp, phy_base + DMPHY_ZQCR);
|
||||
tmp &= ~DMPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
|
||||
tmp |= DMPHY_ZQCR_AVGEN;
|
||||
writel(tmp, phy_base + DMPHY_ZQCR);
|
||||
tmp = readl(phy_base + MPHY_ZQCR);
|
||||
tmp |= MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
|
||||
writel(tmp, phy_base + MPHY_ZQCR);
|
||||
tmp &= ~MPHY_ZQCR_FORCE_ZCAL_VT_UPDATE;
|
||||
tmp |= MPHY_ZQCR_AVGEN;
|
||||
writel(tmp, phy_base + MPHY_ZQCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -405,6 +389,23 @@ static int ddrphy_training(void __iomem *phy_base)
|
|||
}
|
||||
|
||||
/* UMC */
|
||||
static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x66DD131D, 0x77EE1722};
|
||||
/*
|
||||
* The ch2 is a different generation UMC core.
|
||||
* The register spec is different, unfortunately.
|
||||
*/
|
||||
static u32 umc_cmdctlb_ch01[DRAM_FREQ_NR] = {0x13E87C44, 0x18F88C44};
|
||||
static u32 umc_cmdctlb_ch2[DRAM_FREQ_NR] = {0x19E8DC44, 0x1EF8EC44};
|
||||
static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
||||
{0x004A071D, 0x0078071D},
|
||||
{0x0055081E, 0x0089081E},
|
||||
};
|
||||
|
||||
static u32 umc_spcctlb[] = {0x00FF000A, 0x00FF000B};
|
||||
/* The ch2 is different for some reason only hardware guys know... */
|
||||
static u32 umc_flowctla_ch01[] = {0x0800001E, 0x08000022};
|
||||
static u32 umc_flowctla_ch2[] = {0x0800001E, 0x0800001E};
|
||||
|
||||
static void umc_set_system_latency(void __iomem *dc_base, int phy_latency)
|
||||
{
|
||||
u32 val;
|
||||
|
|
|
|||
Loading…
Reference in New Issue