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Initial revision

This commit is contained in:
wdenk 2002-08-26 22:36:39 +00:00
parent 67c4f48a49
commit f8cac651b3
18 changed files with 4704 additions and 0 deletions
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162
board/bmw/bmw.c Normal file
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/*
* (C) Copyright 2002
* James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <malloc.h>
#include <devices.h>
#include <syscall.h>
#include <net.h>
#include <version.h>
#include <dtt.h>
#include <mpc824x.h>
#include <asm/processor.h>
#include <linux/mtd/doc2000.h>
#include "bmw.h"
#include "m48t59y.h"
#include <pci.h>
int checkboard(void)
{
ulong busfreq = get_bus_freq(0);
char buf[32];
puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
printf("Built: %s at %s\n", __DATE__ , __TIME__ );
/* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */
printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
return 0;
}
long int initdram(int board_type)
{
return 64*1024*1024;
}
void
get_tod(void)
{
int year, month, day, hour, minute, second;
m48_tod_get(&year,
&month,
&day,
&hour,
&minute,
&second);
printf(" Current date/time: %d/%d/%d %d:%d:%d \n",
month, day, year, hour, minute, second);
}
/*
* EPIC, PCI, and I/O devices.
* Initialize Mousse Platform, probe for PCI devices,
* Query configuration parameters if not set.
*/
int misc_init_f (void)
{
#if 0
m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n",
TOD_NVRAM_SIZE);
get_tod();
#endif
sys_led_msg("BOOT");
return 0;
}
/*
* Initialize PCI Devices, report devices found.
*/
struct pci_controller hose;
void pci_init (void)
{
pci_mpc824x_init(&hose);
/* pci_dev_init(0); */
}
/*
* Write characters to LCD display.
* Note that the bytes for the first character is the last address.
*/
void
sys_led_msg(char* msg)
{
LED_REG(0) = msg[3];
LED_REG(1) = msg[2];
LED_REG(2) = msg[1];
LED_REG(3) = msg[0];
}
/*
* Map onboard TSOP-16MB DOC FLASH chip.
*/
void doc_init (void)
{
doc_probe(DOC_BASE_ADDR);
}
#define NV_ADDR ((volatile unsigned char *) CFG_ENV_ADDR)
/* Read from NVRAM */
void*
nvram_read(void *dest, const long src, size_t count)
{
int i;
volatile unsigned char* d = (unsigned char*)dest;
volatile unsigned char* s = (unsigned char*)src;
for( i = 0; i < count;i++)
d[i] = s[i];
return dest;
}
/* Write to NVRAM */
void
nvram_write(long dest, const void *src, size_t count)
{
int i;
volatile unsigned char* d = (unsigned char*)dest;
volatile unsigned char* s = (unsigned char*)src;
SYS_TOD_UNPROTECT();
for( i = 0; i < count;i++)
d[i] = s[i];
SYS_TOD_PROTECT();
}

83
board/bmw/serial.c Normal file
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/*
* (C) Copyright 2000
* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "ns16550.h"
#if CONFIG_CONS_INDEX == 1
static struct NS16550 *console =
(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
#elif CONFIG_CONS_INDEX == 2
static struct NS16550 *console =
(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
#else
#error no valid console defined
#endif
extern ulong get_bus_freq (ulong);
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
return (0);
}
void serial_putc (const char c)
{
if (c == '\n') {
serial_putc ('\r');
}
NS16550_putc (console, c);
}
void serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
}
int serial_getc (void)
{
return NS16550_getc (console);
}
int serial_tstc (void)
{
return NS16550_tstc (console);
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
NS16550_reinit (console, clock_divisor);
}

354
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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "cpu86.h"
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDIO */
/* PA24 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII MDC */
/* PA23 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDIO */
/* PA22 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII MDC */
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII TXSL1 */
/* PA12 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII TXSL0 */
/* PA11 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII TXSL1 */
/* PA10 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII TXSL0 */
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
/* PA6 */ { 1, 0, 0, 1, 0, 1 }, /* FCC2 MII PAUSE */
/* PA5 */ { 1, 0, 0, 1, 0, 1 }, /* FCC1 MII PAUSE */
/* PA4 */ { 1, 0, 0, 1, 0, 0 }, /* FCC2 MII PWRDN */
/* PA3 */ { 1, 0, 0, 1, 0, 0 }, /* FCC1 MII PWRDN */
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
/* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FCC2 MII MDINT */
/* PA0 */ { 1, 0, 0, 1, 0, 0 } /* FCC1 MII MDINT */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* PB3 */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* PB2 */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* PB1 */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* PB0 */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
/* PC29 */ { 1, 0, 0, 0, 0, 0 }, /* SCC1 CTS */
/* PC28 */ { 1, 0, 0, 0, 0, 0 }, /* SCC2 CTS */
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DACFD */
/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DNFD */
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FC9 */
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* FDC37C78 DRQFD */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
/* PD29 */ { 1, 0, 0, 1, 0, 0 }, /* SCC1 RTS */
/* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
/* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TXD */
/* PD26 */ { 1, 0, 0, 1, 0, 0 }, /* SCC2 RTS */
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
#if defined(CONFIG_SOFT_I2C)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
#if defined(CONFIG_HARD_I2C)
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#else /* normal I/O port pins */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#endif
#endif
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* PD3 */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* PD2 */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* PD1 */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* PD0 */
}
};
/* ------------------------------------------------------------------------- */
/* Check Board Identity:
*/
int checkboard (void)
{
printf ("Board: CPU86 (Rev %02x)\n", CPU86_REV);
return 0;
}
/* ------------------------------------------------------------------------- */
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
*
* This routine performs standard 8260 initialization sequence
* and calculates the available memory size. It may be called
* several times to try different SDRAM configurations on both
* 60x and local buses.
*/
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
* we are configuring CS1 if base != 0
*/
sdmr_ptr = &memctl->memc_psdmr;
orx_ptr = &memctl->memc_or2;
*orx_ptr = orx;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
}
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
ulong size8, size9;
#endif
long psize;
psize = 32 * 1024 * 1024;
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_psrt = CFG_PSRT;
#ifndef CFG_RAMBOOT
/* 60x SDRAM setup:
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL) ");
}
#endif /* CFG_RAMBOOT */
icache_enable ();
return (psize);
}
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);
}
#endif

485
board/nx823/nx823.c Normal file
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/*
* (C) Copyright 2001
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
*
* (C) Copyright 2001-2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <malloc.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
#if (MPC8XX_SPEED <= 50000000L)
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0F07EC04,
0x01BBD804,
0x1FF7F440,
0xFFFFFC07,
0xFFFFFFFF,
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FE7F434,
0xEFABE834,
0x1FA7D435,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x0F07EC04,
0x10EFDC04,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC00,
0xFFAFFC40,
0xFFAFFC07,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x0E07E804,
0x01BBD000,
0x1FF7F447,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x0E07E800,
0x10EFD400,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC47,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF7DC84,
0xFFFFFC04,
0xFFFFFC84,
0xFFFFFC07,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x7FFFFC07,
0xFFFFFFFF,
0xFFFFFFFF,
0xFFFFFFFF
#else
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFEC04,
0x11AFDC04,
0xEFBBF800,
0x1FF7F447,
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FF7F434,
0xEFEBE834,
0x1FB7D435,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFEC04,
0x10AFDC04,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC00,
0xEFBBF800,
0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFE800,
0x01BBD004,
0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F07FC04,
0xEEAFE800,
0x10AFD400,
0xF0AFFC00,
0xF0AFFC00,
0xE1BBF804,
0x1FF7F447,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF7DC84,
0xFFFFFC04,
0xFFFFFC04,
0xFFFFFC04,
0xFFFFFC84,
0xFFFFFC07,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
#endif
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
*/
int checkboard (void)
{
printf ("Board: Nexus NX823");
return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0, size_b1, size8, size9;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* Up to 2 Banks of 64Mbit x 2 devices
* Initial builds only have 1
*/
memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
memctl->memc_mar = 0x00000088;
/*
* Map controller SDRAM bank 0
*/
memctl->memc_or1 = CFG_OR1_PRELIM;
memctl->memc_br1 = CFG_BR1_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
/*
* Map controller SDRAM bank 1
*/
memctl->memc_or2 = CFG_OR2_PRELIM;
memctl->memc_br2 = CFG_BR2_PRELIM;
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
udelay(1);
memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
memctl->memc_mar = 0x00000088;
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay(500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
/*
* Check Bank 1 Memory Size
* use current column settings
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
size_b1 = dram_size (memctl->memc_mamr, (ulong *)SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
udelay (1000);
/*
* Adjust refresh rate depending on SDRAM type, both banks
* For types > 128 MBit leave it at the current (fast) rate
*/
if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay(1000);
}
/*
* Final mapping: map bigger bank first
*/
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b0 > 0) {
/*
* Position Bank 0 immediately above Bank 1
*/
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b1;
} else {
unsigned long reg;
/*
* No bank 0
*
* invalidate bank
*/
memctl->memc_br1 = 0;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
} else { /* SDRAM Bank 0 is bigger - map first */
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b0;
} else {
unsigned long reg;
/*
* No bank 1
*
* invalidate bank
*/
memctl->memc_br2 = 0;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
}
udelay(10000);
return (size_b0 + size_b1);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
/* NOTREACHED */
}
u_long *my_sernum;
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
char tmp[50];
u_char *e = gd->bd->bi_enetaddr;
/* save serial numbre from flash (uniquely programmed) */
my_sernum = malloc(8);
memcpy(my_sernum,gd->bd->bi_sernum,8);
/* save env variables according to sernum */
sprintf(tmp,"%08lx%08lx",my_sernum[0],my_sernum[1]);
setenv("serial#",tmp);
sprintf(tmp,"%02x:%02x:%02x:%02x:%02x:%02x"
,e[0],e[1],e[2],e[3],e[4],e[5]);
setenv("ethaddr",tmp);
return (0);
}
void load_sernum_ethaddr (void)
{
DECLARE_GLOBAL_DATA_PTR;
int i;
bd_t * bd = gd->bd;
for (i = 0; i < 8; i++) {
bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
}
bd->bi_enetaddr[0] = 0x10;
bd->bi_enetaddr[1] = 0x20;
bd->bi_enetaddr[2] = 0x30;
bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
bd->bi_enetaddr[4] = bd->bi_sernum[5];
bd->bi_enetaddr[5] = bd->bi_sernum[6];
}

132
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include "fpga_serial.h"
#include "hardware.h"
#include "pcippc2.h"
/* 8 data, 1 stop, no parity
*/
#define LCRVAL 0x03
/* RTS/DTR
*/
#define MCRVAL 0x03
/* Clear & enable FIFOs
*/
#define FCRVAL 0x07
static void fpga_serial_wait (void);
static void fpga_serial_print (char c);
void fpga_serial_init (int baudrate)
{
int clock_divisor = 115200 / baudrate;
out8 (FPGA (INT, SERIAL_CONFIG), 0x24);
iobarrier_rw ();
fpga_serial_wait ();
out8 (UART (IER), 0);
out8 (UART (LCR), LCRVAL | 0x80);
iobarrier_rw ();
out8 (UART (DLL), clock_divisor & 0xff);
out8 (UART (DLM), clock_divisor >> 8);
iobarrier_rw ();
out8 (UART (LCR), LCRVAL);
iobarrier_rw ();
out8 (UART (MCR), MCRVAL);
out8 (UART (FCR), FCRVAL);
iobarrier_rw ();
}
void fpga_serial_putc (char c)
{
if (c) {
fpga_serial_print (c);
}
}
void fpga_serial_puts (const char *s)
{
while (*s) {
fpga_serial_print (*s++);
}
}
int fpga_serial_getc (void)
{
while ((in8 (UART (LSR)) & 0x01) == 0);
return in8 (UART (RBR));
}
int fpga_serial_tstc (void)
{
return (in8 (UART (LSR)) & 0x01) != 0;
}
void fpga_serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
int clock_divisor = 115200 / gd->baudrate;
fpga_serial_wait ();
out8 (UART (LCR), LCRVAL | 0x80);
iobarrier_rw ();
out8 (UART (DLL), clock_divisor & 0xff);
out8 (UART (DLM), clock_divisor >> 8);
iobarrier_rw ();
out8 (UART (LCR), LCRVAL);
iobarrier_rw ();
}
static void fpga_serial_wait (void)
{
while ((in8 (UART (LSR)) & 0x40) == 0);
}
static void fpga_serial_print (char c)
{
if (c == '\n') {
while ((in8 (UART (LSR)) & 0x20) == 0);
out8 (UART (THR), '\r');
iobarrier_rw ();
}
while ((in8 (UART (LSR)) & 0x20) == 0);
out8 (UART (THR), c);
iobarrier_rw ();
if (c == '\n') {
fpga_serial_wait ();
}
}

34
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FPGA_SERIAL_H_
#define _FPGA_SERIAL_H_
extern void fpga_serial_init (int);
extern void fpga_serial_putc (char);
extern void fpga_serial_puts (const char *);
extern int fpga_serial_getc (void);
extern int fpga_serial_tstc (void);
extern void fpga_serial_setbrg (void);
#endif

141
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include "sconsole.h"
void (*sconsole_putc) (char) = 0;
void (*sconsole_puts) (const char *) = 0;
int (*sconsole_getc) (void) = 0;
int (*sconsole_tstc) (void) = 0;
void (*sconsole_setbrg) (void) = 0;
int serial_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
sb->pos = 0;
sb->size = 0;
sb->baud = gd->baudrate;
sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
return (0);
}
void serial_putc (char c)
{
if (sconsole_putc) {
(*sconsole_putc) (c);
} else {
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
if (c) {
sb->data[sb->pos++] = c;
if (sb->pos == sb->max_size) {
sb->pos = 0;
}
if (sb->size < sb->max_size) {
sb->size++;
}
}
}
}
void serial_puts (const char *s)
{
if (sconsole_puts) {
(*sconsole_puts) (s);
} else {
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
while (*s) {
sb->data[sb->pos++] = *s++;
if (sb->pos == sb->max_size) {
sb->pos = 0;
}
if (sb->size < sb->max_size) {
sb->size++;
}
}
}
}
int serial_getc (void)
{
if (sconsole_getc) {
return (*sconsole_getc) ();
} else {
return 0;
}
}
int serial_tstc (void)
{
if (sconsole_tstc) {
return (*sconsole_tstc) ();
} else {
return 0;
}
}
void serial_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
if (sconsole_setbrg) {
(*sconsole_setbrg) ();
} else {
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
sb->baud = gd->baudrate;
}
}
int sconsole_get_baudrate (void)
{
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
return sb->baud;
}
void sconsole_flush (void)
{
if (sconsole_putc) {
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
unsigned int end = sb->pos < sb->size
? sb->pos + sb->max_size - sb->size
: sb->pos - sb->size;
while (sb->size) {
(*sconsole_putc) (sb->data[end++]);
if (end == sb->max_size) {
end = 0;
}
sb->size--;
}
}
}

49
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/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _SCONSOLE_H_
#define _SCONSOLE_H_
#include <config.h>
typedef struct sconsole_buffer_s
{
unsigned long size;
unsigned long max_size;
unsigned long pos;
unsigned long baud;
char data [1];
} sconsole_buffer_t;
#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
extern void (* sconsole_putc) (char);
extern void (* sconsole_puts) (const char *);
extern int (* sconsole_getc) (void);
extern int (* sconsole_tstc) (void);
extern void (* sconsole_setbrg) (void);
extern void sconsole_flush (void);
extern int sconsole_get_baudrate (void);
#endif

344
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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 COL */
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 CRS */
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* PA25 */
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* PA24 */
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* PA23 */
/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* PA22 */
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1*/
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* PA13 */
/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* PA12 */
/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* PA11 */
/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* PA10 */
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* PA9 */
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* PA8 */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* PB31 */
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* PB30 */
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* PB29 */
/* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TXD */
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* PB27 */
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* PB26 */
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* PB25 */
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* PB24 */
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* PB23 */
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* PB22 */
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* PB21 */
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* PB20 */
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* PB19 */
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* PB18 */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RXD */
/* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RXD */
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
/* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TXD */
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 CTS */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 CTS */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* PC23 */
/* PC22 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 TXCK */
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXCK */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* PC20 */
/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* PC19 */
/* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* PC18 */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
/* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 DCD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* SCC2 DCD */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 CTS */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 DCD */
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 CTS */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* SCC4 DCD */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* PC2 */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* PC1 */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* PC0 */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RXD */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* PD30 */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* SCC3 RTS */
/* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4 RXD */
/* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4 TXD */
/* PD20 */ { 0, 0, 1, 1, 0, 0 }, /* SCC4 RTS */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* PD16 */
#if defined(CONFIG_SOFT_I2C)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
#if defined(CONFIG_HARD_I2C)
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#else /* normal I/O port pins */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
#endif
#endif
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* PD9 */
/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* PD8 */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 1, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* ------------------------------------------------------------------------- */
/* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: PM826\n");
return 0;
}
/* ------------------------------------------------------------------------- */
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
*
* This routine performs standard 8260 initialization sequence
* and calculates the available memory size. It may be called
* several times to try different SDRAM configurations on both
* 60x and local buses.
*/
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
volatile ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
sdmr_ptr = &memctl->memc_psdmr;
orx_ptr = &memctl->memc_or2;
*orx_ptr = orx;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
}
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
ulong size8, size9;
#endif
ulong psize = 32 * 1024 * 1024;
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
#ifndef CFG_RAMBOOT
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL) ");
} else {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL) ");
}
#endif
return (psize);
}
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
extern void doc_probe (ulong physadr);
void doc_init (void)
{
doc_probe (CFG_DOC_BASE);
}
#endif

318
board/siemens/IAD210/IAD210.c Normal file
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/*
* (C) Copyright 2001
* Paul Geerinckx
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
#include "atm.h"
#include <i2c.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
/* used PLD registers */
# define PLD_GCR1_REG (unsigned char *) (0x10000000 + 0)
# define PLD_EXT_RES (unsigned char *) (0x10000000 + 10)
# define PLD_EXT_FETH (unsigned char *) (0x10000000 + 11)
# define PLD_EXT_LED (unsigned char *) (0x10000000 + 12)
# define PLD_EXT_X21 (unsigned char *) (0x10000000 + 13)
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0xFE2DB004, 0xF0AA7004, 0xF0A5F400, 0xF3AFFC47, /* last */
_NOT_USED_,
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0xFFFAF834, 0xFFE5B435, /* last */
_NOT_USED_,
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0xFE2DB004, 0xF0AF7404, 0xF0AFFC00, 0xF0AFFC00,
0xF0AFFC00, 0xF0AAF800, 0xF1A5E447, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0xFE29B300, 0xF1A27304, 0xFFA5F747, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
0xF1AAF804, 0xFFA5F447, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0xFFAC3884, 0xFFAC3404, 0xFFAFFC04, 0xFFAFFC84,
0xFFAFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* MRS sequence (Offset 38 in UPMA RAM)
*/
0xFFAAB834, 0xFFA57434, 0xFFAFFC05, /* last */
_NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0xFFAFFC04, 0xFFAFFC05, /* last */
_NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile iop8xx_t *iop = &immap->im_ioport;
volatile fec_t *fecp = &immap->im_cpm.cp_fec;
long int size;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mar = 0x00000088;
/*
* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
memctl->memc_or2 = CFG_OR2_PRELIM;
memctl->memc_br2 = CFG_BR2_PRELIM;
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80004105; /* SDRAM precharge */
udelay(1);
memctl->memc_mcr = 0x80004030; /* SDRAM 16x autorefresh */
udelay(1);
memctl->memc_mcr = 0x80004138; /* SDRAM upload parameters */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/*
* Check Bank 0 Memory Size for re-configuration
*
*/
size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
memctl->memc_mamr = CFG_MAMR;
udelay (1000);
/*
* Final mapping
*/
memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
udelay(10000);
/* prepare pin multiplexing for fast ethernet */
atmLoad();
fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
return (size);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
return (0);
}
void board_serial_init(void)
{
;/* nothing to do here */
}
void board_ether_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile iop8xx_t *iop = &immap->im_ioport;
volatile fec_t *fecp = &immap->im_cpm.cp_fec;
atmLoad();
fecp->fec_ecntrl = 0x00000004; /* rev D3 pinmux SET */
iop->iop_pdpar |= 0x0080; /* set pin as MII_clock */
}
int board_pre_init (void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile iop8xx_t *iop = &immap->im_ioport;
/* configure the LED timing output pins - port A pin 4 */
iop->iop_papar = 0x0800;
iop->iop_padir = 0x0800;
/* start timer 2 for the 4hz LED blink rate */
timers->cpmt_tmr2 = 0xff2c; /* 4hz for 64mhz */
timers->cpmt_trr2 = 0x000003d0; /* clk/16 , prescale=256 */
timers->cpmt_tgcr = 0x00000810; /* run timer 2 */
/* chip select for PLD access */
memctl->memc_br6 = 0x10000401;
memctl->memc_or6 = 0xFC000908;
/* PLD initial values ( set LEDs, remove reset on LXT) */
*PLD_GCR1_REG = 0x06;
*PLD_EXT_RES = 0xC0;
*PLD_EXT_FETH = 0x40;
*PLD_EXT_LED = 0xFF;
*PLD_EXT_X21 = 0x04;
return 0;
}
void board_get_enetaddr (uchar *addr)
{
int i;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpm = &immap->im_cpm;
unsigned int rccrtmp;
char default_mac_addr[] = {0x00, 0x08, 0x01, 0x02, 0x03, 0x04};
for (i=0; i<6; i++)
addr[i] = default_mac_addr[i];
printf("There is an error in the i2c driver .. /n");
printf("You need to fix it first....../n");
rccrtmp = cpm->cp_rccr;
cpm->cp_rccr |= 0x0020;
i2c_reg_read(0xa0, 0);
printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
cpm->cp_rccr = rccrtmp;
}

573
board/siemens/SCM/scm.c Normal file
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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "scm.h"
static void config_scoh_cs(void);
extern int fpga_init(void);
#if 0
#define DEBUGF(fmt,args...) printf (fmt ,##args)
#else
#define DEBUGF(fmt,args...)
#endif
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
/* PA25 */ { 0, 0, 0, 1, 0, 0 },
/* PA24 */ { 0, 0, 0, 1, 0, 0 },
/* PA23 */ { 0, 0, 0, 1, 0, 0 },
/* PA22 */ { 0, 0, 0, 1, 0, 0 },
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1]*/
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
/* PA13 */ { 0, 0, 0, 1, 0, 0 },
/* PA12 */ { 0, 0, 0, 1, 0, 0 },
/* PA11 */ { 0, 0, 0, 1, 0, 0 },
/* PA10 */ { 0, 0, 0, 1, 0, 0 },
/* PA9 */ { 1, 1, 1, 1, 0, 0 }, /* TDM_A1 L1TXD0 */
/* PA8 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RXD0 */
/* PA7 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1TSYNC */
/* PA6 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A1 L1RSYNC */
/* PA5 */ { 1, 0, 0, 0, 0, 0 }, /* FIOX_FPGA_PR */
/* PA4 */ { 1, 0, 0, 0, 0, 0 }, /* DOHM_FPGA_PR */
/* PA3 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK4 */
/* PA2 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK4 */
/* PA1 */ { 0, 0, 0, 1, 0, 0 },
/* PA0 */ { 1, 0, 0, 0, 0, 0 } /* BUSY */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MIN */
/* PB30 */ { 1, 0, 0, 1, 0, 0 }, /* EQ_ALARM_MAJ */
/* PB29 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MIN */
/* PB28 */ { 1, 0, 0, 1, 0, 0 }, /* COM_ALARM_MAJ */
/* PB27 */ { 0, 1, 0, 0, 0, 0 },
/* PB26 */ { 0, 1, 0, 0, 0, 0 },
/* PB25 */ { 1, 0, 0, 1, 0, 0 }, /* LED_GREEN_L */
/* PB24 */ { 1, 0, 0, 1, 0, 0 }, /* LED_RED_L */
/* PB23 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TXD */
/* PB22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RXD */
/* PB21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1TSYNC */
/* PB20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_D2 L1RSYNC */
/* PB19 */ { 1, 0, 0, 0, 0, 0 }, /* UID */
/* PB18 */ { 0, 1, 0, 0, 0, 0 },
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
/* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C configuration */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK1 */
/* PC30 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK1 */
/* PC29 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK3 */
/* PC28 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK3 */
/* PC27 */ { 1, 1, 0, 0, 0, 0 }, /* TDM RXCLK2 */
/* PC26 */ { 1, 1, 0, 0, 0, 0 }, /* TDM TXCLK2 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 },
/* PC24 */ { 0, 0, 0, 1, 0, 0 },
/* PC23 */ { 0, 1, 0, 1, 0, 0 },
/* PC22 */ { 0, 1, 0, 0, 0, 0 },
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII TX_CLK */
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RX_CLK */
/* PC19 */ { 0, 1, 0, 0, 0, 0 },
/* PC18 */ { 0, 1, 0, 0, 0, 0 },
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_CLK */
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII TX_CLK */
/* PC15 */ { 0, 0, 0, 1, 0, 0 },
/* PC14 */ { 0, 1, 0, 0, 0, 0 },
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* RES_PHY_L */
/* PC12 */ { 0, 0, 0, 1, 0, 0 },
/* PC11 */ { 0, 0, 0, 1, 0, 0 },
/* PC10 */ { 0, 0, 0, 1, 0, 0 },
/* PC9 */ { 0, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TSYNC */
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* FEP_RDY */
/* PC7 */ { 0, 0, 0, 0, 0, 0 },
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* UC4_ALARM_L */
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* UC3_ALARM_L */
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* UC2_ALARM_L */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* RES_MISC_L */
/* PC2 */ { 0, 0, 0, 1, 0, 0 }, /* RES_OH_L */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* RES_DOHM_L */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* RES_FIOX_L */
},
/* Port D configuration */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_F */
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_F */
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* INIT_D */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* DONE_D */
/* PD25 */ { 0, 0, 0, 1, 0, 0 },
/* PD24 */ { 0, 0, 0, 1, 0, 0 },
/* PD23 */ { 0, 0, 0, 1, 0, 0 },
/* PD22 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1TXD */
/* PD21 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RXD */
/* PD20 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_A2 L1RSYNC */
/* PD19 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPISEL */
/* PD18 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPICLK */
/* PD17 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSI */
/* PD16 */ { 1, 1, 1, 0, 0, 0 }, /* SPI SPIMOSO */
#if defined(CONFIG_SOFT_I2C)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
#if defined(CONFIG_HARD_I2C)
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#else /* normal I/O port pins */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
#endif
#endif
/* PD13 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TXD */
/* PD12 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RXD */
/* PD11 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1TSYNC */
/* PD10 */ { 1, 1, 1, 0, 0, 0 }, /* TDM_B1 L1RSYNC */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 },
/* PD6 */ { 0, 0, 0, 1, 0, 1 },
/* PD5 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_F */
/* PD4 */ { 0, 0, 0, 1, 0, 0 }, /* PROG_D */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* ------------------------------------------------------------------------- */
/* Check Board Identity:
*/
int checkboard (void)
{
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
if (!i || strncmp (str, "TQM8260", 7)) {
puts ("### No HW ID - assuming TQM8260\n");
return (0);
}
puts (str);
putc ('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
*
* This routine performs standard 8260 initialization sequence
* and calculates the available memory size. It may be called
* several times to try different SDRAM configurations on both
* 60x and local buses.
*/
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
* we are configuring CS1 if base != 0
*/
sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
*orx_ptr = orx;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
}
/*
* Test Power-On-Reset.
*/
int power_on_reset (void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Test Reset Status Register */
return gd->reset_status & RSR_CSRS ? 0 : 1;
}
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
long size8, size9;
#endif
long psize, lsize;
psize = 16 * 1024 * 1024;
lsize = 0;
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
#if 0 /* Just for debugging */
#define prt_br_or(brX,orX) do { \
ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
printf ("\n" \
#brX " 0x%08x " #orX " 0x%08x " \
"==> 0x%08lx ... 0x%08lx = %ld MB\n", \
memctl->memc_ ## brX, memctl->memc_ ## orX, \
start, start+sizem, (sizem+1)>>20); \
} while (0)
prt_br_or (br0, or0);
prt_br_or (br1, or1);
prt_br_or (br2, or2);
prt_br_or (br3, or3);
#endif
#ifndef CFG_RAMBOOT
/* 60x SDRAM setup:
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL - %ld MB, ", psize >> 20);
} else {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL - %ld MB, ", psize >> 20);
}
/* Local SDRAM setup:
*/
#ifdef CFG_INIT_LOCAL_SDRAM
memctl->memc_lsrt = CFG_LSRT;
size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
(uchar *) SDRAM_BASE2_PRELIM);
size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
(uchar *) SDRAM_BASE2_PRELIM);
if (size8 < size9) {
lsize = size9;
printf ("Local:9COL - %ld MB) using ", lsize >> 20);
} else {
lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
(uchar *) SDRAM_BASE2_PRELIM);
printf ("Local:8COL - %ld MB) using ", lsize >> 20);
}
#if 0
/* Set up BR2 so that the local SDRAM goes
* right after the 60x SDRAM
*/
memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
(CFG_SDRAM_BASE + psize);
#endif
#endif /* CFG_INIT_LOCAL_SDRAM */
#endif /* CFG_RAMBOOT */
icache_enable ();
config_scoh_cs ();
return (psize);
}
/* ------------------------------------------------------------------------- */
static void config_scoh_cs (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immr->im_memctl;
volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;
volatile uint tmp, i;
/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
memctl->memc_or3 = CFG_CAN0_OR3;
memctl->memc_br3 = CFG_CAN0_BR3;
/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
memctl->memc_or4 = CFG_CAN1_OR4;
memctl->memc_br4 = CFG_CAN1_BR4;
/* Initialize MAMR to write in the array at address 0x0 */
memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
/* Initialize UPMA for CAN: single read */
memctl->memc_mdr = 0xcffeec00;
udelay (1); /* Necessary to have the data correct in the UPM array!!!! */
/* The read on the CAN controller write the data of mdr in UPMA array. */
/* The index to the array will be incremented automatically
through this read */
tmp = can->cpu_interface;
memctl->memc_mdr = 0x0ffcec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x0ffcec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x0ffcec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x0ffcec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x0ffcfc00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x0ffcfc00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0xfffdec07;
udelay (1);
tmp = can->cpu_interface;
/* Initialize MAMR to write in the array at address 0x18 */
memctl->memc_mamr = 0x18 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
/* Initialize UPMA for CAN: single write */
memctl->memc_mdr = 0xfcffec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x00ffec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x00ffec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x00ffec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x00ffec00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x00fffc00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x00fffc00;
udelay (1);
tmp = can->cpu_interface;
memctl->memc_mdr = 0x30ffec07;
udelay (1);
tmp = can->cpu_interface;
/* Initialize MAMR */
memctl->memc_mamr = MxMR_GPL_x4DIS; /* GPL_B4 ouput line Disable */
/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
memctl->memc_or5 = CFG_EXTPROM_OR5;
memctl->memc_br5 = CFG_EXTPROM_BR5;
/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
memctl->memc_or6 = CFG_EXTPROM_OR6;
memctl->memc_br6 = CFG_EXTPROM_BR6;
/* Initialize OR7 / BR7 for the Glue Logic */
memctl->memc_or7 = CFG_FIOX_OR7;
memctl->memc_br7 = CFG_FIOX_BR7;
/* Initialize OR8 / BR8 for the DOH Logic */
memctl->memc_or8 = CFG_FDOHM_OR8;
memctl->memc_br8 = CFG_FDOHM_BR8;
DEBUGF ("OR0 %08x BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
DEBUGF ("OR1 %08x BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
DEBUGF ("OR2 %08x BR2 %08x\n", memctl->memc_or2, memctl->memc_br2);
DEBUGF ("OR3 %08x BR3 %08x\n", memctl->memc_or3, memctl->memc_br3);
DEBUGF ("OR4 %08x BR4 %08x\n", memctl->memc_or4, memctl->memc_br4);
DEBUGF ("OR5 %08x BR5 %08x\n", memctl->memc_or5, memctl->memc_br5);
DEBUGF ("OR6 %08x BR6 %08x\n", memctl->memc_or6, memctl->memc_br6);
DEBUGF ("OR7 %08x BR7 %08x\n", memctl->memc_or7, memctl->memc_br7);
DEBUGF ("OR8 %08x BR8 %08x\n", memctl->memc_or8, memctl->memc_br8);
DEBUGF ("UPMA addr 0x0\n");
memctl->memc_mamr = 0x00 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
for (i = 0; i < 0x8; i++) {
tmp = can->cpu_interface;
udelay (1);
DEBUGF (" %08x ", memctl->memc_mdr);
}
DEBUGF ("\nUPMA addr 0x18\n");
memctl->memc_mamr = 0x18 | MxMR_OP_RARR | MxMR_GPL_x4DIS;
for (i = 0; i < 0x8; i++) {
tmp = can->cpu_interface;
udelay (1);
DEBUGF (" %08x ", memctl->memc_mdr);
}
DEBUGF ("\n");
memctl->memc_mamr = MxMR_GPL_x4DIS;
}
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
fpga_init ();
return (0);
}
/* ------------------------------------------------------------------------- */

589
board/siemens/pcu_e/pcu_e.c Normal file
View File

@ -0,0 +1,589 @@
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>
#include <cmd_bsp.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
static void puma_status (void);
static void puma_set_mode (int mode);
static int puma_init_done (void);
static void puma_load (ulong addr, ulong len);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
/*
* 50 MHz SDRAM access using UPM A
*/
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x11af7c04, 0xefbeec00,
0x1ffddc47, /* last */
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1ffddc35, 0xefceac34, 0x1f3d5c35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x1f0dfc04, 0xeeafbc04, 0x10af7c04, 0xf0affc00,
0xf0affc00, 0xf1affc00, 0xefbeec00, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
0x1f0dfc04, 0xeeafac00, 0x01be4c04, 0x1ffddc47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x1f0dfc04, 0xeeafac00, 0x10af5c00, 0xf0affc00,
0xf0affc00, 0xe1beec04, 0x1ffddc47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1ffd7c84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
0x7ffffc07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* PUMA access using UPM B
*/
const uint puma_table[] =
{
/*
* Single Read. (Offset 0 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_,
/*
* Precharge and MRS
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
0x0ffff804, 0x0ffff400, 0x3ffffc47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
0x7ffffc07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
*/
int checkboard (void)
{
puts ("Board: Siemens PCU E\n");
return (0);
}
/* ------------------------------------------------------------------------- */
long int
initdram (int board_type)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
long int size_b0, reg;
int i;
/*
* Configure UPMA for SDRAM
*/
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
memctl->memc_mptpr = CFG_MPTPR;
/* burst length=4, burst type=sequential, CAS latency=2 */
memctl->memc_mar = 0x00000088;
/*
* Map controller bank 2 to the SDRAM bank at preliminary address.
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or5 = CFG_OR5_PRELIM;
memctl->memc_br5 = CFG_BR5_PRELIM;
#else /* XXX */
memctl->memc_or2 = CFG_OR2_PRELIM;
memctl->memc_br2 = CFG_BR2_PRELIM;
#endif /* XXX */
/* initialize memory address register */
memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
/* mode initialization (offset 5) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(200); /* 0x8000A105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x05);
#else /* XXX */
udelay(200); /* 0x80004105 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x05);
#endif /* XXX */
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(1); /* 0x8000A830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(8) | MCR_MAD(0x30);
#else /* XXX */
udelay(1); /* 0x80004830 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(8) | MCR_MAD(0x30);
#endif /* XXX */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
udelay(1); /* 0x8000A106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS5 | MCR_MLCF(1) | MCR_MAD(0x06);
#else /* XXX */
udelay(1); /* 0x80004106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS2 | MCR_MLCF(1) | MCR_MAD(0x06);
#endif /* XXX */
reg = memctl->memc_mamr;
reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
reg |= MAMR_TLFB_4X; /* ... to 4x */
reg |= MAMR_PTBE; /* enable refresh */
memctl->memc_mamr = reg;
udelay(200);
/* Need at least 10 DRAM accesses to stabilize */
for (i=0; i<10; ++i) {
#if PCU_E_WITH_SWAPPED_CS /* XXX */
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
#else /* XXX */
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
#endif /* XXX */
unsigned long val;
val = *(addr + i);
*(addr + i) = val;
}
/*
* Check Bank 0 Memory Size for re-configuration
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
#else /* XXX */
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
/*
* Final mapping:
*/
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#else /* XXX */
memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
#endif /* XXX */
udelay(1000);
/*
* Configure UPMB for PUMA
*/
upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
return (size_b0);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
}
/* ------------------------------------------------------------------------- */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
#else /* XXX */
#define ETH_CFG_BITS (CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
CFG_PB_ETH_CFG2 | CFG_PB_ETH_CFG3 )
#endif /* XXX */
#define ETH_ALL_BITS (ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
void reset_phy(void)
{
immap_t *immr = (immap_t *)CFG_IMMR;
ulong value;
/* Configure all needed port pins for GPIO */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
# if CFG_ETH_MDDIS_VALUE
immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
# else
immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
# endif
immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS); /* GPIO */
immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS); /* active output */
immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS; /* output */
#endif /* XXX */
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
value = immr->im_cpm.cp_pbdat;
/* Assert Powerdown and Reset signals */
value |= CFG_PB_ETH_POWERDOWN;
value &= ~(CFG_PB_ETH_RESET);
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# if CFG_ETH_MDDIS_VALUE
value |= CFG_PB_ETH_MDDIS;
# else
value &= ~(CFG_PB_ETH_MDDIS);
# endif
#endif
#if CFG_ETH_CFG1_VALUE
value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
#if CFG_ETH_CFG2_VALUE
value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
#if CFG_ETH_CFG3_VALUE
value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
#endif
/* Drive output signals to initial state */
immr->im_cpm.cp_pbdat = value;
immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
udelay (10000);
/* De-assert Ethernet Powerdown */
immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
udelay (10000);
/* de-assert RESET signal of PHY */
immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
udelay (1000);
}
/*-----------------------------------------------------------------------
* Board Special Commands: access functions for "PUMA" FPGA
*/
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
#define PUMA_READ_MODE 0
#define PUMA_LOAD_MODE 1
int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr, len;
switch (argc) {
case 2: /* PUMA reset */
if (strncmp(argv[1], "stat", 4) == 0) { /* Reset */
puma_status ();
return 0;
}
break;
case 4: /* PUMA load addr len */
if (strcmp(argv[1],"load") != 0)
break;
addr = simple_strtoul(argv[2], NULL, 16);
len = simple_strtoul(argv[3], NULL, 16);
printf ("PUMA load: addr %08lX len %ld (0x%lX): ",
addr, len, len);
puma_load (addr, len);
return 0;
default:
break;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
#endif /* CFG_CMD_BSP */
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static void puma_set_mode (int mode)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
/* disable PUMA in memory controller */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_br3 = 0;
#else /* XXX */
memctl->memc_br4 = 0;
#endif /* XXX */
switch (mode) {
case PUMA_READ_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_READ;
memctl->memc_br3 = PUMA_CONF_BR_READ;
#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
break;
case PUMA_LOAD_MODE:
#if PCU_E_WITH_SWAPPED_CS /* XXX */
memctl->memc_or3 = PUMA_CONF_OR_LOAD;
memctl->memc_br3 = PUMA_CONF_BR_LOAD;
#else /* XXX */
memctl->memc_or4 = PUMA_CONF_OR_READ;
memctl->memc_br4 = PUMA_CONF_BR_READ;
#endif /* XXX */
break;
}
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
#define PUMA_INIT_TIMEOUT 1000 /* max. 1000 ms = 1 second */
static void puma_load (ulong addr, ulong len)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile uchar *fpga_addr = (volatile uchar *)PUMA_CONF_BASE; /* XXX ??? */
uchar *data = (uchar *)addr;
int i;
/* align length */
if (len & 1)
++len;
/* Reset FPGA */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT); /* make input */
immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_INIT);
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
#if PCU_E_WITH_SWAPPED_CS /* XXX */
immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG); /* GPIO */
immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG); /* active output */
immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG); /* Set low */
immr->im_cpm.cp_pbdir |= CFG_PB_PUMA_PROG; /* output */
#else
immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG); /* GPIO */
immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG); /* Set low */
immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG); /* active output */
immr->im_ioport.iop_padir |= CFG_PA_PUMA_PROG; /* output */
#endif /* XXX */
udelay (100);
#if PCU_E_WITH_SWAPPED_CS /* XXX */
immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG; /* release reset */
#else
immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG; /* release reset */
#endif /* XXX */
/* wait until INIT indicates completion of reset */
for (i=0; i<PUMA_INIT_TIMEOUT; ++i) {
udelay (1000);
if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
break;
}
if (i == PUMA_INIT_TIMEOUT) {
printf ("*** PUMA init timeout ***\n");
return;
}
puma_set_mode (PUMA_LOAD_MODE);
while (len--)
*fpga_addr = *data++;
puma_set_mode (PUMA_READ_MODE);
puma_status ();
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static void puma_status (void)
{
/* Check state */
printf ("PUMA initialization is %scomplete\n",
puma_init_done() ? "" : "NOT ");
}
/* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . */
static int puma_init_done (void)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
/* make sure pin is GPIO input */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
}
/* ------------------------------------------------------------------------- */
int misc_init_r (void)
{
ulong addr = 0;
ulong len = 0;
char *s;
printf ("PUMA: ");
if (puma_init_done()) {
printf ("initialized\n");
return 0;
}
if ((s = getenv("puma_addr")) != NULL)
addr = simple_strtoul(s, NULL, 16);
if ((s = getenv("puma_len")) != NULL)
len = simple_strtoul(s, NULL, 16);
if ((!addr) || (!len)) {
printf ("net list undefined\n");
return 0;
}
printf ("loading... ");
puma_load (addr, len);
return (0);
}
/* ------------------------------------------------------------------------- */

324
board/spd8xx/spd8xx.c Normal file
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@ -0,0 +1,324 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sharc_table[] =
{
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
0xFFFFEC05, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
/* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
0xFFFFEC05, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
/* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
/* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPM RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, /* last */
/*
* SDRAM Initialization (offset 5 in UPM RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPM RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPM RAM)
*/
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPM RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPM RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPM RAM)
*/
0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
*/
int checkboard (void)
{
puts ("Board: SPD823TS\n");
return (0);
}
/* ------------------------------------------------------------------------- */
long int
initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0;
#if 0
/*
* Map controller bank 2 to the SRAM bank at preliminary address.
*/
memctl->memc_or2 = CFG_OR2;
memctl->memc_br2 = CFG_BR2;
#endif
/*
* Map controller bank 4 to the PER8 bank.
*/
memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4;
#if 0
/* Configure SHARC at UMA */
upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
/* Map controller bank 5 to the SHARC */
memctl->memc_or5 = CFG_OR5;
memctl->memc_br5 = CFG_BR5;
#endif
memctl->memc_mamr = 0x00001000;
/* Configure SDRAM at UMB */
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
memctl->memc_mar = 0x00000088;
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
udelay(200);
memctl->memc_mcr = 0x80806105;
udelay(1);
memctl->memc_mcr = 0x80806130;
udelay(1);
memctl->memc_mcr = 0x80806130;
udelay(1);
memctl->memc_mcr = 0x80806106;
memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
return (size_b0);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mbmr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return (maxsize);
}
/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
immap_t *immr = (immap_t *)CFG_IMMR;
ushort sreg;
/* Configure extra port pins for NS DP83843 PHY */
immr->im_ioport.iop_papar &= ~(PA_ENET_MDC | PA_ENET_MDIO);
sreg = immr->im_ioport.iop_padir;
sreg |= PA_ENET_MDC; /* Mgmt. Data Clock is Output */
sreg &= ~(PA_ENET_MDIO); /* Mgmt. Data I/O is bidirect. => Input */
immr->im_ioport.iop_padir = sreg;
immr->im_ioport.iop_padat &= ~(PA_ENET_MDC); /* set MDC = 0 */
/*
* RESET in implemented by a positive pulse of at least 1 us
* at the reset pin.
*
* Configure RESET pins for NS DP83843 PHY, and RESET chip.
*
* Note: The RESET pin is high active, but there is an
* inverter on the SPD823TS board...
*/
immr->im_ioport.iop_pcpar &= ~(PC_ENET_RESET);
immr->im_ioport.iop_pcdir |= PC_ENET_RESET;
/* assert RESET signal of PHY */
immr->im_ioport.iop_pcdat &= ~(PC_ENET_RESET);
udelay (10);
/* de-assert RESET signal of PHY */
immr->im_ioport.iop_pcdat |= PC_ENET_RESET;
udelay (10);
}
/* ------------------------------------------------------------------------- */
void ide_set_reset(int on)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
/*
* Configure PC for IDE Reset Pin
*/
if (on) { /* assert RESET */
immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
} else { /* release RESET */
immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
}
/* program port pin as GPIO output */
immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
}
/* ------------------------------------------------------------------------- */

402
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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMTXEN */
/* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTCA */
/* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTSOC */
/* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 *ATMRXEN */
/* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRSOC */
/* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRCA */
/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TXD */
/* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RXD */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* PB17 */
/* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* PB16 */
/* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* PB15 */
/* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* PB14 */
/* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* PB13 */
/* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* PB12 */
/* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* PB11 */
/* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* PB10 */
/* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* PB9 */
/* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* PB8 */
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
/* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* PB6 */
/* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* PB5 */
/* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* PB4 */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 1, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII TX_CLK */
/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 1, 0, 0 }, /* PC16 */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
/* PC14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDC */
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* FCC2 MDIO */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
#if defined(CONFIG_SOFT_I2C)
/* PD15 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SDA */
/* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* I2C SCL */
#else
#if defined(CONFIG_HARD_I2C)
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
#else /* normal I/O port pins */
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
#endif
#endif
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* ------------------------------------------------------------------------- */
/* Check Board Identity:
*/
int checkboard (void)
{
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
if (!i || strncmp (str, "TQM8260", 7)) {
puts ("### No HW ID - assuming TQM8260\n");
return (1);
}
puts (str);
putc ('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
*
* This routine performs standard 8260 initialization sequence
* and calculates the available memory size. It may be called
* several times to try different SDRAM configurations on both
* 60x and local buses.
*/
static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
ulong orx, volatile uchar * base)
{
volatile uchar c = 0xff;
ulong cnt, val;
volatile ulong *addr;
volatile uint *sdmr_ptr;
volatile uint *orx_ptr;
int i;
ulong save[32]; /* to make test non-destructive */
ulong maxsize;
/* We must be able to test a location outsize the maximum legal size
* to find out THAT we are outside; but this address still has to be
* mapped by the controller. That means, that the initial mapping has
* to be (at least) twice as large as the maximum expected size.
*/
maxsize = (1 + (~orx | 0x7fff)) / 2;
/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
* we are configuring CS1 if base != 0
*/
sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
orx_ptr = base ? &memctl->memc_or2 : &memctl->memc_or1;
*orx_ptr = orx;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
*(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
i = 0;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
addr = (volatile ulong *) base;
save[i] = *addr;
*addr = 0;
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = (volatile ulong *) base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != ~cnt) {
/* Write the actual size to ORx
*/
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
return (cnt * sizeof (long));
}
}
return (maxsize);
}
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
#ifndef CFG_RAMBOOT
long size8, size9;
#endif
long psize, lsize;
psize = 16 * 1024 * 1024;
lsize = 0;
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
#if 0 /* Just for debugging */
#define prt_br_or(brX,orX) do { \
ulong start = memctl->memc_ ## brX & 0xFFFF8000; \
ulong sizem = ~memctl->memc_ ## orX | 0x00007FFF; \
printf ("\n" \
#brX " 0x%08x " #orX " 0x%08x " \
"==> 0x%08lx ... 0x%08lx = %ld MB\n", \
memctl->memc_ ## brX, memctl->memc_ ## orX, \
start, start+sizem, (sizem+1)>>20); \
} while (0)
prt_br_or (br0, or0);
prt_br_or (br1, or1);
prt_br_or (br2, or2);
prt_br_or (br3, or3);
#endif
#ifndef CFG_RAMBOOT
/* 60x SDRAM setup:
*/
size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
(uchar *) CFG_SDRAM_BASE);
size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
(uchar *) CFG_SDRAM_BASE);
if (size8 < size9) {
psize = size9;
printf ("(60x:9COL - %ld MB, ", psize >> 20);
} else {
psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
(uchar *) CFG_SDRAM_BASE);
printf ("(60x:8COL - %ld MB, ", psize >> 20);
}
/* Local SDRAM setup:
*/
#ifdef CFG_INIT_LOCAL_SDRAM
memctl->memc_lsrt = CFG_LSRT;
size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
(uchar *) SDRAM_BASE2_PRELIM);
size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
(uchar *) SDRAM_BASE2_PRELIM);
if (size8 < size9) {
lsize = size9;
printf ("Local:9COL - %ld MB) using ", lsize >> 20);
} else {
lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
(uchar *) SDRAM_BASE2_PRELIM);
printf ("Local:8COL - %ld MB) using ", lsize >> 20);
}
#if 0
/* Set up BR2 so that the local SDRAM goes
* right after the 60x SDRAM
*/
memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
(CFG_SDRAM_BASE + psize);
#endif
#endif /* CFG_INIT_LOCAL_SDRAM */
#endif /* CFG_RAMBOOT */
icache_enable ();
return (psize);
}
/* ------------------------------------------------------------------------- */

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/*
* (C) Copyright 2000, 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
0x1FF5FC47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x7FFFFC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* Test TQ ID string (TQM8xx...)
* If present, check for "L" type (no second DRAM bank),
* otherwise "L" type is assumed as default.
*
* Set board_type to 'L' for "L" type, 0 else.
*/
int checkboard (void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned char *s = getenv ("serial#");
puts ("Board: ");
if (!s || strncmp (s, "TQM8", 4)) {
puts ("### No HW ID - assuming TQM8xxL\n");
return (0);
}
if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
gd->board_type = 'L';
}
for (; *s; ++s) {
if (*s == ' ')
break;
putc (*s);
}
putc ('\n');
return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size8, size9;
long int size_b0 = 0;
long int size_b1 = 0;
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
/*
* The following value is used as an address (i.e. opcode) for
* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
* the port size is 32bit the SDRAM does NOT "see" the lower two
* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
* MICRON SDRAMs:
* -> 0 00 010 0 010
* | | | | +- Burst Length = 4
* | | | +----- Burst Type = Sequential
* | | +------- CAS Latency = 2
* | +----------- Operating Mode = Standard
* +-------------- Write Burst Mode = Programmed Burst Length
*/
memctl->memc_mar = 0x00000088;
/*
* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
memctl->memc_or2 = CFG_OR2_PRELIM;
memctl->memc_br2 = CFG_BR2_PRELIM;
#ifndef CONFIG_CAN_DRIVER
if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
memctl->memc_or3 = CFG_OR3_PRELIM;
memctl->memc_br3 = CFG_BR3_PRELIM;
}
#endif /* CONFIG_CAN_DRIVER */
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay (200);
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
udelay (1);
#ifndef CONFIG_CAN_DRIVER
if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
udelay (1);
}
#endif /* CONFIG_CAN_DRIVER */
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay (500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
#ifndef CONFIG_CAN_DRIVER
if (board_type != 'L') { /* "L" type boards have only one bank SDRAM */
/*
* Check Bank 1 Memory Size
* use current column settings
* [9 column SDRAM may also be used in 8 column mode,
* but then only half the real size will be used.]
*/
size_b1 =
dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
/* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
} else {
size_b1 = 0;
}
#endif /* CONFIG_CAN_DRIVER */
udelay (1000);
/*
* Adjust refresh rate depending on SDRAM type, both banks
* For types > 128 MBit leave it at the current (fast) rate
*/
if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay (1000);
}
/*
* Final mapping: map bigger bank first
*/
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br3 =
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b0 > 0) {
/*
* Position Bank 0 immediately above Bank 1
*/
memctl->memc_or2 =
((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 =
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b1;
} else {
unsigned long reg;
/*
* No bank 0
*
* invalidate bank
*/
memctl->memc_br2 = 0;
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
} else { /* SDRAM Bank 0 is bigger - map first */
memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br2 =
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
if (size_b1 > 0) {
/*
* Position Bank 1 immediately above Bank 0
*/
memctl->memc_or3 =
((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br3 =
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+ size_b0;
} else {
unsigned long reg;
#ifndef CONFIG_CAN_DRIVER
/*
* No bank 1
*
* invalidate bank
*/
memctl->memc_br3 = 0;
#endif /* CONFIG_CAN_DRIVER */
/* adjust refresh rate depending on SDRAM type, one bank */
reg = memctl->memc_mptpr;
reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
memctl->memc_mptpr = reg;
}
}
udelay (10000);
#ifdef CONFIG_CAN_DRIVER
/* Initialize OR3 / BR3 */
memctl->memc_or3 = CFG_OR3_CAN;
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;
memctl->memc_mcr = 0x0100 | UPMB;
memctl->memc_mdr = 0x0FFFD004;
memctl->memc_mcr = 0x0101 | UPMB;
memctl->memc_mdr = 0x0FFFC000;
memctl->memc_mcr = 0x0102 | UPMB;
memctl->memc_mdr = 0x3FFFC004;
memctl->memc_mcr = 0x0103 | UPMB;
memctl->memc_mdr = 0xFFFFDC05;
memctl->memc_mcr = 0x0104 | UPMB;
/* Initialize UPMB for CAN: single write */
memctl->memc_mdr = 0xFFFCC004;
memctl->memc_mcr = 0x0118 | UPMB;
memctl->memc_mdr = 0xCFFCD004;
memctl->memc_mcr = 0x0119 | UPMB;
memctl->memc_mdr = 0x0FFCC000;
memctl->memc_mcr = 0x011A | UPMB;
memctl->memc_mdr = 0x7FFCC004;
memctl->memc_mcr = 0x011B | UPMB;
memctl->memc_mdr = 0xFFFDCC05;
memctl->memc_mcr = 0x011C | UPMB;
#endif /* CONFIG_CAN_DRIVER */
return (size_b0 + size_b1);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
/* ------------------------------------------------------------------------- */

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/*
* (C) Copyright 2001
* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
#include "vpd.h"
#include "cmd_bsp.h"
/* ======================================================================
* Interpreter command to retrieve board specific Vital Product Data, "VPD"
* ======================================================================
*/
int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
VPD vpd; /* Board specific data struct */
uchar dev_addr = CFG_DEF_EEPROM_ADDR;
/* Validate usage */
if (argc > 2) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
/* Passed in EEPROM address */
if (argc == 2)
dev_addr = (uchar) simple_strtoul (argv[1], NULL, 16);
/* Read VPD and output it */
if (!vpd_get_data (dev_addr, &vpd)) {
vpd_print (&vpd);
return 0;
}
return 1;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_BSP) */

138
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/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
long int spd_sdram (void);
#include <common.h>
#include "walnut405.h"
#include <asm/processor.h>
int board_pre_init (void)
{
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the Walnut board.
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
| IRQ 16 405GP internally generated; active low; level sensitive
| IRQ 17-24 RESERVED
| IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
| IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
| IRQ 27 (EXT IRQ 2) Not Used
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
| Note for Walnut board:
| An interrupt taken for the FPGA (IRQ 25) indicates that either
| the Mouse, Keyboard, IRDA, or External Expansion caused the
| interrupt. The FPGA must be read to determine which device
| caused the interrupt. The default setting of the FPGA clears
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFFE0); /* set int polarities */
mtdcr (uictr, 0x10000000); /* set int trigger levels */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
/* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb1ap, 0x02815480);
mtebc (pb1cr, 0xF0018000);
/* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb2ap, 0x04815A80);
mtebc (pb2cr, 0xF0118000);
/* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb3ap, 0x01815280);
mtebc (pb3cr, 0xF0218000);
/* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb7ap, 0x01815280);
mtebc (pb7cr, 0xF0318000);
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004
*(volatile char *) (FPGA_BRDC) |= 0x1;
return 0;
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
unsigned char *s = getenv ("serial#");
unsigned char *e;
puts ("Board: ");
if (!s || strncmp (s, "WALNUT405", 9)) {
puts ("### No HW ID - assuming WALNUT405");
} else {
for (e = s; *e; ++e) {
if (*e == ' ')
break;
}
for (; s < e; ++s) {
putc (*s);
}
}
putc ('\n');
return (0);
}
/* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */
long int initdram (int board_type)
{
long int ret;
ret = spd_sdram ();
return ret;
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: xxx MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */

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/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <mpc8xx.h>
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint edo_60ns[] =
{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
0x8fffec24, 0x0ffbec04, 0x08f3ec04, 0x07f3ec08,
0x08f3ec04, 0x07f3ec48, 0x08f3ec04, 0x07f3ec48,
0x08f3ec04, 0x07f3ec48, 0x1ff7ec47, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
puts ("Board: AMX860\n");
return 0;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
#ifndef CONFIG_AMX_RAM_EXT
memctl->memc_mptpr = 0x0400; /* divide by 16 */
#else
memctl->memc_mptpr = 0x0200;
#endif
memctl->memc_mamr = 0x30a21114;
memctl->memc_or2 = 0xffc00800;
#ifndef CONFIG_AMX_RAM_EXT
memctl->memc_br2 = 0x81;
return (4 << 20);
#else
memctl->memc_or1 = 0xff000800;
memctl->memc_br1 = 0x00000081;
memctl->memc_br2 = 0x01000081;
return (20 << 20);
#endif
}