Coding style cleanup; update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk 2009-02-12 00:08:39 +01:00
parent 5fc56b907d
commit f15c6515fc
11 changed files with 2440 additions and 54 deletions

2392
CHANGELOG

File diff suppressed because it is too large Load Diff

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@ -124,4 +124,3 @@ void enable_vbus(void)
i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1); i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1);
} }
#endif #endif

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@ -45,4 +45,3 @@ distclean: clean
include $(SRCTREE)/rules.mk include $(SRCTREE)/rules.mk
sinclude $(obj).depend sinclude $(obj).depend

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@ -45,4 +45,3 @@ distclean: clean
include $(SRCTREE)/rules.mk include $(SRCTREE)/rules.mk
sinclude $(obj).depend sinclude $(obj).depend

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@ -238,4 +238,3 @@ static void cache_flush(void)
{ {
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
} }

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@ -51,7 +51,6 @@ leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
2008-02-22, Larry Johnson <lrj@acm.org> 2008-02-22, Larry Johnson <lrj@acm.org>
The CompactFlash(R) controller on the Korat board provides a hi-speed USB The CompactFlash(R) controller on the Korat board provides a hi-speed USB
interface. This may be connected to either a dedicated port on the on-board interface. This may be connected to either a dedicated port on the on-board
USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot

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@ -97,70 +97,70 @@ Implementing AMP(Asymmetric MultiProcessing)
------------- -------------
1. Build kernel image for core0: 1. Build kernel image for core0:
a. $ make 85xx/mpc8572_ds_defconfig a. $ make 85xx/mpc8572_ds_defconfig
b. $ make menuconfig b. $ make menuconfig
- un-select "Processor support"->"Symetric multi-processing support" - un-select "Processor support"->"Symetric multi-processing support"
c. $ make uImage c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core0
2. Build kernel image for core1: 2. Build kernel image for core1:
a. $ make 85xx/mpc8572_ds_defconfig a. $ make 85xx/mpc8572_ds_defconfig
b. $ make menuconfig b. $ make menuconfig
- Un-select "Processor support"->"Symetric multi-processing support" - Un-select "Processor support"->"Symetric multi-processing support"
- Select "Advanced setup" -> " Prompt for advanced kernel - Select "Advanced setup" -> " Prompt for advanced kernel
configuration options" configuration options"
- Select "Set physical address where the kernel is loaded" and - Select "Set physical address where the kernel is loaded" and
set it to 0x20000000, asssuming core1 will start from 512MB. set it to 0x20000000, asssuming core1 will start from 512MB.
- Select "Set custom page offset address" - Select "Set custom page offset address"
- Select "Set custom kernel base address" - Select "Set custom kernel base address"
- Select "Set maximum low memory" - Select "Set maximum low memory"
- "Exit" and save the selection. - "Exit" and save the selection.
c. $ make uImage c. $ make uImage
d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1 d. $ cp arch/powerpc/boot/uImage /tftpboot/uImage.core1
3. Create dtb for core0: 3. Create dtb for core0:
$ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb $ dtc -I dts -O dtb -f -b 0 arch/powerpc/boot/dts/mpc8572ds_core0.dts > /tftpboot/mpc8572ds_core0.dtb
4. Create dtb for core1: 4. Create dtb for core1:
$ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb $ dtc -I dts -O dtb -f -b 1 arch/powerpc/boot/dts/mpc8572ds_core1.dts > /tftpboot/mpc8572ds_core1.dtb
5. Bring up two cores separately: 5. Bring up two cores separately:
a. Power on the board, under u-boot prompt: a. Power on the board, under u-boot prompt:
=> setenv <serverip> => setenv <serverip>
=> setenv <ipaddr> => setenv <ipaddr>
=> setenv bootargs root=/dev/ram rw console=ttyS0,115200 => setenv bootargs root=/dev/ram rw console=ttyS0,115200
b. Bring up core1's kernel first: b. Bring up core1's kernel first:
=> setenv bootm_low 0x20000000 => setenv bootm_low 0x20000000
=> setenv bootm_size 0x10000000 => setenv bootm_size 0x10000000
=> tftp 21000000 8572/uImage.core1 => tftp 21000000 8572/uImage.core1
=> tftp 22000000 8572/ramdiskfile => tftp 22000000 8572/ramdiskfile
=> tftp 20c00000 8572/mpc8572ds_core1.dtb => tftp 20c00000 8572/mpc8572ds_core1.dtb
=> interrupts off => interrupts off
=> bootm start 21000000 22000000 20c00000 => bootm start 21000000 22000000 20c00000
=> bootm loados => bootm loados
=> bootm ramdisk => bootm ramdisk
=> bootm fdt => bootm fdt
=> fdt boardsetup => fdt boardsetup
=> fdt chosen $initrd_start $initrd_end => fdt chosen $initrd_start $initrd_end
=> bootm prep => bootm prep
=> cpu 1 release $bootm_low - $fdtaddr - => cpu 1 release $bootm_low - $fdtaddr -
c. Bring up core0's kernel(on the same u-boot console): c. Bring up core0's kernel(on the same u-boot console):
=> setenv bootm_low 0 => setenv bootm_low 0
=> setenv bootm_size 0x20000000 => setenv bootm_size 0x20000000
=> tftp 1000000 8572/uImage.core0 => tftp 1000000 8572/uImage.core0
=> tftp 2000000 8572/ramdiskfile => tftp 2000000 8572/ramdiskfile
=> tftp c00000 8572/mpc8572ds_core0.dtb => tftp c00000 8572/mpc8572ds_core0.dtb
=> bootm 1000000 2000000 c00000 => bootm 1000000 2000000 c00000
Please note only core0 will run u-boot, core1 starts kernel directly after Please note only core0 will run u-boot, core1 starts kernel directly after
"cpu release" command is issued. "cpu release" command is issued.

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@ -84,4 +84,3 @@ extern int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len);
extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len); extern int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len);
extern void enable_vbus(void); extern void enable_vbus(void);
#endif /* __DAVINCI_USB_H__ */ #endif /* __DAVINCI_USB_H__ */

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@ -314,4 +314,3 @@ extern inline u16 musb_readw(u32 offset);
extern inline u8 musb_readb(u32 offset); extern inline u8 musb_readb(u32 offset);
#endif /* __MUSB_HDRC_DEFS_H__ */ #endif /* __MUSB_HDRC_DEFS_H__ */

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@ -818,8 +818,10 @@ int usb_lowlevel_init(void)
/* Start the host controller. */ /* Start the host controller. */
cmd = ehci_readl(&hcor->or_usbcmd); cmd = ehci_readl(&hcor->or_usbcmd);
/* Philips, Intel, and maybe others need CMD_RUN before the /*
* root hub will detect new devices (why?); NEC doesn't */ * Philips, Intel, and maybe others need CMD_RUN before the
* root hub will detect new devices (why?); NEC doesn't
*/
cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
cmd |= CMD_RUN; cmd |= CMD_RUN;
ehci_writel(&hcor->or_usbcmd, cmd); ehci_writel(&hcor->or_usbcmd, cmd);

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@ -81,4 +81,3 @@
#endif #endif
#endif /* __ASM_ARCH_OMAP_GPMC_H */ #endif /* __ASM_ARCH_OMAP_GPMC_H */