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u-boot
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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

This commit is contained in:
Tom Rini 2014-11-24 12:02:12 -05:00
parent 1739564e75 e7eb277dce
commit dee332ffb7
76 changed files with 1242 additions and 451 deletions
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4
arch/arm/cpu/arm926ejs/mx27/Makefile
View File

@ -5,3 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y = generic.o reset.o timer.o
ifndef CONFIG_SPL_BUILD
obj-y += relocate.o
endif

51
arch/arm/cpu/arm926ejs/mx27/relocate.S Normal file
View File

@ -0,0 +1,51 @@
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)

1
arch/arm/cpu/arm926ejs/mxs/mxsimage-signed.cfg
View File

@ -1,3 +1,4 @@
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin

1
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
View File

@ -1,3 +1,4 @@
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin

1
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg
View File

@ -1,3 +1,4 @@
DISPLAYPROGRESS
SECTION 0x0 BOOTABLE
TAG LAST
LOAD 0x1000 spl/u-boot-spl.bin

31
arch/arm/cpu/armv7/mx5/soc.c
View File

@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
reg = readl(&iomuxc_regs->gpr1);
switch (cs_size) {
case CS0_128:
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
reg |= 0x5;
break;
case CS0_64M_CS1_64M:
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
reg |= 0x1B;
break;
case CS0_64M_CS1_32M_CS2_32M:
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
reg |= 0x4B;
break;
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
reg |= 0x249;
break;
default:
printf("Unknown chip select size: %d\n", cs_size);
break;
}
writel(reg, &iomuxc_regs->gpr1);
}
#ifdef CONFIG_MX53
void boot_mode_apply(unsigned cfg_val)
{

38
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -596,6 +596,14 @@ int enable_sata_clock(void)
ungate_sata_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
}
void disable_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
(struct mxc_ccm_reg *)CCM_BASE_ADDR;
clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
#endif
int enable_pcie_clock(void)
@ -673,6 +681,36 @@ void hab_caam_clock_enable(unsigned char enable)
}
#endif
static void enable_pll3(void)
{
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
/* make sure pll3 is enabled */
if ((readl(&anatop->usb1_pll_480_ctrl) &
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
/* enable pll's power */
writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
&anatop->usb1_pll_480_ctrl_set);
writel(0x80, &anatop->ana_misc2_clr);
/* wait for pll lock */
while ((readl(&anatop->usb1_pll_480_ctrl) &
BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
;
/* disable bypass */
writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
&anatop->usb1_pll_480_ctrl_clr);
/* enable pll output */
writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
&anatop->usb1_pll_480_ctrl_set);
}
}
void enable_thermal_clk(void)
{
enable_pll3();
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {

15
arch/arm/cpu/armv7/mx6/soc.c
View File

@ -22,6 +22,8 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/bootm.h>
#include <dm.h>
#include <imx_thermal.h>
enum ldo_reg {
LDO_ARM,
@ -37,6 +39,19 @@ struct scu_regs {
u32 fpga_rev;
};
#if defined(CONFIG_IMX6_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 1,
.fuse_word = 6,
};
U_BOOT_DEVICE(imx6_thermal) = {
.name = "imx_thermal",
.platdata = &imx6_thermal_plat,
};
#endif
u32 get_nr_cpus(void)
{
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;

5
arch/arm/cpu/armv7/omap-common/sata.c
View File

@ -74,6 +74,11 @@ int init_sata(int dev)
return ret;
}
int reset_sata(int dev)
{
return 0;
}
/* On OMAP platforms SATA provides the SCSI subsystem */
void scsi_init(void)
{

60
arch/arm/imx-common/cpu.c
View File

@ -17,6 +17,8 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
@ -134,6 +136,11 @@ int print_cpuinfo(void)
{
u32 cpurev;
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, ret;
#endif
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
@ -141,6 +148,21 @@ int print_cpuinfo(void)
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (!ret)
printf("CPU: Temperature %d C\n", cpu_tmp);
else
printf("CPU: Temperature: invalid sensor data\n");
} else {
printf("CPU: Temperature: Can't find sensor device\n");
}
#endif
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
@ -180,10 +202,44 @@ u32 get_ahb_clk(void)
return get_periph_clk() / (ahb_podf + 1);
}
#if defined(CONFIG_VIDEO_IPUV3)
void arch_preboot_os(void)
{
#if defined(CONFIG_CMD_SATA)
sata_stop();
#endif
#if defined(CONFIG_VIDEO_IPUV3)
/* disable video before launching O/S */
ipuv3_fb_shutdown();
}
#endif
}
void set_chipselect_size(int const cs_size)
{
unsigned int reg;
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
reg = readl(&iomuxc_regs->gpr[1]);
switch (cs_size) {
case CS0_128:
reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
reg |= 0x5;
break;
case CS0_64M_CS1_64M:
reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
reg |= 0x1B;
break;
case CS0_64M_CS1_32M_CS2_32M:
reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
reg |= 0x4B;
break;
case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
reg |= 0x249;
break;
default:
printf("Unknown chip select size: %d\n", cs_size);
break;
}
writel(reg, &iomuxc_regs->gpr[1]);
}

2
board/compulab/cm_fx6/imximage.cfg → arch/arm/imx-common/spl_sd.cfg
View File

@ -4,5 +4,5 @@
* SPDX-License-Identifier: GPL-2.0+
*/
IMAGE_VERSION 2
IMAGE_VERSION 2
BOOT_FROM sd

5
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -12,3 +12,8 @@
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6D 0x64
#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3

12
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -202,11 +202,6 @@
*/
#define WBED 1
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
/*
* CSPI register definitions
*/
@ -414,8 +409,7 @@ struct weim {
#if defined(CONFIG_MX51)
struct iomuxc {
u32 gpr0;
u32 gpr1;
u32 gpr[2];
u32 omux0;
u32 omux1;
u32 omux2;
@ -424,9 +418,7 @@ struct iomuxc {
};
#elif defined(CONFIG_MX53)
struct iomuxc {
u32 gpr0;
u32 gpr1;
u32 gpr2;
u32 gpr[3];
u32 omux0;
u32 omux1;
u32 omux2;

2
arch/arm/include/asm/arch-mx6/clock.h
View File

@ -60,10 +60,12 @@ void enable_uart_clk(unsigned char enable);
int enable_cspi_clock(unsigned char enable, unsigned spi_num);
int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
int enable_sata_clock(void);
void disable_sata_clock(void);
int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq);
void enable_enet_clk(unsigned char enable);
void enable_thermal_clk(void);
#endif /* __ASM_ARCH_CLOCK_H */

37
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -332,6 +332,43 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
/* WEIM registers */
struct weim {
u32 cs0gcr1;
u32 cs0gcr2;
u32 cs0rcr1;
u32 cs0rcr2;
u32 cs0wcr1;
u32 cs0wcr2;
u32 cs1gcr1;
u32 cs1gcr2;
u32 cs1rcr1;
u32 cs1rcr2;
u32 cs1wcr1;
u32 cs1wcr2;
u32 cs2gcr1;
u32 cs2gcr2;
u32 cs2rcr1;
u32 cs2rcr2;
u32 cs2wcr1;
u32 cs2wcr2;
u32 cs3gcr1;
u32 cs3gcr2;
u32 cs3rcr1;
u32 cs3rcr2;
u32 cs3wcr1;
u32 cs3wcr2;
u32 unused[12];
u32 wcr;
u32 wiar;
u32 ear;
};
/* System Reset Controller (SRC) */
struct src {
u32 scr;

1
arch/arm/include/asm/arch-mx6/sys_proto.h
View File

@ -26,6 +26,7 @@ u32 get_cpu_rev(void);
const char *get_imx_type(u32 imxtype);
unsigned imx_ddr_size(void);
void set_chipselect_size(int const);
/*
* Initializes on-chip ethernet controllers.

5
arch/arm/lib/crt0.S
View File

@ -104,6 +104,11 @@ clr_gd:
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
b relocate_code
here:
/*
* now relocate vectors
*/
bl relocate_vectors
/* Set up final (full) environment */

73
arch/arm/lib/relocate.S
View File

@ -10,6 +10,47 @@
#include <config.h>
#include <linux/linkage.h>
/*
* Default/weak exception vectors relocation routine
*
* This routine covers the standard ARM cases: normal (0x00000000),
* high (0xffff0000) and VBAR. SoCs which do not comply with any of
* the standard cases must provide their own, strong, version.
*/
.section .text.relocate_vectors,"ax",%progbits
.weak relocate_vectors
ENTRY(relocate_vectors)
#ifdef CONFIG_HAS_VBAR
/*
* If the ARM processor has the security extensions,
* use VBAR to relocate the exception vectors.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
#else
/*
* Copy the relocated exception vectors to the
* correct address
* CP15 c1 V bit gives us the location of the vectors:
* 0x00000000 or 0xFFFF0000.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
ands r2, r2, #(1 << 13)
ldreq r1, =0x00000000 /* If V=0 */
ldrne r1, =0xFFFF0000 /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
#endif
bx lr
ENDPROC(relocate_vectors)
/*
* void relocate_code(addr_moni)
*
@ -54,34 +95,6 @@ fixnext:
cmp r2, r3
blo fixloop
/*
* Relocate the exception vectors
*/
#ifdef CONFIG_HAS_VBAR
/*
* If the ARM processor has the security extensions,
* use VBAR to relocate the exception vectors.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
#else
/*
* Copy the relocated exception vectors to the
* correct address
* CP15 c1 V bit gives us the location of the vectors:
* 0x00000000 or 0xFFFF0000.
*/
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
ands r2, r2, #(1 << 13)
ldreq r1, =0x00000000 /* If V=0 */
ldrne r1, =0xFFFF0000 /* If V=1 */
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
ldmia r0!, {r2-r8,r10}
stmia r1!, {r2-r8,r10}
#endif
relocate_done:
#ifdef __XSCALE__
@ -96,9 +109,9 @@ relocate_done:
/* ARMv4- don't know bx lr but the assembler fails to see that */
#ifdef __ARM_ARCH_4__
mov pc, lr
mov pc, lr
#else
bx lr
bx lr
#endif
ENDPROC(relocate_code)

10
board/bachmann/ot1200/ot1200.c
View File

@ -173,7 +173,7 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = {
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@ -196,13 +196,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

10
board/boundary/nitrogen6x/nitrogen6x.c
View File

@ -302,7 +302,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@ -325,13 +325,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

12
board/compulab/cm_fx6/cm_fx6.c
View File

@ -98,9 +98,6 @@ int sata_initialize(void)
/* Make sure this gpio has logical 0 value */
gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
udelay(100);
cm_fx6_sata_power(0);
mdelay(250);
cm_fx6_sata_power(1);
for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
@ -125,6 +122,15 @@ int sata_initialize(void)
return err;
}
int sata_stop(void)
{
__sata_stop();
cm_fx6_sata_power(0);
mdelay(250);
return 0;
}
#else
static int cm_fx6_setup_issd(void) { return 0; }
#endif

10
board/embest/mx6boards/mx6boards.c
View File

@ -216,7 +216,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
int i;
/*
@ -268,13 +268,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

1
board/freescale/common/Makefile
View File

@ -53,6 +53,7 @@ obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
obj-$(CONFIG_ZM7300) += zm7300.o
obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/

54
board/freescale/common/pfuze.c Normal file
View File

@ -0,0 +1,54 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
struct pmic *pfuze_common_init(unsigned char i2cbus)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(i2cbus);
if (ret)
return NULL;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return NULL;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
reg &= ~SW1x_STBY_MASK;
reg |= SW1x_0_975V;
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
return p;
}

12
board/freescale/common/pfuze.h Normal file
View File

@ -0,0 +1,12 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PFUZE_BOARD_HELPER__
#define __PFUZE_BOARD_HELPER__
struct pmic *pfuze_common_init(unsigned char i2cbus);
#endif

10
board/freescale/mx51evk/mx51evk.c
View File

@ -320,7 +320,7 @@ int board_mmc_init(bd_t *bis)
};
u32 index;
s32 status = 0;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
@ -340,11 +340,13 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

10
board/freescale/mx53ard/mx53ard.c
View File

@ -166,7 +166,7 @@ int board_mmc_init(bd_t *bis)
};
u32 index;
s32 status = 0;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
@ -185,12 +185,14 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

10
board/freescale/mx53evk/mx53evk.c
View File

@ -195,7 +195,7 @@ int board_mmc_init(bd_t *bis)
};
u32 index;
s32 status = 0;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@ -214,12 +214,14 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

10
board/freescale/mx53loco/mx53loco.c
View File

@ -186,7 +186,7 @@ int board_mmc_init(bd_t *bis)
};
u32 index;
s32 status = 0;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@ -205,12 +205,14 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(2)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

10
board/freescale/mx53smd/mx53smd.c
View File

@ -106,7 +106,7 @@ int board_mmc_init(bd_t *bis)
};
u32 index;
s32 status = 0;
int ret;
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
@ -121,12 +121,14 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(1)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

10
board/freescale/mx6qarm2/mx6qarm2.c
View File

@ -125,7 +125,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
u32 index = 0;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
@ -145,13 +145,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif

95
board/freescale/mx6qsabreauto/mx6qsabreauto.c
View File

@ -28,6 +28,8 @@
#include <asm/imx-common/video.h>
#include <asm/arch/crm_regs.h>
#include <pca953x.h>
#include <power/pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
@ -53,6 +55,12 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define I2C_PMIC 1
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@ -97,6 +105,7 @@ static struct i2c_pads_info i2c_pad_info1 = {
}
};
#ifndef CONFIG_SYS_FLASH_CFI
/*
* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
* Compass Sensor, Accelerometer, Res Touch
@ -113,6 +122,7 @@ static struct i2c_pads_info i2c_pad_info2 = {
.gp = IMX_GPIO_NR(3, 18)
}
};
#endif
static iomux_v3_cfg_t const i2c3_pads[] = {
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
@ -160,6 +170,75 @@ static int port_exp_direction_output(unsigned gpio, int value)
return 0;
}
static iomux_v3_cfg_t const eimnor_pads[] = {
MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void eimnor_cs_setup(void)
{
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
writel(0x00020181, &weim_regs->cs0gcr1);
writel(0x00000001, &weim_regs->cs0gcr2);
writel(0x0a020000, &weim_regs->cs0rcr1);
writel(0x0000c000, &weim_regs->cs0rcr2);
writel(0x0804a240, &weim_regs->cs0wcr1);
writel(0x00000120, &weim_regs->wcr);
set_chipselect_size(CS0_128);
}
static void setup_iomux_eimnor(void)
{
imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
eimnor_cs_setup();
}
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
@ -402,6 +481,7 @@ int board_early_init_f(void)
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
return 0;
}
@ -415,11 +495,13 @@ int board_init(void)
/* I2C 3 Steer */
gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
#ifndef CONFIG_SYS_FLASH_CFI
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
#endif
gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
setup_iomux_eimnor();
return 0;
}
@ -430,6 +512,17 @@ int board_spi_cs_gpio(unsigned bus, unsigned cs)
}
#endif
int power_init_board(void)
{
struct pmic *p;
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
return 0;
}
#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */

1
board/freescale/mx6sabresd/MAINTAINERS
View File

@ -5,3 +5,4 @@ F: board/freescale/mx6sabresd/
F: include/configs/mx6sabresd.h
F: configs/mx6dlsabresd_defconfig
F: configs/mx6qsabresd_defconfig
F: configs/mx6sabresd_spl_defconfig

90
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -27,12 +27,11 @@
#include <i2c.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
#include <asm/arch/mx6-ddr.h>
DECLARE_GLOBAL_DATA_PTR;
#define BOOT_CFG 0x020D8004
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@ -300,7 +299,8 @@ int board_mmc_init(bd_t *bis)
return 0;
#else
unsigned reg = readl(BOOT_CFG) >> 11;
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
@ -560,60 +560,27 @@ int board_init(void)
return 0;
}
static int pfuze_init(void)
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
/* Increase VGEN3 from 2.5 to 2.8V */
pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
reg &= ~0xf;
reg |= 0xa;
reg &= ~LDO_VOL_MASK;
reg |= LDOB_2_80V;
pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
/* Increase VGEN5 from 2.8 to 3V */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg &= ~0xf;
reg |= 0xc;
reg &= ~LDO_VOL_MASK;
reg |= LDOB_3_00V;
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
/* Set SW1AB stanby volage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
return 0;
}
@ -640,8 +607,6 @@ int board_late_init(void)
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
pfuze_init();
return 0;
}
@ -729,11 +694,33 @@ static struct mx6_ddr3_cfg mem_ddr = {
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* This section require the differentiation
* between iMX6 Sabre Families.
* But for now, it will configure only for
* SabreSD.
* This section requires the differentiation between iMX6 Sabre boards, but
* for now, it will configure only for the mx6q variant.
*/
static void spl_dram_init(void)
{
@ -768,6 +755,9 @@ void board_init_f(ulong dummy)
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();

58
board/freescale/mx6sabresd/mx6sabresd_spl.cfg
View File

@ -1,58 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
DATA 4 0x020c4074 0x3FF00000
DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4 0x020c4060 0x000000fb

7
board/freescale/mx6slevk/mx6slevk.c
View File

@ -230,16 +230,11 @@ int board_eth_init(bd_t *bis)
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/* clear gpr1[14], gpr1[18:17] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
ret = enable_fec_anatop_clock(ENET_50MHz);
if (ret)
return ret;
return 0;
return enable_fec_anatop_clock(ENET_50MHz);
}
#endif

159
board/freescale/mx6sxsabresd/mx6sxsabresd.c
View File

@ -25,6 +25,7 @@
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
DECLARE_GLOBAL_DATA_PTR;
@ -68,6 +69,34 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD pin */
MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* RST_B, used for power reset cycle */
MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@ -119,7 +148,6 @@ static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int ret;
int reg;
/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
@ -140,11 +168,7 @@ static int setup_fec(void)
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
ret = enable_fec_anatop_clock(ENET_125MHz);
if (ret)
return ret;
return 0;
return enable_fec_anatop_clock(ENET_125MHz);
}
int board_eth_init(bd_t *bis)
@ -170,52 +194,19 @@ static struct i2c_pads_info i2c_pad_info1 = {
},
};
static int pfuze_init(void)
int power_init_board(void)
{
struct pmic *p;
int ret;
unsigned int reg;
ret = power_pfuze100_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("PFUZE100");
ret = pmic_probe(p);
if (ret)
return ret;
pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
/* Set SW1AB standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PUZE_100_SW1ABCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
reg &= ~0x3f;
reg |= 0x1b;
pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
reg &= ~0xc0;
reg |= 0x40;
pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
p = pfuze_common_init(I2C_PMIC);
if (!p)
return -ENODEV;
/* Enable power of VGEN5 3V3, needed for SD3 */
pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
reg &= ~0x1F;
reg |= 0x1F;
reg &= ~LDO_VOL_MASK;
reg |= (LDOB_3_30V | (1 << LDO_EN));
pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
return 0;
@ -243,7 +234,6 @@ int board_phy_config(struct phy_device *phydev)
int board_early_init_f(void)
{
setup_iomux_uart();
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
@ -255,35 +245,98 @@ int board_early_init_f(void)
return 0;
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
int board_mmc_getcd(struct mmc *mmc)
{
return 1; /* Assume boot SD always present */
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = 1; /* Assume uSDHC2 is always present */
break;
case USDHC3_BASE_ADDR:
ret = !gpio_get_value(USDHC3_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = !gpio_get_value(USDHC4_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
int i, ret;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC2
* mmc1 USDHC3
* mmc2 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
gpio_direction_input(USDHC3_CD_GPIO);
gpio_direction_output(USDHC3_PWR_GPIO, 1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
imx_iomux_v3_setup_multiple_pads(
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
gpio_direction_input(USDHC4_CD_GPIO);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_SYS_I2C_MXC
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
#endif
return 0;
}
int board_late_init(void)
{
pfuze_init();
return 0;
}

42
board/gateworks/gw_ventana/clocks.cfg
View File

@ -1,42 +0,0 @@
/*
* Copyright (C) 2013 Boundary Devices
* Copyright (C) 2013 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4, CCM_CCOSR, 0x000000fb

29
board/gateworks/gw_ventana/gw_ventana.cfg
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2013 Gateworks Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd, nand, sata
*/
#ifdef CONFIG_SPI_FLASH
BOOT_FROM spi
#else
BOOT_FROM nand
#endif
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
#include "clocks.cfg"

28
board/gateworks/gw_ventana/gw_ventana_spl.c
View File

@ -8,6 +8,7 @@
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
@ -392,6 +393,30 @@ static void spl_dram_init(int width, int size_mb, int board_model)
mx6_dram_cfg(&sysinfo, calib, mem);
}
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0x00FFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
@ -405,6 +430,9 @@ void board_init_f(ulong dummy)
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* iomux and setup of i2c */
board_early_init_f();
i2c_setup_iomux();

28
board/kosagi/novena/novena_spl.c
View File

@ -17,6 +17,7 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/arch/crm_regs.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
@ -533,6 +534,30 @@ static struct mx6_ddr3_cfg elpida_4gib_1600 = {
.trasmin = 3590,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0x00C03F3F, &ccm->CCGR0);
writel(0x0030FC03, &ccm->CCGR1);
writel(0x0FFFC000, &ccm->CCGR2);
writel(0x3FF00000, &ccm->CCGR3);
writel(0xFFFFF300, &ccm->CCGR4);
writel(0x0F0000C3, &ccm->CCGR5);
writel(0x000003FF, &ccm->CCGR6);
}
static void gpr_init(void)
{
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
/*
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
* - we have a stack and a place to store GD, both in SRAM
@ -543,6 +568,9 @@ void board_init_f(ulong dummy)
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
gpr_init();
/* setup GP timer */
timer_init();

47
board/kosagi/novena/setup.cfg
View File

@ -1,47 +0,0 @@
/*
* Copyright (C) 2014 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/* Boot Device : sd */
BOOT_FROM sd
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* set the default clock gate to save power */
DATA 4, CCM_CCGR0, 0x00C03F3F
DATA 4, CCM_CCGR1, 0x0030FC03
DATA 4, CCM_CCGR2, 0x0FFFC000
DATA 4, CCM_CCGR3, 0x3FF00000
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
DATA 4, CCM_CCGR5, 0x0F0000C3
DATA 4, CCM_CCGR6, 0x000003FF
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
/*
* Setup CCM_CCOSR register as follows:
*
* cko1_en = 1 --> CKO1 enabled
* cko1_div = 111 --> divide by 8
* cko1_sel = 1011 --> ahb_clk_root
*
* This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
*/
DATA 4, CCM_CCOSR, 0x000000fb

13
board/tbs/tbs2910/tbs2910.c
View File

@ -219,15 +219,13 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int i;
/*
* (U-boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 eMMC
*/
int i, ret;
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
@ -251,12 +249,13 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return status;
return 0;
}
#endif /* CONFIG_FSL_ESDHC */

13
board/tqc/tqma6/tqma6.c
View File

@ -17,6 +17,7 @@
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/spi.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <libfdt.h>
@ -50,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
gd->ram_size = imx_ddr_size();
return 0;
}
@ -180,8 +181,14 @@ static struct i2c_pads_info tqma6_i2c3_pads = {
static void tqma6_setup_i2c(void)
{
/* use logical index for bus, e.g. I2C1 -> 0 */
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
int ret;
/*
* use logical index for bus, e.g. I2C1 -> 0
* warn on error
*/
ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
if (ret)
printf("setup I2C3 failed: %d\n", ret);
}
int board_early_init_f(void)

10
board/tqc/tqma6/tqma6_mba6.c
View File

@ -224,8 +224,14 @@ static struct i2c_pads_info mba6_i2c1_pads = {
static void mba6_setup_i2c(void)
{
/* use logical index for bus, e.g. I2C1 -> 0 */
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
int ret;
/*
* use logical index for bus, e.g. I2C1 -> 0
* warn on error
*/
ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads);
if (ret)
printf("setup I2C1 failed: %d\n", ret);
}

10
board/wandboard/wandboard.c
View File

@ -144,7 +144,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
s32 status = 0;
int ret;
u32 index = 0;
/*
@ -173,13 +173,15 @@ int board_mmc_init(bd_t *bis)
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
return status;
return -EINVAL;
}
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
if (ret)
return ret;
}
return status;
return 0;
}
static int mx6_rgmii_rework(struct phy_device *phydev)

24
common/cmd_sata.c
View File

@ -48,6 +48,20 @@ int __sata_initialize(void)
}
int sata_initialize(void) __attribute__((weak,alias("__sata_initialize")));
__weak int __sata_stop(void)
{
int i, err = 0;
for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++)
err |= reset_sata(i);
if (err)
printf("Could not reset some SATA devices\n");
return err;
}
int sata_stop(void) __attribute__((weak, alias("__sata_stop")));
#ifdef CONFIG_PARTITIONS
block_dev_desc_t *sata_get_dev(int dev)
{
@ -59,8 +73,15 @@ static int do_sata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
if (argc == 2 && strcmp(argv[1], "init") == 0)
if (argc == 2 && strcmp(argv[1], "stop") == 0)
return sata_stop();
if (argc == 2 && strcmp(argv[1], "init") == 0) {
if (sata_curr_device != -1)
sata_stop();
return sata_initialize();
}
/* If the user has not yet run `sata init`, do it now */
if (sata_curr_device == -1)
@ -185,6 +206,7 @@ U_BOOT_CMD(
sata, 5, 1, do_sata,
"SATA sub system",
"init - init SATA sub system\n"
"sata stop - disable SATA sub system\n"
"sata info - show available SATA devices\n"
"sata device [dev] - show or set current device\n"
"sata part [dev] - print partition table\n"

2
configs/cm_fx6_defconfig
View File

@ -1,4 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/cm_fx6/imximage.cfg,MX6QDL,SPL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_CM_FX6=y

2
configs/gwventana_defconfig
View File

@ -1,4 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_GW_VENTANA=y

2
configs/mx6sabresd_spl_defconfig
View File

@ -1,5 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_MX6SABRESD=y

2
configs/novena_defconfig
View File

@ -1,4 +1,4 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q"
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6Q"
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_KOSAGI_NOVENA=y

13
doc/README.mxsimage
View File

@ -27,7 +27,7 @@ These semantics and rules will be outlined now.
- Each line of the configuration file contains exactly one instruction.
- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
- The configuration file is a concatenation of blocks called "sections" and
optionally "DCD blocks" (see below).
optionally "DCD blocks" (see below), and optional flags lines.
- Each "section" is started by the "SECTION" instruction.
- The "SECTION" instruction has the following semantics:
@ -139,9 +139,14 @@ These semantics and rules will be outlined now.
NOOP
- This instruction does nothing.
- If the verbose output from the BootROM is enabled, the BootROM will produce a
letter on the Debug UART for each instruction it started processing. Here is a
mapping between the above instructions and the BootROM verbose output:
- An optional flags lines can be one of the following:
DISPLAYPROGRESS
- Enable boot progress output form the BootROM.
- If the boot progress output from the BootROM is enabled, the BootROM will
produce a letter on the Debug UART for each instruction it started processing.
Here is a mapping between the above instructions and the BootROM output:
H -- SB Image header loaded
T -- TAG instruction

1
drivers/Makefile
View File

@ -21,3 +21,4 @@ obj-y += pwm/
obj-y += input/
# SOC specific infrastructure drivers.
obj-y += soc/
obj-y += thermal/

5
drivers/block/ata_piix.c
View File

@ -192,6 +192,11 @@ int init_sata(int dev)
return 0;
}
int reset_sata(int dev)
{
return 0;
}
static inline u8 sata_inb(unsigned long ioaddr)
{
return inb(ioaddr);

21
drivers/block/dwc_ahsata.c
View File

@ -592,6 +592,27 @@ int init_sata(int dev)
return 0;
}
int reset_sata(int dev)
{
struct ahci_probe_ent *probe_ent =
(struct ahci_probe_ent *)sata_dev_desc[dev].priv;
struct sata_host_regs *host_mmio =
(struct sata_host_regs *)probe_ent->mmio_base;
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf("The sata index %d is out of ranges\n\r", dev);
return -1;
}
setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
udelay(100);
disable_sata_clock();
return 0;
}
static void dwc_ahsata_print_info(int dev)
{
block_dev_desc_t *pdev = &(sata_dev_desc[dev]);

5
drivers/block/fsl_sata.c
View File

@ -255,6 +255,11 @@ int init_sata(int dev)
return 0;
}
int reset_sata(int dev)
{
return 0;
}
static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
{
printf("\n\rSATA: %08x\n\r", (u32)reg);

5
drivers/block/pata_bfin.c
View File

@ -1009,6 +1009,11 @@ int init_sata(int dev)
return res;
}
int reset_sata(int dev)
{
return 0;
}
/* Read up to 255 sectors
*
* Returns sectors read

5
drivers/block/sata_dwc.c
View File

@ -423,6 +423,11 @@ int init_sata(int dev)
return rc;
}
int reset_sata(int dev)
{
return 0;
}
static u8 ata_check_altstatus(struct ata_port *ap)
{
u8 val = 0;

5
drivers/block/sata_sil.c
View File

@ -571,6 +571,11 @@ int init_sata(int dev)
return 0;
}
int reset_sata(int dev)
{
return 0;
}
/*
* SATA interface between low level driver and command layer
*/

5
drivers/block/sata_sil3114.c
View File

@ -702,6 +702,11 @@ int init_sata (int dev)
return res;
}
int reset_sata(int dev)
{
return 0;
}
/* Check if device is connected to port */
int sata_bus_probe (int portno)
{

8
drivers/mmc/fsl_esdhc.c
View File

@ -23,6 +23,13 @@
DECLARE_GLOBAL_DATA_PTR;
#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
IRQSTATEN_CINT | \
IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
IRQSTATEN_DINT)
struct fsl_esdhc {
uint dsaddr; /* SDMA system address register */
uint blkattr; /* Block attributes register */
@ -558,6 +565,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
memset(&cfg->cfg, 0, sizeof(cfg->cfg));
voltage_caps = 0;

9
drivers/thermal/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# (C) Copyright 2014 Freescale Semiconductor, Inc.
# Author: Nitin Garg <nitin.garg@freescale.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DM_THERMAL) += thermal-uclass.o
obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o

177
drivers/thermal/imx_thermal.c Normal file
View File

@ -0,0 +1,177 @@
/*
* (C) Copyright 2014 Freescale Semiconductor, Inc.
* Author: Nitin Garg <nitin.garg@freescale.com>
* Ye Li <Ye.Li@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <div64.h>
#include <fuse.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <thermal.h>
#include <imx_thermal.h>
#define TEMPERATURE_MIN -40
#define TEMPERATURE_HOT 80
#define TEMPERATURE_MAX 125
#define FACTOR0 10000000
#define FACTOR1 15976
#define FACTOR2 4297157
#define MEASURE_FREQ 327
#define TEMPSENSE0_TEMP_CNT_SHIFT 8
#define TEMPSENSE0_TEMP_CNT_MASK (0xfff << TEMPSENSE0_TEMP_CNT_SHIFT)
#define TEMPSENSE0_FINISHED (1 << 2)
#define TEMPSENSE0_MEASURE_TEMP (1 << 1)
#define TEMPSENSE0_POWER_DOWN (1 << 0)
#define MISC0_REFTOP_SELBIASOFF (1 << 3)
#define TEMPSENSE1_MEASURE_FREQ 0xffff
static int read_cpu_temperature(struct udevice *dev)
{
int temperature;
unsigned int reg, n_meas;
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
unsigned int *priv = dev_get_priv(dev);
u32 fuse = *priv;
int t1, n1;
u32 c1, c2;
u64 temp64;
/*
* Sensor data layout:
* [31:20] - sensor value @ 25C
* We use universal formula now and only need sensor value @ 25C
* slope = 0.4297157 - (0.0015976 * 25C fuse)
*/
n1 = fuse >> 20;
t1 = 25; /* t1 always 25C */
/*
* Derived from linear interpolation:
* slope = 0.4297157 - (0.0015976 * 25C fuse)
* slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
* (Nmeas - n1) / (Tmeas - t1) = slope
* We want to reduce this down to the minimum computation necessary
* for each temperature read. Also, we want Tmeas in millicelsius
* and we don't want to lose precision from integer division. So...
* Tmeas = (Nmeas - n1) / slope + t1
* milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
* milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
* Let constant c1 = (-1000 / slope)
* milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
* Let constant c2 = n1 *c1 + 1000 * t1
* milli_Tmeas = c2 - Nmeas * c1
*/
temp64 = FACTOR0;
temp64 *= 1000;
do_div(temp64, FACTOR1 * n1 - FACTOR2);
c1 = temp64;
c2 = n1 * c1 + 1000 * t1;
/*
* now we only use single measure, every time we read
* the temperature, we will power on/down anadig thermal
* module
*/
writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr);
writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
/* setup measure freq */
reg = readl(&anatop->tempsense1);
reg &= ~TEMPSENSE1_MEASURE_FREQ;
reg |= MEASURE_FREQ;
writel(reg, &anatop->tempsense1);
/* start the measurement process */
writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr);
writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
writel(TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set);
/* make sure that the latest temp is valid */
while ((readl(&anatop->tempsense0) &
TEMPSENSE0_FINISHED) == 0)
udelay(10000);
/* read temperature count */
reg = readl(&anatop->tempsense0);
n_meas = (reg & TEMPSENSE0_TEMP_CNT_MASK)
>> TEMPSENSE0_TEMP_CNT_SHIFT;
writel(TEMPSENSE0_FINISHED, &anatop->tempsense0_clr);
/* milli_Tmeas = c2 - Nmeas * c1 */
temperature = (c2 - n_meas * c1)/1000;
/* power down anatop thermal sensor */
writel(TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set);
writel(MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr);
return temperature;
}
int imx_thermal_get_temp(struct udevice *dev, int *temp)
{
int cpu_tmp = 0;
cpu_tmp = read_cpu_temperature(dev);
while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) {
if (cpu_tmp >= TEMPERATURE_HOT) {
printf("CPU Temperature is %d C, too hot to boot, waiting...\n",
cpu_tmp);
udelay(5000000);
cpu_tmp = read_cpu_temperature(dev);
} else {
break;
}
}
*temp = cpu_tmp;
return 0;
}
static const struct dm_thermal_ops imx_thermal_ops = {
.get_temp = imx_thermal_get_temp,
};
static int imx_thermal_probe(struct udevice *dev)
{
unsigned int fuse = ~0;
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
unsigned int *priv = dev_get_priv(dev);
/* Read Temperature calibration data fuse */
fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
/* Check for valid fuse */
if (fuse == 0 || fuse == ~0) {
printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
return -EPERM;
} else {
printf("CPU: Thermal calibration data: 0x%x\n", fuse);
}
*priv = fuse;
enable_thermal_clk();
return 0;
}
U_BOOT_DRIVER(imx_thermal) = {
.name = "imx_thermal",
.id = UCLASS_THERMAL,
.ops = &imx_thermal_ops,
.probe = imx_thermal_probe,
.priv_auto_alloc_size = sizeof(unsigned int),
.flags = DM_FLAG_PRE_RELOC,
};

30
drivers/thermal/thermal-uclass.c Normal file
View File

@ -0,0 +1,30 @@
/*
* (C) Copyright 2014 Freescale Semiconductor, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <thermal.h>
#include <errno.h>
#include <fdtdec.h>
#include <malloc.h>
#include <asm/io.h>
#include <linux/list.h>
int thermal_get_temp(struct udevice *dev, int *temp)
{
const struct dm_thermal_ops *ops = device_get_ops(dev);
if (!ops->get_temp)
return -ENOSYS;
return ops->get_temp(dev, temp);
}
UCLASS_DRIVER(thermal) = {
.id = UCLASS_THERMAL,
.name = "thermal",
};

16
include/configs/mx6qsabreauto.h
View File

@ -37,6 +37,16 @@
#include "mx6sabre_common.h"
#undef CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
@ -64,4 +74,10 @@
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
/* PMIC */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
#endif /* __MX6QSABREAUTO_CONFIG_H */

7
include/configs/mx6sabre_common.h
View File

@ -25,6 +25,11 @@
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_DM
#define CONFIG_DM_THERMAL
#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
#define CONFIG_IMX6_THERMAL
#define CONFIG_SYS_GENERIC_BOARD
/* Size of malloc() pool */
@ -37,7 +42,7 @@
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
#ifdef CONFIG_CMD_FUSE
#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
#define CONFIG_MXC_OCOTP
#endif

2
include/configs/mx6slevk.h
View File

@ -87,7 +87,7 @@
"fdt_addr=0x88000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcdev=1\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \

8
include/configs/mx6sxsabresd.h
View File

@ -59,7 +59,7 @@
"fdt_addr=0x88000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
"mmcdev=0\0" \
"mmcdev=2\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
@ -214,7 +214,6 @@
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
@ -223,4 +222,9 @@
#define CONFIG_CMD_CACHE
#endif
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
#endif
#endif /* __CONFIG_H */

28
include/configs/tqma6.h
View File

@ -68,6 +68,8 @@
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
@ -275,12 +277,10 @@
#elif defined(CONFIG_TQMA6X_SPI_BOOT)
#define CONFIG_FLASH_SECTOR_SIZE 0x10000
#define TQMA6_UBOOT_OFFSET 0x400
#define TQMA6_UBOOT_SECTOR_START 0x0
/* max u-boot size: 512k */
#define TQMA6_UBOOT_SECTOR_SIZE CONFIG_FLASH_SECTOR_SIZE
#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
#define TQMA6_UBOOT_SECTOR_COUNT 0x8
#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \
TQMA6_UBOOT_SECTOR_COUNT)
@ -288,7 +288,7 @@
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE)
#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
@ -299,7 +299,7 @@
#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \
CONFIG_ENV_SECT_SIZE)
#define TQMA6_FDT_SECT_SIZE (CONFIG_FLASH_SECTOR_SIZE)
#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE)
#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */
#define TQMA6_FDT_SECTOR_COUNT 0x01
@ -320,7 +320,7 @@
"setexpr blkc ${filesize} + " \
__stringify(TQMA6_UBOOT_OFFSET) "; " \
"setexpr size ${uboot_sectors} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"if itest ${blkc} <= ${size}; then " \
"sf probe; " \
"sf erase 0 ${size}; " \
@ -332,9 +332,9 @@
"update_kernel=run kernel_name; if tftp ${kernel}; then " \
"if itest ${filesize} > 0; then " \
"setexpr size ${kernel_sectors} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${kernel_start} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"if itest ${filesize} <= ${size}; then " \
"sf probe; " \
"sf erase ${offset} ${size}; " \
@ -346,9 +346,9 @@
"update_fdt=if tftp ${fdt_file}; then " \
"if itest ${filesize} > 0; then " \
"setexpr size ${fdt_sectors} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${fdt_start} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"if itest ${filesize} <= ${size}; then " \
"sf probe; " \
"sf erase ${offset} ${size}; " \
@ -359,16 +359,16 @@
"setenv filesize 0; setenv size ; setenv offset\0" \
"loadimage=sf probe; " \
"setexpr size ${kernel_sectors} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${kernel_start} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"sf read ${loadaddr} ${offset} ${size}; " \
"setenv size ; setenv offset\0" \
"loadfdt=sf probe; " \
"setexpr size ${fdt_sectors} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"setexpr offset ${fdt_start} * " \
__stringify(CONFIG_FLASH_SECTOR_SIZE)"; " \
__stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \
"sf read ${${fdt_addr}} ${offset} ${size}; " \
"setenv size ; setenv offset\0" \

1
include/dm/uclass-id.h
View File

@ -28,6 +28,7 @@ enum uclass_id {
UCLASS_SPI_GENERIC, /* Generic SPI flash target */
UCLASS_SPI_FLASH, /* SPI flash */
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_THERMAL, /* Thermal sensor */
UCLASS_COUNT,
UCLASS_INVALID = -1,

17
include/imx_thermal.h Normal file
View File

@ -0,0 +1,17 @@
/*
*
* (C) Copyright 2014 Freescale Semiconductor, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _IMX_THERMAL_H_
#define _IMX_THERMAL_H_
struct imx_thermal_plat {
void *regs;
int fuse_bank;
int fuse_word;
};
#endif /* _IMX_THERMAL_H_ */

80
include/power/pfuze100_pmic.h
View File

@ -37,6 +37,86 @@ enum {
PMIC_NUM_OF_REGS = 0x7f,
};
/*
* Buck Regulators
*/
/* SW1A/B/C Output Voltage Configuration */
#define SW1x_0_300V 0
#define SW1x_0_325V 1
#define SW1x_0_350V 2
#define SW1x_0_375V 3
#define SW1x_0_400V 4
#define SW1x_0_425V 5
#define SW1x_0_450V 6
#define SW1x_0_475V 7
#define SW1x_0_500V 8
#define SW1x_0_525V 9
#define SW1x_0_550V 10
#define SW1x_0_575V 11
#define SW1x_0_600V 12
#define SW1x_0_625V 13
#define SW1x_0_650V 14
#define SW1x_0_675V 15
#define SW1x_0_700V 16
#define SW1x_0_725V 17
#define SW1x_0_750V 18
#define SW1x_0_775V 19
#define SW1x_0_800V 20
#define SW1x_0_825V 21
#define SW1x_0_850V 22
#define SW1x_0_875V 23
#define SW1x_0_900V 24
#define SW1x_0_925V 25
#define SW1x_0_950V 26
#define SW1x_0_975V 27
#define SW1x_1_000V 28
#define SW1x_1_025V 29
#define SW1x_1_050V 30
#define SW1x_1_075V 31
#define SW1x_1_100V 32
#define SW1x_1_125V 33
#define SW1x_1_150V 34
#define SW1x_1_175V 35
#define SW1x_1_200V 36
#define SW1x_1_225V 37
#define SW1x_1_250V 38
#define SW1x_1_275V 39
#define SW1x_1_300V 40
#define SW1x_1_325V 41
#define SW1x_1_350V 42
#define SW1x_1_375V 43
#define SW1x_1_400V 44
#define SW1x_1_425V 45
#define SW1x_1_450V 46
#define SW1x_1_475V 47
#define SW1x_1_500V 48
#define SW1x_1_525V 49
#define SW1x_1_550V 50
#define SW1x_1_575V 51
#define SW1x_1_600V 52
#define SW1x_1_625V 53
#define SW1x_1_650V 54
#define SW1x_1_675V 55
#define SW1x_1_700V 56
#define SW1x_1_725V 57
#define SW1x_1_750V 58
#define SW1x_1_775V 59
#define SW1x_1_800V 60
#define SW1x_1_825V 61
#define SW1x_1_850V 62
#define SW1x_1_875V 63
#define SW1x_NORMAL_MASK 0x3f
#define SW1x_STBY_MASK 0x3f
#define SW1x_OFF_MASK 0x3f
#define SW1xCONF_DVSSPEED_MASK 0xc0
#define SW1xCONF_DVSSPEED_2US 0x00
#define SW1xCONF_DVSSPEED_4US 0x40
#define SW1xCONF_DVSSPEED_8US 0x80
#define SW1xCONF_DVSSPEED_16US 0xc0
/*
* LDO Configuration
*/

3
include/sata.h
View File

@ -3,12 +3,15 @@
#include <part.h>
int init_sata(int dev);
int reset_sata(int dev);
int scan_sata(int dev);
ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
int sata_initialize(void);
int __sata_initialize(void);
int sata_stop(void);
int __sata_stop(void);
int sata_port_status(int dev, int port);
extern block_dev_desc_t sata_dev_desc[];

42
include/thermal.h Normal file
View File

@ -0,0 +1,42 @@
/*
*
* (C) Copyright 2014 Freescale Semiconductor, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _THERMAL_H_
#define _THERMAL_H_
#include <dm.h>
int thermal_get_temp(struct udevice *dev, int *temp);
/**
* struct struct dm_thermal_ops - Driver model Thermal operations
*
* The uclass interface is implemented by all Thermal devices which use
* driver model.
*/
struct dm_thermal_ops {
/**
* Get the current temperature
*
* The device provided is the slave device. It's parent controller
* will be used to provide the communication.
*
* This must be called before doing any transfers with a Thermal slave.
* It will enable and initialize any Thermal hardware as necessary,
* and make sure that the SCK line is in the correct idle state. It is
* not allowed to claim the same bus for several slaves without
* releasing the bus in between.
*
* @dev: The Thermal device
*
* Returns: 0 if the bus was claimed successfully, or a negative value
* if it wasn't.
*/
int (*get_temp)(struct udevice *dev, int *temp);
};
#endif /* _THERMAL_H_ */

20
tools/mxsimage.c
View File

@ -125,7 +125,7 @@ struct sb_image_ctx {
unsigned int in_section:1;
unsigned int in_dcd:1;
/* Image configuration */
unsigned int verbose_boot:1;
unsigned int display_progress:1;
unsigned int silent_dump:1;
char *input_filename;
char *output_filename;
@ -1308,8 +1308,8 @@ static int sb_prefill_image_header(struct sb_image_ctx *ictx)
sizeof(struct sb_sections_header) / SB_BLOCK_SIZE;
hdr->timestamp_us = sb_get_timestamp() * 1000000;
/* FIXME -- add proper config option */
hdr->flags = ictx->verbose_boot ? SB_IMAGE_FLAG_VERBOSE : 0,
hdr->flags = ictx->display_progress ?
SB_IMAGE_FLAG_DISPLAY_PROGRESS : 0;
/* FIXME -- We support only default key */
hdr->key_count = 1;
@ -1416,7 +1416,7 @@ static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd)
{
char *tok;
char *line = cmd->cmd;
char *rptr;
char *rptr = NULL;
int ret;
/* Analyze the identifier on this line first. */
@ -1428,6 +1428,12 @@ static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd)
cmd->cmd = rptr;
/* set DISPLAY_PROGRESS flag */
if (!strcmp(tok, "DISPLAYPROGRESS")) {
ictx->display_progress = 1;
return 0;
}
/* DCD */
if (!strcmp(tok, "DCD")) {
ictx->in_section = 0;
@ -1681,10 +1687,11 @@ static int sb_verify_image_header(struct sb_image_ctx *ictx,
ntohs(hdr->component_version.minor),
ntohs(hdr->component_version.revision));
if (hdr->flags & ~SB_IMAGE_FLAG_VERBOSE)
if (hdr->flags & ~SB_IMAGE_FLAGS_MASK)
ret = -EINVAL;
soprintf(ictx, "%s Image flags: %s\n", stat[!!ret],
hdr->flags & SB_IMAGE_FLAG_VERBOSE ? "Verbose_boot" : "");
hdr->flags & SB_IMAGE_FLAG_DISPLAY_PROGRESS ?
"Display_progress" : "");
if (ret)
return ret;
@ -2287,7 +2294,6 @@ static int mxsimage_generate(struct image_tool_params *params,
ctx.cfg_filename = params->imagename;
ctx.output_filename = params->imagefile;
ctx.verbose_boot = 1;
ret = sb_build_tree_from_cfg(&ctx);
if (ret)

5
tools/mxsimage.h
View File

@ -81,8 +81,9 @@ struct sb_boot_image_header {
#define SB_VERSION_MAJOR 1
#define SB_VERSION_MINOR 1
/* Enable to HTLLC verbose boot report. */
#define SB_IMAGE_FLAG_VERBOSE (1 << 0)
/* Enable to HTLLC boot report. */
#define SB_IMAGE_FLAG_DISPLAY_PROGRESS (1 << 0)
#define SB_IMAGE_FLAGS_MASK SB_IMAGE_FLAG_DISPLAY_PROGRESS
struct sb_key_dictionary_key {
/* The CBC-MAC of image and sections header. */