mxs: prefix register acessor macros with 'mxs' prefix
As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Otavio Salvador
Albert ARIBAUD
parent
3a0398d7b9
commit
ddcf13b152
|
|
@ -207,7 +207,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
|
|||
return;
|
||||
|
||||
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
|
||||
(ssp * sizeof(struct mx28_register_32));
|
||||
(ssp * sizeof(struct mxs_register_32));
|
||||
|
||||
clrbits_le32(clkreg, CLKCTRL_SSP_CLKGATE);
|
||||
while (readl(clkreg) & CLKCTRL_SSP_CLKGATE)
|
||||
|
|
@ -256,7 +256,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
|
|||
return XTAL_FREQ_KHZ;
|
||||
|
||||
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
|
||||
(ssp * sizeof(struct mx28_register_32));
|
||||
(ssp * sizeof(struct mxs_register_32));
|
||||
|
||||
tmp = readl(clkreg) & CLKCTRL_SSP_DIV_MASK;
|
||||
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
|
|||
{
|
||||
u32 reg, ofs, bp, bm;
|
||||
void *iomux_base = (void *)MXS_PINCTRL_BASE;
|
||||
struct mx28_register_32 *mxs_reg;
|
||||
struct mxs_register_32 *mxs_reg;
|
||||
|
||||
/* muxsel */
|
||||
ofs = 0x100;
|
||||
|
|
@ -70,7 +70,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
|
|||
/* vol */
|
||||
if (PAD_VOL_VALID(pad)) {
|
||||
bp = PAD_PIN(pad) % 8 * 4 + 2;
|
||||
mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
|
||||
mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
|
||||
if (PAD_VOL(pad))
|
||||
writel(1 << bp, &mxs_reg->reg_set);
|
||||
else
|
||||
|
|
@ -82,7 +82,7 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad)
|
|||
ofs = PULL_OFFSET;
|
||||
ofs += PAD_BANK(pad) * 0x10;
|
||||
bp = PAD_PIN(pad);
|
||||
mxs_reg = (struct mx28_register_32 *)(iomux_base + ofs);
|
||||
mxs_reg = (struct mxs_register_32 *)(iomux_base + ofs);
|
||||
if (PAD_PULL(pad))
|
||||
writel(1 << bp, &mxs_reg->reg_set);
|
||||
else
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ void enable_caches(void)
|
|||
#endif
|
||||
}
|
||||
|
||||
int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
|
||||
int mx28_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, int timeout)
|
||||
{
|
||||
while (--timeout) {
|
||||
if ((readl(®->reg) & mask) == mask)
|
||||
|
|
@ -92,7 +92,7 @@ int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
|
|||
return !timeout;
|
||||
}
|
||||
|
||||
int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
|
||||
int mx28_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, int timeout)
|
||||
{
|
||||
while (--timeout) {
|
||||
if ((readl(®->reg) & mask) == 0)
|
||||
|
|
@ -103,7 +103,7 @@ int mx28_wait_mask_clr(struct mx28_register_32 *reg, uint32_t mask, int timeout)
|
|||
return !timeout;
|
||||
}
|
||||
|
||||
int mx28_reset_block(struct mx28_register_32 *reg)
|
||||
int mx28_reset_block(struct mxs_register_32 *reg)
|
||||
{
|
||||
/* Clear SFTRST */
|
||||
writel(MX28_BLOCK_SFTRST, ®->reg_clr);
|
||||
|
|
|
|||
|
|
@ -30,142 +30,142 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_apbh_regs {
|
||||
mx28_reg_32(hw_apbh_ctrl0)
|
||||
mx28_reg_32(hw_apbh_ctrl1)
|
||||
mx28_reg_32(hw_apbh_ctrl2)
|
||||
mx28_reg_32(hw_apbh_channel_ctrl)
|
||||
mx28_reg_32(hw_apbh_devsel)
|
||||
mx28_reg_32(hw_apbh_dma_burst_size)
|
||||
mx28_reg_32(hw_apbh_debug)
|
||||
mxs_reg_32(hw_apbh_ctrl0)
|
||||
mxs_reg_32(hw_apbh_ctrl1)
|
||||
mxs_reg_32(hw_apbh_ctrl2)
|
||||
mxs_reg_32(hw_apbh_channel_ctrl)
|
||||
mxs_reg_32(hw_apbh_devsel)
|
||||
mxs_reg_32(hw_apbh_dma_burst_size)
|
||||
mxs_reg_32(hw_apbh_debug)
|
||||
|
||||
uint32_t reserved[36];
|
||||
|
||||
union {
|
||||
struct {
|
||||
mx28_reg_32(hw_apbh_ch_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch_cmd)
|
||||
mx28_reg_32(hw_apbh_ch_bar)
|
||||
mx28_reg_32(hw_apbh_ch_sema)
|
||||
mx28_reg_32(hw_apbh_ch_debug1)
|
||||
mx28_reg_32(hw_apbh_ch_debug2)
|
||||
mxs_reg_32(hw_apbh_ch_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch_cmd)
|
||||
mxs_reg_32(hw_apbh_ch_bar)
|
||||
mxs_reg_32(hw_apbh_ch_sema)
|
||||
mxs_reg_32(hw_apbh_ch_debug1)
|
||||
mxs_reg_32(hw_apbh_ch_debug2)
|
||||
} ch[16];
|
||||
struct {
|
||||
mx28_reg_32(hw_apbh_ch0_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch0_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch0_cmd)
|
||||
mx28_reg_32(hw_apbh_ch0_bar)
|
||||
mx28_reg_32(hw_apbh_ch0_sema)
|
||||
mx28_reg_32(hw_apbh_ch0_debug1)
|
||||
mx28_reg_32(hw_apbh_ch0_debug2)
|
||||
mx28_reg_32(hw_apbh_ch1_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch1_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch1_cmd)
|
||||
mx28_reg_32(hw_apbh_ch1_bar)
|
||||
mx28_reg_32(hw_apbh_ch1_sema)
|
||||
mx28_reg_32(hw_apbh_ch1_debug1)
|
||||
mx28_reg_32(hw_apbh_ch1_debug2)
|
||||
mx28_reg_32(hw_apbh_ch2_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch2_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch2_cmd)
|
||||
mx28_reg_32(hw_apbh_ch2_bar)
|
||||
mx28_reg_32(hw_apbh_ch2_sema)
|
||||
mx28_reg_32(hw_apbh_ch2_debug1)
|
||||
mx28_reg_32(hw_apbh_ch2_debug2)
|
||||
mx28_reg_32(hw_apbh_ch3_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch3_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch3_cmd)
|
||||
mx28_reg_32(hw_apbh_ch3_bar)
|
||||
mx28_reg_32(hw_apbh_ch3_sema)
|
||||
mx28_reg_32(hw_apbh_ch3_debug1)
|
||||
mx28_reg_32(hw_apbh_ch3_debug2)
|
||||
mx28_reg_32(hw_apbh_ch4_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch4_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch4_cmd)
|
||||
mx28_reg_32(hw_apbh_ch4_bar)
|
||||
mx28_reg_32(hw_apbh_ch4_sema)
|
||||
mx28_reg_32(hw_apbh_ch4_debug1)
|
||||
mx28_reg_32(hw_apbh_ch4_debug2)
|
||||
mx28_reg_32(hw_apbh_ch5_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch5_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch5_cmd)
|
||||
mx28_reg_32(hw_apbh_ch5_bar)
|
||||
mx28_reg_32(hw_apbh_ch5_sema)
|
||||
mx28_reg_32(hw_apbh_ch5_debug1)
|
||||
mx28_reg_32(hw_apbh_ch5_debug2)
|
||||
mx28_reg_32(hw_apbh_ch6_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch6_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch6_cmd)
|
||||
mx28_reg_32(hw_apbh_ch6_bar)
|
||||
mx28_reg_32(hw_apbh_ch6_sema)
|
||||
mx28_reg_32(hw_apbh_ch6_debug1)
|
||||
mx28_reg_32(hw_apbh_ch6_debug2)
|
||||
mx28_reg_32(hw_apbh_ch7_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch7_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch7_cmd)
|
||||
mx28_reg_32(hw_apbh_ch7_bar)
|
||||
mx28_reg_32(hw_apbh_ch7_sema)
|
||||
mx28_reg_32(hw_apbh_ch7_debug1)
|
||||
mx28_reg_32(hw_apbh_ch7_debug2)
|
||||
mx28_reg_32(hw_apbh_ch8_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch8_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch8_cmd)
|
||||
mx28_reg_32(hw_apbh_ch8_bar)
|
||||
mx28_reg_32(hw_apbh_ch8_sema)
|
||||
mx28_reg_32(hw_apbh_ch8_debug1)
|
||||
mx28_reg_32(hw_apbh_ch8_debug2)
|
||||
mx28_reg_32(hw_apbh_ch9_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch9_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch9_cmd)
|
||||
mx28_reg_32(hw_apbh_ch9_bar)
|
||||
mx28_reg_32(hw_apbh_ch9_sema)
|
||||
mx28_reg_32(hw_apbh_ch9_debug1)
|
||||
mx28_reg_32(hw_apbh_ch9_debug2)
|
||||
mx28_reg_32(hw_apbh_ch10_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch10_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch10_cmd)
|
||||
mx28_reg_32(hw_apbh_ch10_bar)
|
||||
mx28_reg_32(hw_apbh_ch10_sema)
|
||||
mx28_reg_32(hw_apbh_ch10_debug1)
|
||||
mx28_reg_32(hw_apbh_ch10_debug2)
|
||||
mx28_reg_32(hw_apbh_ch11_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch11_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch11_cmd)
|
||||
mx28_reg_32(hw_apbh_ch11_bar)
|
||||
mx28_reg_32(hw_apbh_ch11_sema)
|
||||
mx28_reg_32(hw_apbh_ch11_debug1)
|
||||
mx28_reg_32(hw_apbh_ch11_debug2)
|
||||
mx28_reg_32(hw_apbh_ch12_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch12_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch12_cmd)
|
||||
mx28_reg_32(hw_apbh_ch12_bar)
|
||||
mx28_reg_32(hw_apbh_ch12_sema)
|
||||
mx28_reg_32(hw_apbh_ch12_debug1)
|
||||
mx28_reg_32(hw_apbh_ch12_debug2)
|
||||
mx28_reg_32(hw_apbh_ch13_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch13_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch13_cmd)
|
||||
mx28_reg_32(hw_apbh_ch13_bar)
|
||||
mx28_reg_32(hw_apbh_ch13_sema)
|
||||
mx28_reg_32(hw_apbh_ch13_debug1)
|
||||
mx28_reg_32(hw_apbh_ch13_debug2)
|
||||
mx28_reg_32(hw_apbh_ch14_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch14_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch14_cmd)
|
||||
mx28_reg_32(hw_apbh_ch14_bar)
|
||||
mx28_reg_32(hw_apbh_ch14_sema)
|
||||
mx28_reg_32(hw_apbh_ch14_debug1)
|
||||
mx28_reg_32(hw_apbh_ch14_debug2)
|
||||
mx28_reg_32(hw_apbh_ch15_curcmdar)
|
||||
mx28_reg_32(hw_apbh_ch15_nxtcmdar)
|
||||
mx28_reg_32(hw_apbh_ch15_cmd)
|
||||
mx28_reg_32(hw_apbh_ch15_bar)
|
||||
mx28_reg_32(hw_apbh_ch15_sema)
|
||||
mx28_reg_32(hw_apbh_ch15_debug1)
|
||||
mx28_reg_32(hw_apbh_ch15_debug2)
|
||||
mxs_reg_32(hw_apbh_ch0_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch0_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch0_cmd)
|
||||
mxs_reg_32(hw_apbh_ch0_bar)
|
||||
mxs_reg_32(hw_apbh_ch0_sema)
|
||||
mxs_reg_32(hw_apbh_ch0_debug1)
|
||||
mxs_reg_32(hw_apbh_ch0_debug2)
|
||||
mxs_reg_32(hw_apbh_ch1_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch1_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch1_cmd)
|
||||
mxs_reg_32(hw_apbh_ch1_bar)
|
||||
mxs_reg_32(hw_apbh_ch1_sema)
|
||||
mxs_reg_32(hw_apbh_ch1_debug1)
|
||||
mxs_reg_32(hw_apbh_ch1_debug2)
|
||||
mxs_reg_32(hw_apbh_ch2_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch2_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch2_cmd)
|
||||
mxs_reg_32(hw_apbh_ch2_bar)
|
||||
mxs_reg_32(hw_apbh_ch2_sema)
|
||||
mxs_reg_32(hw_apbh_ch2_debug1)
|
||||
mxs_reg_32(hw_apbh_ch2_debug2)
|
||||
mxs_reg_32(hw_apbh_ch3_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch3_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch3_cmd)
|
||||
mxs_reg_32(hw_apbh_ch3_bar)
|
||||
mxs_reg_32(hw_apbh_ch3_sema)
|
||||
mxs_reg_32(hw_apbh_ch3_debug1)
|
||||
mxs_reg_32(hw_apbh_ch3_debug2)
|
||||
mxs_reg_32(hw_apbh_ch4_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch4_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch4_cmd)
|
||||
mxs_reg_32(hw_apbh_ch4_bar)
|
||||
mxs_reg_32(hw_apbh_ch4_sema)
|
||||
mxs_reg_32(hw_apbh_ch4_debug1)
|
||||
mxs_reg_32(hw_apbh_ch4_debug2)
|
||||
mxs_reg_32(hw_apbh_ch5_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch5_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch5_cmd)
|
||||
mxs_reg_32(hw_apbh_ch5_bar)
|
||||
mxs_reg_32(hw_apbh_ch5_sema)
|
||||
mxs_reg_32(hw_apbh_ch5_debug1)
|
||||
mxs_reg_32(hw_apbh_ch5_debug2)
|
||||
mxs_reg_32(hw_apbh_ch6_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch6_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch6_cmd)
|
||||
mxs_reg_32(hw_apbh_ch6_bar)
|
||||
mxs_reg_32(hw_apbh_ch6_sema)
|
||||
mxs_reg_32(hw_apbh_ch6_debug1)
|
||||
mxs_reg_32(hw_apbh_ch6_debug2)
|
||||
mxs_reg_32(hw_apbh_ch7_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch7_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch7_cmd)
|
||||
mxs_reg_32(hw_apbh_ch7_bar)
|
||||
mxs_reg_32(hw_apbh_ch7_sema)
|
||||
mxs_reg_32(hw_apbh_ch7_debug1)
|
||||
mxs_reg_32(hw_apbh_ch7_debug2)
|
||||
mxs_reg_32(hw_apbh_ch8_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch8_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch8_cmd)
|
||||
mxs_reg_32(hw_apbh_ch8_bar)
|
||||
mxs_reg_32(hw_apbh_ch8_sema)
|
||||
mxs_reg_32(hw_apbh_ch8_debug1)
|
||||
mxs_reg_32(hw_apbh_ch8_debug2)
|
||||
mxs_reg_32(hw_apbh_ch9_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch9_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch9_cmd)
|
||||
mxs_reg_32(hw_apbh_ch9_bar)
|
||||
mxs_reg_32(hw_apbh_ch9_sema)
|
||||
mxs_reg_32(hw_apbh_ch9_debug1)
|
||||
mxs_reg_32(hw_apbh_ch9_debug2)
|
||||
mxs_reg_32(hw_apbh_ch10_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch10_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch10_cmd)
|
||||
mxs_reg_32(hw_apbh_ch10_bar)
|
||||
mxs_reg_32(hw_apbh_ch10_sema)
|
||||
mxs_reg_32(hw_apbh_ch10_debug1)
|
||||
mxs_reg_32(hw_apbh_ch10_debug2)
|
||||
mxs_reg_32(hw_apbh_ch11_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch11_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch11_cmd)
|
||||
mxs_reg_32(hw_apbh_ch11_bar)
|
||||
mxs_reg_32(hw_apbh_ch11_sema)
|
||||
mxs_reg_32(hw_apbh_ch11_debug1)
|
||||
mxs_reg_32(hw_apbh_ch11_debug2)
|
||||
mxs_reg_32(hw_apbh_ch12_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch12_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch12_cmd)
|
||||
mxs_reg_32(hw_apbh_ch12_bar)
|
||||
mxs_reg_32(hw_apbh_ch12_sema)
|
||||
mxs_reg_32(hw_apbh_ch12_debug1)
|
||||
mxs_reg_32(hw_apbh_ch12_debug2)
|
||||
mxs_reg_32(hw_apbh_ch13_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch13_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch13_cmd)
|
||||
mxs_reg_32(hw_apbh_ch13_bar)
|
||||
mxs_reg_32(hw_apbh_ch13_sema)
|
||||
mxs_reg_32(hw_apbh_ch13_debug1)
|
||||
mxs_reg_32(hw_apbh_ch13_debug2)
|
||||
mxs_reg_32(hw_apbh_ch14_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch14_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch14_cmd)
|
||||
mxs_reg_32(hw_apbh_ch14_bar)
|
||||
mxs_reg_32(hw_apbh_ch14_sema)
|
||||
mxs_reg_32(hw_apbh_ch14_debug1)
|
||||
mxs_reg_32(hw_apbh_ch14_debug2)
|
||||
mxs_reg_32(hw_apbh_ch15_curcmdar)
|
||||
mxs_reg_32(hw_apbh_ch15_nxtcmdar)
|
||||
mxs_reg_32(hw_apbh_ch15_cmd)
|
||||
mxs_reg_32(hw_apbh_ch15_bar)
|
||||
mxs_reg_32(hw_apbh_ch15_sema)
|
||||
mxs_reg_32(hw_apbh_ch15_debug1)
|
||||
mxs_reg_32(hw_apbh_ch15_debug2)
|
||||
};
|
||||
};
|
||||
mx28_reg_32(hw_apbh_version)
|
||||
mxs_reg_32(hw_apbh_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -30,30 +30,30 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_bch_regs {
|
||||
mx28_reg_32(hw_bch_ctrl)
|
||||
mx28_reg_32(hw_bch_status0)
|
||||
mx28_reg_32(hw_bch_mode)
|
||||
mx28_reg_32(hw_bch_encodeptr)
|
||||
mx28_reg_32(hw_bch_dataptr)
|
||||
mx28_reg_32(hw_bch_metaptr)
|
||||
mxs_reg_32(hw_bch_ctrl)
|
||||
mxs_reg_32(hw_bch_status0)
|
||||
mxs_reg_32(hw_bch_mode)
|
||||
mxs_reg_32(hw_bch_encodeptr)
|
||||
mxs_reg_32(hw_bch_dataptr)
|
||||
mxs_reg_32(hw_bch_metaptr)
|
||||
|
||||
uint32_t reserved[4];
|
||||
|
||||
mx28_reg_32(hw_bch_layoutselect)
|
||||
mx28_reg_32(hw_bch_flash0layout0)
|
||||
mx28_reg_32(hw_bch_flash0layout1)
|
||||
mx28_reg_32(hw_bch_flash1layout0)
|
||||
mx28_reg_32(hw_bch_flash1layout1)
|
||||
mx28_reg_32(hw_bch_flash2layout0)
|
||||
mx28_reg_32(hw_bch_flash2layout1)
|
||||
mx28_reg_32(hw_bch_flash3layout0)
|
||||
mx28_reg_32(hw_bch_flash3layout1)
|
||||
mx28_reg_32(hw_bch_dbgkesread)
|
||||
mx28_reg_32(hw_bch_dbgcsferead)
|
||||
mx28_reg_32(hw_bch_dbgsyndegread)
|
||||
mx28_reg_32(hw_bch_dbgahbmread)
|
||||
mx28_reg_32(hw_bch_blockname)
|
||||
mx28_reg_32(hw_bch_version)
|
||||
mxs_reg_32(hw_bch_layoutselect)
|
||||
mxs_reg_32(hw_bch_flash0layout0)
|
||||
mxs_reg_32(hw_bch_flash0layout1)
|
||||
mxs_reg_32(hw_bch_flash1layout0)
|
||||
mxs_reg_32(hw_bch_flash1layout1)
|
||||
mxs_reg_32(hw_bch_flash2layout0)
|
||||
mxs_reg_32(hw_bch_flash2layout1)
|
||||
mxs_reg_32(hw_bch_flash3layout0)
|
||||
mxs_reg_32(hw_bch_flash3layout1)
|
||||
mxs_reg_32(hw_bch_dbgkesread)
|
||||
mxs_reg_32(hw_bch_dbgcsferead)
|
||||
mxs_reg_32(hw_bch_dbgsyndegread)
|
||||
mxs_reg_32(hw_bch_dbgahbmread)
|
||||
mxs_reg_32(hw_bch_blockname)
|
||||
mxs_reg_32(hw_bch_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -30,38 +30,38 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_clkctrl_regs {
|
||||
mx28_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
|
||||
mx28_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
|
||||
mx28_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
|
||||
mx28_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
|
||||
mx28_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
|
||||
mx28_reg_32(hw_clkctrl_cpu) /* 0x50 */
|
||||
mx28_reg_32(hw_clkctrl_hbus) /* 0x60 */
|
||||
mx28_reg_32(hw_clkctrl_xbus) /* 0x70 */
|
||||
mx28_reg_32(hw_clkctrl_xtal) /* 0x80 */
|
||||
mx28_reg_32(hw_clkctrl_ssp0) /* 0x90 */
|
||||
mx28_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
|
||||
mx28_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
|
||||
mx28_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
|
||||
mx28_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
|
||||
mx28_reg_32(hw_clkctrl_spdif) /* 0xe0 */
|
||||
mx28_reg_32(hw_clkctrl_emi) /* 0xf0 */
|
||||
mx28_reg_32(hw_clkctrl_saif0) /* 0x100 */
|
||||
mx28_reg_32(hw_clkctrl_saif1) /* 0x110 */
|
||||
mx28_reg_32(hw_clkctrl_lcdif) /* 0x120 */
|
||||
mx28_reg_32(hw_clkctrl_etm) /* 0x130 */
|
||||
mx28_reg_32(hw_clkctrl_enet) /* 0x140 */
|
||||
mx28_reg_32(hw_clkctrl_hsadc) /* 0x150 */
|
||||
mx28_reg_32(hw_clkctrl_flexcan) /* 0x160 */
|
||||
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
|
||||
mxs_reg_32(hw_clkctrl_pll0ctrl1) /* 0x10 */
|
||||
mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */
|
||||
mxs_reg_32(hw_clkctrl_pll1ctrl1) /* 0x30 */
|
||||
mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */
|
||||
mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */
|
||||
mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */
|
||||
mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */
|
||||
mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */
|
||||
mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */
|
||||
mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */
|
||||
mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */
|
||||
mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */
|
||||
mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */
|
||||
mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */
|
||||
mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */
|
||||
mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */
|
||||
mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */
|
||||
mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */
|
||||
mxs_reg_32(hw_clkctrl_etm) /* 0x130 */
|
||||
mxs_reg_32(hw_clkctrl_enet) /* 0x140 */
|
||||
mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */
|
||||
mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */
|
||||
|
||||
uint32_t reserved[16];
|
||||
|
||||
mx28_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
|
||||
mx28_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
|
||||
mx28_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
|
||||
mx28_reg_32(hw_clkctrl_reset) /* 0x1e0 */
|
||||
mx28_reg_32(hw_clkctrl_status) /* 0x1f0 */
|
||||
mx28_reg_32(hw_clkctrl_version) /* 0x200 */
|
||||
mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */
|
||||
mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */
|
||||
mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */
|
||||
mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */
|
||||
mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */
|
||||
mxs_reg_32(hw_clkctrl_version) /* 0x200 */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Freescale i.MX28 Register Accessors
|
||||
* Freescale i.MXS Register Accessors
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
|
|
@ -20,11 +20,11 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef __MX28_REGS_COMMON_H__
|
||||
#define __MX28_REGS_COMMON_H__
|
||||
#ifndef __MXS_REGS_COMMON_H__
|
||||
#define __MXS_REGS_COMMON_H__
|
||||
|
||||
/*
|
||||
* The i.MX28 has interesting feature when it comes to register access. There
|
||||
* The i.MXS has interesting feature when it comes to register access. There
|
||||
* are four kinds of access to one particular register. Those are:
|
||||
*
|
||||
* 1) Common read/write access. To use this mode, just write to the address of
|
||||
|
|
@ -47,36 +47,36 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#define __mx28_reg_8(name) \
|
||||
#define __mxs_reg_8(name) \
|
||||
uint8_t name[4]; \
|
||||
uint8_t name##_set[4]; \
|
||||
uint8_t name##_clr[4]; \
|
||||
uint8_t name##_tog[4]; \
|
||||
|
||||
#define __mx28_reg_32(name) \
|
||||
#define __mxs_reg_32(name) \
|
||||
uint32_t name; \
|
||||
uint32_t name##_set; \
|
||||
uint32_t name##_clr; \
|
||||
uint32_t name##_tog;
|
||||
|
||||
struct mx28_register_8 {
|
||||
__mx28_reg_8(reg)
|
||||
struct mxs_register_8 {
|
||||
__mxs_reg_8(reg)
|
||||
};
|
||||
|
||||
struct mx28_register_32 {
|
||||
__mx28_reg_32(reg)
|
||||
struct mxs_register_32 {
|
||||
__mxs_reg_32(reg)
|
||||
};
|
||||
|
||||
#define mx28_reg_8(name) \
|
||||
#define mxs_reg_8(name) \
|
||||
union { \
|
||||
struct { __mx28_reg_8(name) }; \
|
||||
struct mx28_register_8 name##_reg; \
|
||||
struct { __mxs_reg_8(name) }; \
|
||||
struct mxs_register_8 name##_reg; \
|
||||
};
|
||||
|
||||
#define mx28_reg_32(name) \
|
||||
#define mxs_reg_32(name) \
|
||||
union { \
|
||||
struct { __mx28_reg_32(name) }; \
|
||||
struct mx28_register_32 name##_reg; \
|
||||
struct { __mxs_reg_32(name) }; \
|
||||
struct mxs_register_32 name##_reg; \
|
||||
};
|
||||
|
||||
#endif /* __MX28_REGS_COMMON_H__ */
|
||||
#endif /* __MXS_REGS_COMMON_H__ */
|
||||
|
|
|
|||
|
|
@ -26,16 +26,16 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_digctl_regs {
|
||||
mx28_reg_32(hw_digctl_ctrl) /* 0x000 */
|
||||
mx28_reg_32(hw_digctl_status) /* 0x010 */
|
||||
mx28_reg_32(hw_digctl_hclkcount) /* 0x020 */
|
||||
mx28_reg_32(hw_digctl_ramctrl) /* 0x030 */
|
||||
mx28_reg_32(hw_digctl_emi_status) /* 0x040 */
|
||||
mx28_reg_32(hw_digctl_read_margin) /* 0x050 */
|
||||
mxs_reg_32(hw_digctl_ctrl) /* 0x000 */
|
||||
mxs_reg_32(hw_digctl_status) /* 0x010 */
|
||||
mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */
|
||||
mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */
|
||||
mxs_reg_32(hw_digctl_emi_status) /* 0x040 */
|
||||
mxs_reg_32(hw_digctl_read_margin) /* 0x050 */
|
||||
uint32_t hw_digctl_writeonce; /* 0x060 */
|
||||
uint32_t reserved_writeonce[3];
|
||||
mx28_reg_32(hw_digctl_bist_ctl) /* 0x070 */
|
||||
mx28_reg_32(hw_digctl_bist_status) /* 0x080 */
|
||||
mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */
|
||||
mxs_reg_32(hw_digctl_bist_status) /* 0x080 */
|
||||
uint32_t hw_digctl_entropy; /* 0x090 */
|
||||
uint32_t reserved_entropy[3];
|
||||
uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
|
||||
|
|
@ -43,7 +43,7 @@ struct mx28_digctl_regs {
|
|||
|
||||
uint32_t reserved1[4];
|
||||
|
||||
mx28_reg_32(hw_digctl_microseconds) /* 0x0c0 */
|
||||
mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */
|
||||
uint32_t hw_digctl_dbgrd; /* 0x0d0 */
|
||||
uint32_t reserved_hw_digctl_dbgrd[3];
|
||||
uint32_t hw_digctl_dbg; /* 0x0e0 */
|
||||
|
|
@ -51,21 +51,21 @@ struct mx28_digctl_regs {
|
|||
|
||||
uint32_t reserved2[4];
|
||||
|
||||
mx28_reg_32(hw_digctl_usb_loopback) /* 0x100 */
|
||||
mx28_reg_32(hw_digctl_ocram_status0) /* 0x110 */
|
||||
mx28_reg_32(hw_digctl_ocram_status1) /* 0x120 */
|
||||
mx28_reg_32(hw_digctl_ocram_status2) /* 0x130 */
|
||||
mx28_reg_32(hw_digctl_ocram_status3) /* 0x140 */
|
||||
mx28_reg_32(hw_digctl_ocram_status4) /* 0x150 */
|
||||
mx28_reg_32(hw_digctl_ocram_status5) /* 0x160 */
|
||||
mx28_reg_32(hw_digctl_ocram_status6) /* 0x170 */
|
||||
mx28_reg_32(hw_digctl_ocram_status7) /* 0x180 */
|
||||
mx28_reg_32(hw_digctl_ocram_status8) /* 0x190 */
|
||||
mx28_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
|
||||
mx28_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
|
||||
mx28_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
|
||||
mx28_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
|
||||
mx28_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
|
||||
mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */
|
||||
mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */
|
||||
mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */
|
||||
mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */
|
||||
mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */
|
||||
mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */
|
||||
mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */
|
||||
mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */
|
||||
mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */
|
||||
mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */
|
||||
mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */
|
||||
mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */
|
||||
mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */
|
||||
mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */
|
||||
mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */
|
||||
|
||||
uint32_t reserved3[36];
|
||||
|
||||
|
|
@ -75,7 +75,7 @@ struct mx28_digctl_regs {
|
|||
uint32_t reserved_hw_digctl_scratch1[3];
|
||||
uint32_t hw_digctl_armcache; /* 0x2a0 */
|
||||
uint32_t reserved_hw_digctl_armcache[3];
|
||||
mx28_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
|
||||
mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */
|
||||
uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */
|
||||
uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3];
|
||||
uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */
|
||||
|
|
|
|||
|
|
@ -30,22 +30,22 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_gpmi_regs {
|
||||
mx28_reg_32(hw_gpmi_ctrl0)
|
||||
mx28_reg_32(hw_gpmi_compare)
|
||||
mx28_reg_32(hw_gpmi_eccctrl)
|
||||
mx28_reg_32(hw_gpmi_ecccount)
|
||||
mx28_reg_32(hw_gpmi_payload)
|
||||
mx28_reg_32(hw_gpmi_auxiliary)
|
||||
mx28_reg_32(hw_gpmi_ctrl1)
|
||||
mx28_reg_32(hw_gpmi_timing0)
|
||||
mx28_reg_32(hw_gpmi_timing1)
|
||||
mxs_reg_32(hw_gpmi_ctrl0)
|
||||
mxs_reg_32(hw_gpmi_compare)
|
||||
mxs_reg_32(hw_gpmi_eccctrl)
|
||||
mxs_reg_32(hw_gpmi_ecccount)
|
||||
mxs_reg_32(hw_gpmi_payload)
|
||||
mxs_reg_32(hw_gpmi_auxiliary)
|
||||
mxs_reg_32(hw_gpmi_ctrl1)
|
||||
mxs_reg_32(hw_gpmi_timing0)
|
||||
mxs_reg_32(hw_gpmi_timing1)
|
||||
|
||||
uint32_t reserved[4];
|
||||
|
||||
mx28_reg_32(hw_gpmi_data)
|
||||
mx28_reg_32(hw_gpmi_stat)
|
||||
mx28_reg_32(hw_gpmi_debug)
|
||||
mx28_reg_32(hw_gpmi_version)
|
||||
mxs_reg_32(hw_gpmi_data)
|
||||
mxs_reg_32(hw_gpmi_stat)
|
||||
mxs_reg_32(hw_gpmi_debug)
|
||||
mxs_reg_32(hw_gpmi_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -27,20 +27,20 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_i2c_regs {
|
||||
mx28_reg_32(hw_i2c_ctrl0)
|
||||
mx28_reg_32(hw_i2c_timing0)
|
||||
mx28_reg_32(hw_i2c_timing1)
|
||||
mx28_reg_32(hw_i2c_timing2)
|
||||
mx28_reg_32(hw_i2c_ctrl1)
|
||||
mx28_reg_32(hw_i2c_stat)
|
||||
mx28_reg_32(hw_i2c_queuectrl)
|
||||
mx28_reg_32(hw_i2c_queuestat)
|
||||
mx28_reg_32(hw_i2c_queuecmd)
|
||||
mx28_reg_32(hw_i2c_queuedata)
|
||||
mx28_reg_32(hw_i2c_data)
|
||||
mx28_reg_32(hw_i2c_debug0)
|
||||
mx28_reg_32(hw_i2c_debug1)
|
||||
mx28_reg_32(hw_i2c_version)
|
||||
mxs_reg_32(hw_i2c_ctrl0)
|
||||
mxs_reg_32(hw_i2c_timing0)
|
||||
mxs_reg_32(hw_i2c_timing1)
|
||||
mxs_reg_32(hw_i2c_timing2)
|
||||
mxs_reg_32(hw_i2c_ctrl1)
|
||||
mxs_reg_32(hw_i2c_stat)
|
||||
mxs_reg_32(hw_i2c_queuectrl)
|
||||
mxs_reg_32(hw_i2c_queuestat)
|
||||
mxs_reg_32(hw_i2c_queuecmd)
|
||||
mxs_reg_32(hw_i2c_queuedata)
|
||||
mxs_reg_32(hw_i2c_data)
|
||||
mxs_reg_32(hw_i2c_debug0)
|
||||
mxs_reg_32(hw_i2c_debug1)
|
||||
mxs_reg_32(hw_i2c_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -30,38 +30,38 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_lcdif_regs {
|
||||
mx28_reg_32(hw_lcdif_ctrl) /* 0x00 */
|
||||
mx28_reg_32(hw_lcdif_ctrl1) /* 0x10 */
|
||||
mx28_reg_32(hw_lcdif_ctrl2) /* 0x20 */
|
||||
mx28_reg_32(hw_lcdif_transfer_count) /* 0x30 */
|
||||
mx28_reg_32(hw_lcdif_cur_buf) /* 0x40 */
|
||||
mx28_reg_32(hw_lcdif_next_buf) /* 0x50 */
|
||||
mx28_reg_32(hw_lcdif_timing) /* 0x60 */
|
||||
mx28_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
|
||||
mx28_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
|
||||
mx28_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
|
||||
mx28_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
|
||||
mx28_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
|
||||
mx28_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
|
||||
mx28_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
|
||||
mx28_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
|
||||
mx28_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
|
||||
mx28_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
|
||||
mx28_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
|
||||
mx28_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
|
||||
mx28_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
|
||||
mx28_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
|
||||
mx28_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
|
||||
mx28_reg_32(hw_lcdif_csc_offset) /* 0x160 */
|
||||
mx28_reg_32(hw_lcdif_csc_limit) /* 0x170 */
|
||||
mx28_reg_32(hw_lcdif_data) /* 0x180 */
|
||||
mx28_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
|
||||
mx28_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
|
||||
mx28_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
|
||||
mx28_reg_32(hw_lcdif_version) /* 0x1c0 */
|
||||
mx28_reg_32(hw_lcdif_debug0) /* 0x1d0 */
|
||||
mx28_reg_32(hw_lcdif_debug1) /* 0x1e0 */
|
||||
mx28_reg_32(hw_lcdif_debug2) /* 0x1f0 */
|
||||
mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */
|
||||
mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */
|
||||
mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */
|
||||
mxs_reg_32(hw_lcdif_transfer_count) /* 0x30 */
|
||||
mxs_reg_32(hw_lcdif_cur_buf) /* 0x40 */
|
||||
mxs_reg_32(hw_lcdif_next_buf) /* 0x50 */
|
||||
mxs_reg_32(hw_lcdif_timing) /* 0x60 */
|
||||
mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */
|
||||
mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */
|
||||
mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */
|
||||
mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */
|
||||
mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */
|
||||
mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */
|
||||
mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */
|
||||
mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */
|
||||
mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */
|
||||
mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */
|
||||
mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */
|
||||
mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */
|
||||
mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */
|
||||
mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */
|
||||
mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */
|
||||
mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */
|
||||
mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */
|
||||
mxs_reg_32(hw_lcdif_data) /* 0x180 */
|
||||
mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x190 */
|
||||
mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */
|
||||
mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1b0 */
|
||||
mxs_reg_32(hw_lcdif_version) /* 0x1c0 */
|
||||
mxs_reg_32(hw_lcdif_debug0) /* 0x1d0 */
|
||||
mxs_reg_32(hw_lcdif_debug1) /* 0x1e0 */
|
||||
mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -30,30 +30,30 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_lradc_regs {
|
||||
mx28_reg_32(hw_lradc_ctrl0);
|
||||
mx28_reg_32(hw_lradc_ctrl1);
|
||||
mx28_reg_32(hw_lradc_ctrl2);
|
||||
mx28_reg_32(hw_lradc_ctrl3);
|
||||
mx28_reg_32(hw_lradc_status);
|
||||
mx28_reg_32(hw_lradc_ch0);
|
||||
mx28_reg_32(hw_lradc_ch1);
|
||||
mx28_reg_32(hw_lradc_ch2);
|
||||
mx28_reg_32(hw_lradc_ch3);
|
||||
mx28_reg_32(hw_lradc_ch4);
|
||||
mx28_reg_32(hw_lradc_ch5);
|
||||
mx28_reg_32(hw_lradc_ch6);
|
||||
mx28_reg_32(hw_lradc_ch7);
|
||||
mx28_reg_32(hw_lradc_delay0);
|
||||
mx28_reg_32(hw_lradc_delay1);
|
||||
mx28_reg_32(hw_lradc_delay2);
|
||||
mx28_reg_32(hw_lradc_delay3);
|
||||
mx28_reg_32(hw_lradc_debug0);
|
||||
mx28_reg_32(hw_lradc_debug1);
|
||||
mx28_reg_32(hw_lradc_conversion);
|
||||
mx28_reg_32(hw_lradc_ctrl4);
|
||||
mx28_reg_32(hw_lradc_treshold0);
|
||||
mx28_reg_32(hw_lradc_treshold1);
|
||||
mx28_reg_32(hw_lradc_version);
|
||||
mxs_reg_32(hw_lradc_ctrl0);
|
||||
mxs_reg_32(hw_lradc_ctrl1);
|
||||
mxs_reg_32(hw_lradc_ctrl2);
|
||||
mxs_reg_32(hw_lradc_ctrl3);
|
||||
mxs_reg_32(hw_lradc_status);
|
||||
mxs_reg_32(hw_lradc_ch0);
|
||||
mxs_reg_32(hw_lradc_ch1);
|
||||
mxs_reg_32(hw_lradc_ch2);
|
||||
mxs_reg_32(hw_lradc_ch3);
|
||||
mxs_reg_32(hw_lradc_ch4);
|
||||
mxs_reg_32(hw_lradc_ch5);
|
||||
mxs_reg_32(hw_lradc_ch6);
|
||||
mxs_reg_32(hw_lradc_ch7);
|
||||
mxs_reg_32(hw_lradc_delay0);
|
||||
mxs_reg_32(hw_lradc_delay1);
|
||||
mxs_reg_32(hw_lradc_delay2);
|
||||
mxs_reg_32(hw_lradc_delay3);
|
||||
mxs_reg_32(hw_lradc_debug0);
|
||||
mxs_reg_32(hw_lradc_debug1);
|
||||
mxs_reg_32(hw_lradc_conversion);
|
||||
mxs_reg_32(hw_lradc_ctrl4);
|
||||
mxs_reg_32(hw_lradc_treshold0);
|
||||
mxs_reg_32(hw_lradc_treshold1);
|
||||
mxs_reg_32(hw_lradc_version);
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -30,49 +30,49 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_ocotp_regs {
|
||||
mx28_reg_32(hw_ocotp_ctrl) /* 0x0 */
|
||||
mx28_reg_32(hw_ocotp_data) /* 0x10 */
|
||||
mx28_reg_32(hw_ocotp_cust0) /* 0x20 */
|
||||
mx28_reg_32(hw_ocotp_cust1) /* 0x30 */
|
||||
mx28_reg_32(hw_ocotp_cust2) /* 0x40 */
|
||||
mx28_reg_32(hw_ocotp_cust3) /* 0x50 */
|
||||
mx28_reg_32(hw_ocotp_crypto0) /* 0x60 */
|
||||
mx28_reg_32(hw_ocotp_crypto1) /* 0x70 */
|
||||
mx28_reg_32(hw_ocotp_crypto2) /* 0x80 */
|
||||
mx28_reg_32(hw_ocotp_crypto3) /* 0x90 */
|
||||
mx28_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
|
||||
mx28_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
|
||||
mx28_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
|
||||
mx28_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
|
||||
mx28_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
|
||||
mx28_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
|
||||
mx28_reg_32(hw_ocotp_swcap) /* 0x100 */
|
||||
mx28_reg_32(hw_ocotp_custcap) /* 0x110 */
|
||||
mx28_reg_32(hw_ocotp_lock) /* 0x120 */
|
||||
mx28_reg_32(hw_ocotp_ops0) /* 0x130 */
|
||||
mx28_reg_32(hw_ocotp_ops1) /* 0x140 */
|
||||
mx28_reg_32(hw_ocotp_ops2) /* 0x150 */
|
||||
mx28_reg_32(hw_ocotp_ops3) /* 0x160 */
|
||||
mx28_reg_32(hw_ocotp_un0) /* 0x170 */
|
||||
mx28_reg_32(hw_ocotp_un1) /* 0x180 */
|
||||
mx28_reg_32(hw_ocotp_un2) /* 0x190 */
|
||||
mx28_reg_32(hw_ocotp_rom0) /* 0x1a0 */
|
||||
mx28_reg_32(hw_ocotp_rom1) /* 0x1b0 */
|
||||
mx28_reg_32(hw_ocotp_rom2) /* 0x1c0 */
|
||||
mx28_reg_32(hw_ocotp_rom3) /* 0x1d0 */
|
||||
mx28_reg_32(hw_ocotp_rom4) /* 0x1e0 */
|
||||
mx28_reg_32(hw_ocotp_rom5) /* 0x1f0 */
|
||||
mx28_reg_32(hw_ocotp_rom6) /* 0x200 */
|
||||
mx28_reg_32(hw_ocotp_rom7) /* 0x210 */
|
||||
mx28_reg_32(hw_ocotp_srk0) /* 0x220 */
|
||||
mx28_reg_32(hw_ocotp_srk1) /* 0x230 */
|
||||
mx28_reg_32(hw_ocotp_srk2) /* 0x240 */
|
||||
mx28_reg_32(hw_ocotp_srk3) /* 0x250 */
|
||||
mx28_reg_32(hw_ocotp_srk4) /* 0x260 */
|
||||
mx28_reg_32(hw_ocotp_srk5) /* 0x270 */
|
||||
mx28_reg_32(hw_ocotp_srk6) /* 0x280 */
|
||||
mx28_reg_32(hw_ocotp_srk7) /* 0x290 */
|
||||
mx28_reg_32(hw_ocotp_version) /* 0x2a0 */
|
||||
mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */
|
||||
mxs_reg_32(hw_ocotp_data) /* 0x10 */
|
||||
mxs_reg_32(hw_ocotp_cust0) /* 0x20 */
|
||||
mxs_reg_32(hw_ocotp_cust1) /* 0x30 */
|
||||
mxs_reg_32(hw_ocotp_cust2) /* 0x40 */
|
||||
mxs_reg_32(hw_ocotp_cust3) /* 0x50 */
|
||||
mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */
|
||||
mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */
|
||||
mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */
|
||||
mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */
|
||||
mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */
|
||||
mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */
|
||||
mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */
|
||||
mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */
|
||||
mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */
|
||||
mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */
|
||||
mxs_reg_32(hw_ocotp_swcap) /* 0x100 */
|
||||
mxs_reg_32(hw_ocotp_custcap) /* 0x110 */
|
||||
mxs_reg_32(hw_ocotp_lock) /* 0x120 */
|
||||
mxs_reg_32(hw_ocotp_ops0) /* 0x130 */
|
||||
mxs_reg_32(hw_ocotp_ops1) /* 0x140 */
|
||||
mxs_reg_32(hw_ocotp_ops2) /* 0x150 */
|
||||
mxs_reg_32(hw_ocotp_ops3) /* 0x160 */
|
||||
mxs_reg_32(hw_ocotp_un0) /* 0x170 */
|
||||
mxs_reg_32(hw_ocotp_un1) /* 0x180 */
|
||||
mxs_reg_32(hw_ocotp_un2) /* 0x190 */
|
||||
mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */
|
||||
mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */
|
||||
mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */
|
||||
mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */
|
||||
mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */
|
||||
mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */
|
||||
mxs_reg_32(hw_ocotp_rom6) /* 0x200 */
|
||||
mxs_reg_32(hw_ocotp_rom7) /* 0x210 */
|
||||
mxs_reg_32(hw_ocotp_srk0) /* 0x220 */
|
||||
mxs_reg_32(hw_ocotp_srk1) /* 0x230 */
|
||||
mxs_reg_32(hw_ocotp_srk2) /* 0x240 */
|
||||
mxs_reg_32(hw_ocotp_srk3) /* 0x250 */
|
||||
mxs_reg_32(hw_ocotp_srk4) /* 0x260 */
|
||||
mxs_reg_32(hw_ocotp_srk5) /* 0x270 */
|
||||
mxs_reg_32(hw_ocotp_srk6) /* 0x280 */
|
||||
mxs_reg_32(hw_ocotp_srk7) /* 0x290 */
|
||||
mxs_reg_32(hw_ocotp_version) /* 0x2a0 */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -30,129 +30,129 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_pinctrl_regs {
|
||||
mx28_reg_32(hw_pinctrl_ctrl) /* 0x0 */
|
||||
mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */
|
||||
|
||||
uint32_t reserved1[60];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
|
||||
mx28_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */
|
||||
mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */
|
||||
|
||||
uint32_t reserved2[72];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_drive0) /* 0x300 */
|
||||
mx28_reg_32(hw_pinctrl_drive1) /* 0x310 */
|
||||
mx28_reg_32(hw_pinctrl_drive2) /* 0x320 */
|
||||
mx28_reg_32(hw_pinctrl_drive3) /* 0x330 */
|
||||
mx28_reg_32(hw_pinctrl_drive4) /* 0x340 */
|
||||
mx28_reg_32(hw_pinctrl_drive5) /* 0x350 */
|
||||
mx28_reg_32(hw_pinctrl_drive6) /* 0x360 */
|
||||
mx28_reg_32(hw_pinctrl_drive7) /* 0x370 */
|
||||
mx28_reg_32(hw_pinctrl_drive8) /* 0x380 */
|
||||
mx28_reg_32(hw_pinctrl_drive9) /* 0x390 */
|
||||
mx28_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
|
||||
mx28_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
|
||||
mx28_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
|
||||
mx28_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
|
||||
mx28_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
|
||||
mx28_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
|
||||
mx28_reg_32(hw_pinctrl_drive16) /* 0x400 */
|
||||
mx28_reg_32(hw_pinctrl_drive17) /* 0x410 */
|
||||
mx28_reg_32(hw_pinctrl_drive18) /* 0x420 */
|
||||
mx28_reg_32(hw_pinctrl_drive19) /* 0x430 */
|
||||
mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */
|
||||
mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */
|
||||
mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */
|
||||
mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */
|
||||
mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */
|
||||
mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */
|
||||
mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */
|
||||
mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */
|
||||
mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */
|
||||
mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */
|
||||
mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */
|
||||
mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */
|
||||
mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */
|
||||
mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */
|
||||
mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */
|
||||
mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */
|
||||
mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */
|
||||
mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */
|
||||
mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */
|
||||
mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */
|
||||
|
||||
uint32_t reserved3[112];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_pull0) /* 0x600 */
|
||||
mx28_reg_32(hw_pinctrl_pull1) /* 0x610 */
|
||||
mx28_reg_32(hw_pinctrl_pull2) /* 0x620 */
|
||||
mx28_reg_32(hw_pinctrl_pull3) /* 0x630 */
|
||||
mx28_reg_32(hw_pinctrl_pull4) /* 0x640 */
|
||||
mx28_reg_32(hw_pinctrl_pull5) /* 0x650 */
|
||||
mx28_reg_32(hw_pinctrl_pull6) /* 0x660 */
|
||||
mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */
|
||||
mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */
|
||||
mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */
|
||||
mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */
|
||||
mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */
|
||||
mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */
|
||||
mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */
|
||||
|
||||
uint32_t reserved4[36];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_dout0) /* 0x700 */
|
||||
mx28_reg_32(hw_pinctrl_dout1) /* 0x710 */
|
||||
mx28_reg_32(hw_pinctrl_dout2) /* 0x720 */
|
||||
mx28_reg_32(hw_pinctrl_dout3) /* 0x730 */
|
||||
mx28_reg_32(hw_pinctrl_dout4) /* 0x740 */
|
||||
mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */
|
||||
mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */
|
||||
mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */
|
||||
mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */
|
||||
mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */
|
||||
|
||||
uint32_t reserved5[108];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_din0) /* 0x900 */
|
||||
mx28_reg_32(hw_pinctrl_din1) /* 0x910 */
|
||||
mx28_reg_32(hw_pinctrl_din2) /* 0x920 */
|
||||
mx28_reg_32(hw_pinctrl_din3) /* 0x930 */
|
||||
mx28_reg_32(hw_pinctrl_din4) /* 0x940 */
|
||||
mxs_reg_32(hw_pinctrl_din0) /* 0x900 */
|
||||
mxs_reg_32(hw_pinctrl_din1) /* 0x910 */
|
||||
mxs_reg_32(hw_pinctrl_din2) /* 0x920 */
|
||||
mxs_reg_32(hw_pinctrl_din3) /* 0x930 */
|
||||
mxs_reg_32(hw_pinctrl_din4) /* 0x940 */
|
||||
|
||||
uint32_t reserved6[108];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_doe0) /* 0xb00 */
|
||||
mx28_reg_32(hw_pinctrl_doe1) /* 0xb10 */
|
||||
mx28_reg_32(hw_pinctrl_doe2) /* 0xb20 */
|
||||
mx28_reg_32(hw_pinctrl_doe3) /* 0xb30 */
|
||||
mx28_reg_32(hw_pinctrl_doe4) /* 0xb40 */
|
||||
mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */
|
||||
mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */
|
||||
mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */
|
||||
mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */
|
||||
mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */
|
||||
|
||||
uint32_t reserved7[300];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
|
||||
mx28_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
|
||||
mx28_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
|
||||
mx28_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
|
||||
mx28_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
|
||||
mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */
|
||||
mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */
|
||||
mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */
|
||||
mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */
|
||||
mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */
|
||||
|
||||
uint32_t reserved8[44];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
|
||||
mx28_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
|
||||
mx28_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
|
||||
mx28_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
|
||||
mx28_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
|
||||
mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */
|
||||
mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */
|
||||
mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */
|
||||
mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */
|
||||
mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */
|
||||
|
||||
uint32_t reserved9[44];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
|
||||
mx28_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
|
||||
mx28_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
|
||||
mx28_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
|
||||
mx28_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
|
||||
mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */
|
||||
mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */
|
||||
mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */
|
||||
mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */
|
||||
mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */
|
||||
|
||||
uint32_t reserved10[44];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
|
||||
mx28_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
|
||||
mx28_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
|
||||
mx28_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
|
||||
mx28_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
|
||||
mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */
|
||||
mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */
|
||||
mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */
|
||||
mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */
|
||||
mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */
|
||||
|
||||
uint32_t reserved11[44];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
|
||||
mx28_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
|
||||
mx28_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
|
||||
mx28_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
|
||||
mx28_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
|
||||
mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */
|
||||
mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */
|
||||
mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */
|
||||
mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */
|
||||
mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */
|
||||
|
||||
uint32_t reserved12[380];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
|
||||
mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */
|
||||
|
||||
uint32_t reserved13[76];
|
||||
|
||||
mx28_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
|
||||
mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -26,10 +26,10 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_power_regs {
|
||||
mx28_reg_32(hw_power_ctrl)
|
||||
mx28_reg_32(hw_power_5vctrl)
|
||||
mx28_reg_32(hw_power_minpwr)
|
||||
mx28_reg_32(hw_power_charge)
|
||||
mxs_reg_32(hw_power_ctrl)
|
||||
mxs_reg_32(hw_power_5vctrl)
|
||||
mxs_reg_32(hw_power_minpwr)
|
||||
mxs_reg_32(hw_power_charge)
|
||||
uint32_t hw_power_vdddctrl;
|
||||
uint32_t reserved_vddd[3];
|
||||
uint32_t hw_power_vddactrl;
|
||||
|
|
@ -44,23 +44,23 @@ struct mx28_power_regs {
|
|||
uint32_t reserved_misc[3];
|
||||
uint32_t hw_power_dclimits;
|
||||
uint32_t reserved_dclimits[3];
|
||||
mx28_reg_32(hw_power_loopctrl)
|
||||
mxs_reg_32(hw_power_loopctrl)
|
||||
uint32_t hw_power_sts;
|
||||
uint32_t reserved_sts[3];
|
||||
mx28_reg_32(hw_power_speed)
|
||||
mxs_reg_32(hw_power_speed)
|
||||
uint32_t hw_power_battmonitor;
|
||||
uint32_t reserved_battmonitor[3];
|
||||
|
||||
uint32_t reserved[4];
|
||||
|
||||
mx28_reg_32(hw_power_reset)
|
||||
mx28_reg_32(hw_power_debug)
|
||||
mx28_reg_32(hw_power_thermal)
|
||||
mx28_reg_32(hw_power_usb1ctrl)
|
||||
mx28_reg_32(hw_power_special)
|
||||
mx28_reg_32(hw_power_version)
|
||||
mx28_reg_32(hw_power_anaclkctrl)
|
||||
mx28_reg_32(hw_power_refctrl)
|
||||
mxs_reg_32(hw_power_reset)
|
||||
mxs_reg_32(hw_power_debug)
|
||||
mxs_reg_32(hw_power_thermal)
|
||||
mxs_reg_32(hw_power_usb1ctrl)
|
||||
mxs_reg_32(hw_power_special)
|
||||
mxs_reg_32(hw_power_version)
|
||||
mxs_reg_32(hw_power_anaclkctrl)
|
||||
mxs_reg_32(hw_power_refctrl)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -27,20 +27,20 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_rtc_regs {
|
||||
mx28_reg_32(hw_rtc_ctrl)
|
||||
mx28_reg_32(hw_rtc_stat)
|
||||
mx28_reg_32(hw_rtc_milliseconds)
|
||||
mx28_reg_32(hw_rtc_seconds)
|
||||
mx28_reg_32(hw_rtc_rtc_alarm)
|
||||
mx28_reg_32(hw_rtc_watchdog)
|
||||
mx28_reg_32(hw_rtc_persistent0)
|
||||
mx28_reg_32(hw_rtc_persistent1)
|
||||
mx28_reg_32(hw_rtc_persistent2)
|
||||
mx28_reg_32(hw_rtc_persistent3)
|
||||
mx28_reg_32(hw_rtc_persistent4)
|
||||
mx28_reg_32(hw_rtc_persistent5)
|
||||
mx28_reg_32(hw_rtc_debug)
|
||||
mx28_reg_32(hw_rtc_version)
|
||||
mxs_reg_32(hw_rtc_ctrl)
|
||||
mxs_reg_32(hw_rtc_stat)
|
||||
mxs_reg_32(hw_rtc_milliseconds)
|
||||
mxs_reg_32(hw_rtc_seconds)
|
||||
mxs_reg_32(hw_rtc_rtc_alarm)
|
||||
mxs_reg_32(hw_rtc_watchdog)
|
||||
mxs_reg_32(hw_rtc_persistent0)
|
||||
mxs_reg_32(hw_rtc_persistent1)
|
||||
mxs_reg_32(hw_rtc_persistent2)
|
||||
mxs_reg_32(hw_rtc_persistent3)
|
||||
mxs_reg_32(hw_rtc_persistent4)
|
||||
mxs_reg_32(hw_rtc_persistent5)
|
||||
mxs_reg_32(hw_rtc_debug)
|
||||
mxs_reg_32(hw_rtc_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -29,26 +29,26 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_ssp_regs {
|
||||
mx28_reg_32(hw_ssp_ctrl0)
|
||||
mx28_reg_32(hw_ssp_cmd0)
|
||||
mx28_reg_32(hw_ssp_cmd1)
|
||||
mx28_reg_32(hw_ssp_xfer_size)
|
||||
mx28_reg_32(hw_ssp_block_size)
|
||||
mx28_reg_32(hw_ssp_compref)
|
||||
mx28_reg_32(hw_ssp_compmask)
|
||||
mx28_reg_32(hw_ssp_timing)
|
||||
mx28_reg_32(hw_ssp_ctrl1)
|
||||
mx28_reg_32(hw_ssp_data)
|
||||
mx28_reg_32(hw_ssp_sdresp0)
|
||||
mx28_reg_32(hw_ssp_sdresp1)
|
||||
mx28_reg_32(hw_ssp_sdresp2)
|
||||
mx28_reg_32(hw_ssp_sdresp3)
|
||||
mx28_reg_32(hw_ssp_ddr_ctrl)
|
||||
mx28_reg_32(hw_ssp_dll_ctrl)
|
||||
mx28_reg_32(hw_ssp_status)
|
||||
mx28_reg_32(hw_ssp_dll_sts)
|
||||
mx28_reg_32(hw_ssp_debug)
|
||||
mx28_reg_32(hw_ssp_version)
|
||||
mxs_reg_32(hw_ssp_ctrl0)
|
||||
mxs_reg_32(hw_ssp_cmd0)
|
||||
mxs_reg_32(hw_ssp_cmd1)
|
||||
mxs_reg_32(hw_ssp_xfer_size)
|
||||
mxs_reg_32(hw_ssp_block_size)
|
||||
mxs_reg_32(hw_ssp_compref)
|
||||
mxs_reg_32(hw_ssp_compmask)
|
||||
mxs_reg_32(hw_ssp_timing)
|
||||
mxs_reg_32(hw_ssp_ctrl1)
|
||||
mxs_reg_32(hw_ssp_data)
|
||||
mxs_reg_32(hw_ssp_sdresp0)
|
||||
mxs_reg_32(hw_ssp_sdresp1)
|
||||
mxs_reg_32(hw_ssp_sdresp2)
|
||||
mxs_reg_32(hw_ssp_sdresp3)
|
||||
mxs_reg_32(hw_ssp_ddr_ctrl)
|
||||
mxs_reg_32(hw_ssp_dll_ctrl)
|
||||
mxs_reg_32(hw_ssp_status)
|
||||
mxs_reg_32(hw_ssp_dll_sts)
|
||||
mxs_reg_32(hw_ssp_debug)
|
||||
mxs_reg_32(hw_ssp_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -29,25 +29,25 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mx28_timrot_regs {
|
||||
mx28_reg_32(hw_timrot_rotctrl)
|
||||
mx28_reg_32(hw_timrot_rotcount)
|
||||
mx28_reg_32(hw_timrot_timctrl0)
|
||||
mx28_reg_32(hw_timrot_running_count0)
|
||||
mx28_reg_32(hw_timrot_fixed_count0)
|
||||
mx28_reg_32(hw_timrot_match_count0)
|
||||
mx28_reg_32(hw_timrot_timctrl1)
|
||||
mx28_reg_32(hw_timrot_running_count1)
|
||||
mx28_reg_32(hw_timrot_fixed_count1)
|
||||
mx28_reg_32(hw_timrot_match_count1)
|
||||
mx28_reg_32(hw_timrot_timctrl2)
|
||||
mx28_reg_32(hw_timrot_running_count2)
|
||||
mx28_reg_32(hw_timrot_fixed_count2)
|
||||
mx28_reg_32(hw_timrot_match_count2)
|
||||
mx28_reg_32(hw_timrot_timctrl3)
|
||||
mx28_reg_32(hw_timrot_running_count3)
|
||||
mx28_reg_32(hw_timrot_fixed_count3)
|
||||
mx28_reg_32(hw_timrot_match_count3)
|
||||
mx28_reg_32(hw_timrot_version)
|
||||
mxs_reg_32(hw_timrot_rotctrl)
|
||||
mxs_reg_32(hw_timrot_rotcount)
|
||||
mxs_reg_32(hw_timrot_timctrl0)
|
||||
mxs_reg_32(hw_timrot_running_count0)
|
||||
mxs_reg_32(hw_timrot_fixed_count0)
|
||||
mxs_reg_32(hw_timrot_match_count0)
|
||||
mxs_reg_32(hw_timrot_timctrl1)
|
||||
mxs_reg_32(hw_timrot_running_count1)
|
||||
mxs_reg_32(hw_timrot_fixed_count1)
|
||||
mxs_reg_32(hw_timrot_match_count1)
|
||||
mxs_reg_32(hw_timrot_timctrl2)
|
||||
mxs_reg_32(hw_timrot_running_count2)
|
||||
mxs_reg_32(hw_timrot_fixed_count2)
|
||||
mxs_reg_32(hw_timrot_match_count2)
|
||||
mxs_reg_32(hw_timrot_timctrl3)
|
||||
mxs_reg_32(hw_timrot_running_count3)
|
||||
mxs_reg_32(hw_timrot_fixed_count3)
|
||||
mxs_reg_32(hw_timrot_match_count3)
|
||||
mxs_reg_32(hw_timrot_version)
|
||||
};
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -24,16 +24,16 @@
|
|||
#define __REGS_USBPHY_H__
|
||||
|
||||
struct mx28_usbphy_regs {
|
||||
mx28_reg_32(hw_usbphy_pwd)
|
||||
mx28_reg_32(hw_usbphy_tx)
|
||||
mx28_reg_32(hw_usbphy_rx)
|
||||
mx28_reg_32(hw_usbphy_ctrl)
|
||||
mx28_reg_32(hw_usbphy_status)
|
||||
mx28_reg_32(hw_usbphy_debug)
|
||||
mx28_reg_32(hw_usbphy_debug0_status)
|
||||
mx28_reg_32(hw_usbphy_debug1)
|
||||
mx28_reg_32(hw_usbphy_version)
|
||||
mx28_reg_32(hw_usbphy_ip)
|
||||
mxs_reg_32(hw_usbphy_pwd)
|
||||
mxs_reg_32(hw_usbphy_tx)
|
||||
mxs_reg_32(hw_usbphy_rx)
|
||||
mxs_reg_32(hw_usbphy_ctrl)
|
||||
mxs_reg_32(hw_usbphy_status)
|
||||
mxs_reg_32(hw_usbphy_debug)
|
||||
mxs_reg_32(hw_usbphy_debug0_status)
|
||||
mxs_reg_32(hw_usbphy_debug1)
|
||||
mxs_reg_32(hw_usbphy_version)
|
||||
mxs_reg_32(hw_usbphy_ip)
|
||||
};
|
||||
|
||||
#define USBPHY_PWD_RXPWDRX (1 << 20)
|
||||
|
|
|
|||
|
|
@ -23,11 +23,11 @@
|
|||
#ifndef __MX28_H__
|
||||
#define __MX28_H__
|
||||
|
||||
int mx28_reset_block(struct mx28_register_32 *reg);
|
||||
int mx28_wait_mask_set(struct mx28_register_32 *reg,
|
||||
int mx28_reset_block(struct mxs_register_32 *reg);
|
||||
int mx28_wait_mask_set(struct mxs_register_32 *reg,
|
||||
uint32_t mask,
|
||||
int timeout);
|
||||
int mx28_wait_mask_clr(struct mx28_register_32 *reg,
|
||||
int mx28_wait_mask_clr(struct mxs_register_32 *reg,
|
||||
uint32_t mask,
|
||||
int timeout);
|
||||
|
||||
|
|
|
|||
|
|
@ -73,8 +73,8 @@ int gpio_get_value(unsigned gpio)
|
|||
{
|
||||
uint32_t bank = PAD_BANK(gpio);
|
||||
uint32_t offset = PINCTRL_DIN(bank);
|
||||
struct mx28_register_32 *reg =
|
||||
(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
struct mxs_register_32 *reg =
|
||||
(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
|
||||
return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
|
||||
}
|
||||
|
|
@ -83,8 +83,8 @@ void gpio_set_value(unsigned gpio, int value)
|
|||
{
|
||||
uint32_t bank = PAD_BANK(gpio);
|
||||
uint32_t offset = PINCTRL_DOUT(bank);
|
||||
struct mx28_register_32 *reg =
|
||||
(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
struct mxs_register_32 *reg =
|
||||
(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
|
||||
if (value)
|
||||
writel(1 << PAD_PIN(gpio), ®->reg_set);
|
||||
|
|
@ -96,8 +96,8 @@ int gpio_direction_input(unsigned gpio)
|
|||
{
|
||||
uint32_t bank = PAD_BANK(gpio);
|
||||
uint32_t offset = PINCTRL_DOE(bank);
|
||||
struct mx28_register_32 *reg =
|
||||
(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
struct mxs_register_32 *reg =
|
||||
(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
|
||||
writel(1 << PAD_PIN(gpio), ®->reg_clr);
|
||||
|
||||
|
|
@ -108,8 +108,8 @@ int gpio_direction_output(unsigned gpio, int value)
|
|||
{
|
||||
uint32_t bank = PAD_BANK(gpio);
|
||||
uint32_t offset = PINCTRL_DOE(bank);
|
||||
struct mx28_register_32 *reg =
|
||||
(struct mx28_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
struct mxs_register_32 *reg =
|
||||
(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
|
||||
|
||||
writel(1 << PAD_PIN(gpio), ®->reg_set);
|
||||
|
||||
|
|
|
|||
|
|
@ -75,8 +75,8 @@ int ehci_hcd_init(void)
|
|||
|
||||
int ret;
|
||||
uint32_t usb_base, cap_base;
|
||||
struct mx28_register_32 *digctl_ctrl =
|
||||
(struct mx28_register_32 *)HW_DIGCTL_CTRL;
|
||||
struct mxs_register_32 *digctl_ctrl =
|
||||
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
|
||||
struct mx28_clkctrl_regs *clkctrl_regs =
|
||||
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
|
||||
|
|
@ -119,8 +119,8 @@ int ehci_hcd_stop(void)
|
|||
{
|
||||
int ret;
|
||||
uint32_t tmp;
|
||||
struct mx28_register_32 *digctl_ctrl =
|
||||
(struct mx28_register_32 *)HW_DIGCTL_CTRL;
|
||||
struct mxs_register_32 *digctl_ctrl =
|
||||
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
|
||||
struct mx28_clkctrl_regs *clkctrl_regs =
|
||||
(struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue