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Code cleanup.

This commit is contained in:
Wolfgang Denk 2006-11-30 18:02:20 +01:00 committed by Wolfgang Denk
parent ab07b6c221
commit dd520bf314
30 changed files with 1710 additions and 1281 deletions
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422
CHANGELOG
View File

@ -1,3 +1,9 @@
commit 8d9a8610b8256331132227e9e6585c6bd5742787
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu Nov 30 01:54:07 2006 +0100
Code cleanup. Update CHANGELOG.
commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba
Author: Grant Likely <grant.likely@secretlab.ca>
Date: Wed Nov 29 16:23:42 2006 +0100
@ -52,6 +58,49 @@ Date: Wed Nov 29 12:03:57 2006 +0100
Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a
Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Tue Nov 28 16:17:27 2006 -0600
Make fsl-i2c not conflict with SOFT I2C
Signed-off-by: Timur Tabi <timur@freescale.com>
commit 14198bf768fdc958e3c1afd2404e5262208e98d7
Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Date: Tue Nov 28 16:17:18 2006 -0600
Fix I2C master address initialization.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit cf3d045e51ca8dcc6cf759827140861d6ac25c04
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Tue Nov 28 23:31:19 2006 -0600
Assign maintainers for mpc8349emds and mpc8360emds
Dave for mpc8360emds, and me for mpc8349emds.
commit 1aa934c81b77f2080d3ca4b226eab67b17a33961
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Tue Nov 28 23:28:33 2006 -0600
Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c
give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
since they are passed by reference to ucc_get_cmxucr_reg and assigned.
commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5
Author: Timur Tabi <timur@freescale.com>
Date: Tue Nov 28 12:09:35 2006 -0600
mpc83xx: Miscellaneous code style fixes
Implement various code style fixes and similar changes.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706
Author: Stefan Roese <sr@denx.de>
Date: Tue Nov 28 17:55:49 2006 +0100
@ -268,6 +317,379 @@ Date: Mon Nov 6 17:06:36 2006 +0100
This fixes get_ram_size() problems on MPC5200 Rev. B boards.
commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa
Author: Timur Tabi <timur@freescale.com>
Date: Fri Nov 3 19:15:00 2006 -0600
mpc83xx: Update 83xx to use fsl_i2c.c
Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit d239d74b1c937984bc519083a8e7de373a390f06
Author: Timur Tabi <timur@freescale.com>
Date: Fri Nov 3 12:00:28 2006 -0600
mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit f7fb2e703ec9688541416962724adff70a7322cb
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Thu Nov 2 19:47:11 2006 -0600
mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
commit 90f30a710a3c619b5405860a686c4ddfc495d4b6
Author: Dave Liu <daveliu@freescale.com>
Date: Thu Nov 2 18:05:50 2006 -0600
mpc83xx: Fix the incorrect dcbz operation
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Nov 1 00:10:40 2006 -0600
mpc83xx: add OF_FLAT_TREE bits to 83xx boards
add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
STDOUT_PATH configuration bits to mpc8349emds,
mpc8349itx, and mpc8360emds board code.
redo environment to use bootm with the fdtaddr
for booting ARCH=powerpc kernels by default,
and provide default fdtaddr values.
commit 48041365b3420589ad464ebc7752e0053538b729
Author: Kim Phillips <kim.phillips@freescale.com>
Date: Wed Nov 1 00:07:25 2006 -0600
mpc83xx: change ft code to modify local-mac-address property
Update 83xx OF code to update local-mac-address properties
for ethernet instead of the obsolete 'address' property.
commit 9ca880a250870a7d55754291b5591d2b5fe89b54
Author: Timur Tabi <timur@freescale.com>
Date: Tue Oct 31 21:23:16 2006 -0600
mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS
This patch also adds an improved I2C set_speed(), which handles all clock
frequencies.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit ac4b5622ce050b5ee1e154b98df630d778661632
Author: Dave Liu <daveliu@freescale.com>
Date: Tue Oct 31 19:54:59 2006 -0600
mpc83xx: add the README.mpc8360emds
add doc/README.mpc8360emds to accompany the new board support
commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef
Author: Dave Liu <daveliu@freescale.com>
Date: Fri Nov 3 12:11:15 2006 -0600
mpc83xx: add QE ethernet support
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73
Author: Dave Liu <daveliu@freescale.com>
Date: Fri Nov 3 19:33:44 2006 -0600
mpc83xx: Add MPC8360EMDS basic board support
Add support for the Freescale MPC8360EMDS board.
Includes DDR, DUART, Local Bus, PCI.
commit 23892e49352de74f7fac36ff90bb1be143d195e3
Author: Dave Liu <daveliu@freescale.com>
Date: Tue Oct 31 19:30:40 2006 -0600
mpc83xx: add the QUICC Engine (QE) immap file
common QE immap file. Also required for 8360.
commit b701652a4992bdcc62fb1a6038a85beef9e55da4
Author: Dave Liu <daveliu@freescale.com>
Date: Tue Oct 31 19:25:38 2006 -0600
mpc83xx: Add 8360 specifics to 83xx immap
Mainly add QE device dependencies, with appropriate 8360 protection.
Lindent also run.
commit 988833324a7fda482c8ac3ca23eb539f8232e404
Author: Timur Tabi <timur@freescale.com>
Date: Tue Oct 31 19:14:41 2006 -0600
mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2"
2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2"
CHANGELOG:
* For the 8349E-mITX, fix some size values in pci_init_board(), enable
the clock for the 2nd USB board (Linux kernel will hang otherwise),
and fix the CONFIG_BOOTARGS macro.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357
Author: Timur Tabi <timur@freescale.com>
Date: Tue Oct 31 18:44:42 2006 -0600
mpc83xx: Add support for the MPC8349E-mITX
PREREQUISITE PATCHES:
* This patch can only be applied after the following patches have been applied:
1) DNX#2006090742000024 "Add support for multiple I2C buses"
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
CHANGELOG:
* Add support for the Freescale MPC8349E-mITX reference design platform.
The second TSEC (Vitesse 7385 switch) is not supported at this time.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit 183da6d9b446cc12123455844ad1187e2375626f
Author: Ben Warren <bwarren@qstreams.com>
Date: Tue Sep 12 10:15:53 2006 -0400
Additional MPC8349 support for multibus i2c
Hello,
Here is a patch for a file that was accidentally left out of a previous
attempt.
It accompanies the patch with ticket DNX#2006090742000024
CHANGELOG:
Change PCI initialization to use new multi-bus I2C API.
regards,
Ben
commit b24f119d672b709d153ff2ac091d4aa63ec6877d
Author: Ben Warren <bwarren@qstreams.com>
Date: Thu Sep 7 16:51:04 2006 -0400
Multi-bus I2C implementation of MPC834x
Hello,
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.
/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
CHANGELOG:
Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.
regards,
Ben
commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae
Author: Ben Warren <bwarren@qstreams.com>
Date: Thu Sep 7 16:50:54 2006 -0400
Add support for multiple I2C buses
Hello,
Attached is a patch providing support for multiple I2C buses at the
command level. The second part of the patch includes an implementation
for the MPC834x CPU and MPC8349EMDS board.
/*** Note: This patch replaces ticket DNX#2006083042000018 ***/
Signed-off-by: Ben Warren <bwarren@qstreams.com>
Overview:
1. Include new 'i2c' command (based on USB implementation) using
CONFIG_I2C_CMD_TREE.
2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that
the commands to change bus number and speed are only available under the
new 'i2c' command mentioned in the first bullet.
3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form
of an array of bus-device pairs. Otherwise, it is an array of uchar.
CHANGELOG:
Added new 'i2c' master command for all I2C interaction. This is
conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for
setting I2C bus speed as well as changing the active bus if the board
has more than one (conditionally compiled with
CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses.
Updated README.
regards,
Ben
commit bed85caf872714ebf53013967a695c9d63acfc68
Author: Timur Tabi <timur@freescale.com>
Date: Tue Oct 31 18:13:36 2006 -0600
mpc83xx: Add support for Errata DDR6 on MPC 834x systems
CHANGELOG:
* Errata DDR6, which affects all current MPC 834x processors, lists changes
required to maintain compatibility with various types of DDR memory. This
patch implements those changes.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit afd6e470f639883002c7c59d562690a5cb0f4865
Author: Timur Tabi <timur@freescale.com>
Date: Wed Oct 25 18:45:23 2006 -0500
mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it
commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a
Author: Timur Tabi <timur@freescale.com>
Date: Tue Aug 22 17:07:00 2006 -0500
mpc83xx: Add support for variable flash memory sizes on 83xx systems
CHANGELOG:
* On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
window registers, instead of using a hard-coded value of 8MB.
Signed-off-by: Timur Tabi <timur@freescale.com>
commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965
Author: Tanya Jiang <tanya.jiang@freescale.com>
Date: Thu Aug 3 18:38:13 2006 +0800
mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros
Unified TQM834x variable names with 83xx and consolidated macro
in preparation for the 8360 and other upcoming 83xx devices.
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
commit f6eda7f80ccc13d658020268c507d7173cf2e8aa
Author: Dave Liu <daveliu@freescale.com>
Date: Wed Oct 25 14:41:21 2006 -0500
mpc83xx: Changed to unified mpx83xx names and added common 83xx changes
Incorporated the common unified variable names and the changes in preparation
for releasing mpc8360 patches.
Signed-off-by: Dave Liu <daveliu@freescale.com>
commit 3894c46c27c64891f93ac04edde86a9fa9758d92
Author: Tanya Jiang <tanya.jiang@freescale.com>
Date: Thu Aug 3 18:36:02 2006 +0800
mpc83xx: Fix missing build for mpc8349emds pci.c
Make pci build for mpc8349emds
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219
Author: Tanya Jiang <tanya.jiang@freescale.com>
Date: Thu Aug 3 18:39:49 2006 +0800
mpc83xx: Removed unused file resetvec.S for mpc83xx cpu
Removed unused file resetvec.S for mpc83xx cpu
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf
Author: Nick Spence <Nick.Spence@freescale.com>
Date: Sat Sep 30 00:32:59 2006 -0700
NAND Flash verify across block boundaries
This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is
defined
and the write crosses a block boundary. The pointer to the verification
buffer (bufstart) is not being updated to reflect the starting of the
new
block so the verification of the second block fails.
CHANGELOG:
* Fix NAND FLASH page verification across block boundaries
commit f484dc791a3932537213c43c654cc1295c64b84c
Author: Nick Spence <nick.spence@freescale.com>
Date: Thu Sep 7 07:39:46 2006 -0700
Added RGMII support to the TSECs and Marvell 881111 Phy
Added a phy initialization to adjust the RGMII RX and TX timing
Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode
Signed-off-by: Nick Spence <nick.spence@freescale.com>
commit c59200443072353044aa4bf737a5a60f9a9af231
Author: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu Nov 2 15:15:01 2006 +0100

30
Makefile
View File

@ -93,7 +93,7 @@ MKCONFIG := $(SRCTREE)/mkconfig
export MKCONFIG
ifneq ($(OBJTREE),$(SRCTREE))
REMOTE_BUILD := 1
REMOTE_BUILD := 1
export REMOTE_BUILD
endif
@ -378,8 +378,8 @@ Lite5200_LOWBOOT08_config \
icecube_5200_config \
icecube_5200_LOWBOOT_config \
icecube_5200_LOWBOOT08_config \
icecube_5200_DDR_config \
icecube_5200_DDR_LOWBOOT_config \
icecube_5200_DDR_config \
icecube_5200_DDR_LOWBOOT_config \
icecube_5200_DDR_LOWBOOT08_config \
icecube_5100_config: unconfig
@mkdir -p $(obj)include
@ -458,7 +458,7 @@ prs200_highboot_DDR_config: unconfig
@[ -n "$(findstring _SDRAM,$@)" ] || \
{ if [ -n "$(findstring mcc200,$@)" ]; \
then \
echo "... with DDR" ; \
echo "... with DDR" ; \
else \
if [ -n "$(findstring _DDR,$@)" ];\
then \
@ -865,9 +865,9 @@ RPXClassic_config: unconfig
RPXlite_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc8xx RPXlite
RPXlite_DW_64_config \
RPXlite_DW_LCD_config \
RPXlite_DW_64_LCD_config \
RPXlite_DW_64_config \
RPXlite_DW_LCD_config \
RPXlite_DW_64_LCD_config \
RPXlite_DW_NVRAM_config \
RPXlite_DW_NVRAM_64_config \
RPXlite_DW_NVRAM_LCD_config \
@ -880,12 +880,12 @@ RPXlite_DW_config: unconfig
echo "... with 64MHz system clock ..."; \
}
@[ -z "$(findstring _LCD,$@)" ] || \
{ echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
{ echo "#define CONFIG_LCD" >>$(obj)include/config.h ; \
echo "#define CONFIG_NEC_NL6448BC20" >>$(obj)include/config.h ; \
echo "... with LCD display ..."; \
}
@[ -z "$(findstring _NVRAM,$@)" ] || \
{ echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \
{ echo "#define CFG_ENV_IS_IN_NVRAM" >>$(obj)include/config.h ; \
echo "... with ENV in NVRAM ..."; \
}
@$(MKCONFIG) -a RPXlite_DW ppc mpc8xx RPXlite_dw
@ -1821,7 +1821,7 @@ ap966_config \
ap922_config \
ap922_XA10_config \
ap7_config \
ap720t_config \
ap720t_config \
ap920t_config \
ap926ejs_config \
ap946es_config: unconfig
@ -1978,7 +1978,7 @@ cm4008_config : unconfig
cm41xx_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cm41xx NULL ks8695
gth2_config : unconfig
gth2_config : unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@echo "#define CONFIG_GTH2 1" >>$(obj)include/config.h
@ -2124,19 +2124,19 @@ tb0229_config: unconfig
#########################################################################
## MIPS32 AU1X00
#########################################################################
dbau1000_config : unconfig
dbau1000_config : unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@echo "#define CONFIG_DBAU1000 1" >>$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1100_config : unconfig
dbau1100_config : unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@echo "#define CONFIG_DBAU1100 1" >>$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
dbau1500_config : unconfig
dbau1500_config : unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@echo "#define CONFIG_DBAU1500 1" >>$(obj)include/config.h
@ -2154,7 +2154,7 @@ dbau1550_el_config : unconfig
@echo "#define CONFIG_DBAU1550 1" >>$(obj)include/config.h
@$(MKCONFIG) -a dbau1x00 mips mips dbau1x00
pb1000_config : unconfig
pb1000_config : unconfig
@mkdir -p $(obj)include
@ >$(obj)include/config.h
@echo "#define CONFIG_PB1000 1" >>$(obj)include/config.h

10
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
View File

@ -50,13 +50,13 @@ long int initdram (int board_type)
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_16);
MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M
| MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *)(CFG_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
@ -70,10 +70,10 @@ long int initdram (int board_type)
#ifdef CFG_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_16;
MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M
MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M
| MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
@ -82,7 +82,7 @@ long int initdram (int board_type)
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i=0; i < 2000; i++)
asm(" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *)(CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE1 * 1024 * 1024;
#endif

2
board/BuS/EB+MCF-EV123/VCxK.c
View File

@ -66,7 +66,7 @@ int init_vcxk(void)
return 1;
}
void vcxk_loadimage(ulong source)
void vcxk_loadimage(ulong source)
{
int cnt;
vcxk_acknowledge_wait();

16
board/BuS/EB+MCF-EV123/VCxK.h
View File

@ -25,24 +25,24 @@
#define __VCXK_H_
extern int init_vcxk(void);
void vcxk_loadimage(ulong source);
void vcxk_loadimage(ulong source);
#define VIDEO_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
#define VIDEO_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
#define VIDEO_ACKNOWLEDGE_PIN 0x0001
#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT
#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR
#define VIDEO_ENABLE_PORT MCFGPTB_GPTPORT
#define VIDEO_ENABLE_DDR MCFGPTB_GPTDDR
#define VIDEO_ENABLE_PIN 0x0002
#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT
#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR
#define VIDEO_REQUEST_PORT MCFGPTB_GPTPORT
#define VIDEO_REQUEST_DDR MCFGPTB_GPTDDR
#define VIDEO_REQUEST_PIN 0x0004
#define VIDEO_Invert_CFG MCFGPIO_PEPAR
#define VIDEO_Invert_IO MCFGPIO_PEPAR_PEPA2
#define VIDEO_INVERT_PORT MCFGPIO_PORTE
#define VIDEO_INVERT_DDR MCFGPIO_DDRE
#define VIDEO_INVERT_PORT MCFGPIO_PORTE
#define VIDEO_INVERT_DDR MCFGPIO_DDRE
#define VIDEO_INVERT_PIN MCFGPIO_PORT2
#endif

2
board/BuS/EB+MCF-EV123/cfm_flash.c
View File

@ -60,7 +60,7 @@ void cfm_flash_init (flash_info_t * info)
MCFCFM_MCR = 0;
MCFCFM_CLKD = CFM_CLK;
debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CFG_CLK);
MCFCFM_SACC = 0;
MCFCFM_DACC = 0;

2
board/BuS/EB+MCF-EV123/flash.c
View File

@ -256,7 +256,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
enable_interrupts ();
if (cflag)
icache_enable ();
icache_enable ();
return rc;
}

8
board/BuS/EB+MCF-EV123/u-boot.lds
View File

@ -34,11 +34,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/LEOX/elpt860/u-boot.lds
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

8
board/LEOX/elpt860/u-boot.lds.debug
View File

@ -43,11 +43,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }

2
board/MAI/AmigaOneG3SE/Makefile
View File

@ -30,7 +30,7 @@ endif
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
via686.o i8259.o ../bios_emulator/x86interface.o \
via686.o i8259.o ../bios_emulator/x86interface.o \
../bios_emulator/bios.o ../bios_emulator/glue.o \
interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \
../menu/cmd_menu.o cmd_boota.o nvram.o

10
board/MAI/AmigaOneG3SE/articiaS_pci.c
View File

@ -368,11 +368,11 @@ void articiaS_pci_init (void)
if (articiaS_init_vga() == -1)
{
/* If the VGA didn't init and we have stdout set to VGA, reset to serial */
/* s = getenv("stdout"); */
/* if (s && strcmp(s, "vga") == 0) */
/* { */
/* setenv("stdout", "serial"); */
/* } */
/* s = getenv("stdout"); */
/* if (s && strcmp(s, "vga") == 0) */
/* { */
/* setenv("stdout", "serial"); */
/* } */
}
}
pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);

148
board/MAI/AmigaOneG3SE/enet.c
View File

@ -41,57 +41,57 @@
/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
#define TotalReset (0<<11)
#define SelectWindow (1<<11)
#define StartCoax (2<<11)
#define RxDisable (3<<11)
#define RxEnable (4<<11)
#define RxReset (5<<11)
#define UpStall (6<<11)
#define UpUnstall (6<<11)+1
#define DownStall (6<<11)+2
#define DownUnstall (6<<11)+3
#define RxDiscard (8<<11)
#define TxEnable (9<<11)
#define TxDisable (10<<11)
#define TxReset (11<<11)
#define FakeIntr (12<<11)
#define AckIntr (13<<11)
#define SetIntrEnb (14<<11)
#define SetStatusEnb (15<<11)
#define SetRxFilter (16<<11)
#define SetRxThreshold (17<<11)
#define SetTxThreshold (18<<11)
#define SetTxStart (19<<11)
#define StartDMAUp (20<<11)
#define StartDMADown (20<<11)+1
#define TotalReset (0<<11)
#define SelectWindow (1<<11)
#define StartCoax (2<<11)
#define RxDisable (3<<11)
#define RxEnable (4<<11)
#define RxReset (5<<11)
#define UpStall (6<<11)
#define UpUnstall (6<<11)+1
#define DownStall (6<<11)+2
#define DownUnstall (6<<11)+3
#define RxDiscard (8<<11)
#define TxEnable (9<<11)
#define TxDisable (10<<11)
#define TxReset (11<<11)
#define FakeIntr (12<<11)
#define AckIntr (13<<11)
#define SetIntrEnb (14<<11)
#define SetStatusEnb (15<<11)
#define SetRxFilter (16<<11)
#define SetRxThreshold (17<<11)
#define SetTxThreshold (18<<11)
#define SetTxStart (19<<11)
#define StartDMAUp (20<<11)
#define StartDMADown (20<<11)+1
#define StatsEnable (21<<11)
#define StatsDisable (22<<11)
#define StopCoax (23<<11)
#define SetFilterBit (25<<11)
#define StopCoax (23<<11)
#define SetFilterBit (25<<11)
/* The SetRxFilter command accepts the following classes */
#define RxStation 1
#define RxStation 1
#define RxMulticast 2
#define RxBroadcast 4
#define RxProm 8
#define RxProm 8
/* 3Com status word defnitions */
#define IntLatch 0x0001
#define HostError 0x0002
#define TxComplete 0x0004
#define TxAvailable 0x0008
#define RxComplete 0x0010
#define RxEarly 0x0020
#define IntReq 0x0040
#define StatsFull 0x0080
#define DMADone (1<<8)
#define DownComplete (1<<9)
#define UpComplete (1<<10)
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
#define IntLatch 0x0001
#define HostError 0x0002
#define TxComplete 0x0004
#define TxAvailable 0x0008
#define RxComplete 0x0010
#define RxEarly 0x0020
#define IntReq 0x0040
#define StatsFull 0x0080
#define DMADone (1<<8)
#define DownComplete (1<<9)
#define UpComplete (1<<10)
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
/* Polling Registers */
@ -100,17 +100,17 @@
/* Register window 0 offets */
#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
#define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
#define Wn0EepromData 12 /* Window 0: EEPROM results register. */
#define IntrStatus 0x0E /* Valid in all windows. */
/* Register window 0 EEPROM bits */
#define EEPROM_Read 0x80
#define EEPROM_WRITE 0x40
#define EEPROM_ERASE 0xC0
#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
#define EEPROM_Read 0x80
#define EEPROM_WRITE 0x40
#define EEPROM_ERASE 0xC0
#define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
#define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
/* EEPROM locations. */
@ -129,13 +129,13 @@
/* Register window 1 offsets, the window used in normal operation */
#define TX_FIFO 0x10
#define RX_FIFO 0x10
#define RxErrors 0x14
#define RxStatus 0x18
#define TX_FIFO 0x10
#define RX_FIFOa 0x10
#define RxErrors 0x14
#define RxStatus 0x18
#define Timer 0x1A
#define TxStatus 0x1B
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
#define TxStatus 0x1B
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
/* Register Window 2 */
@ -147,47 +147,47 @@
#define Wn3_MAC_Ctrl 6
#define Wn3_Options 8
#define BFEXT(value, offset, bitcount) \
#define BFEXT(value, offset, bitcount) \
((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
#define BFINS(lhs, rhs, offset, bitcount) \
(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
(((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
(((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
#define RAM_SIZE(v) BFEXT(v, 0, 3)
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
#define RAM_SPEED(v) BFEXT(v, 4, 2)
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
#define RAM_SPEED(v) BFEXT(v, 4, 2)
#define ROM_SIZE(v) BFEXT(v, 6, 2)
#define RAM_SPLIT(v) BFEXT(v, 16, 2)
#define RAM_SPLIT(v) BFEXT(v, 16, 2)
#define XCVR(v) BFEXT(v, 20, 4)
#define AUTOSELECT(v) BFEXT(v, 24, 1)
#define AUTOSELECT(v) BFEXT(v, 24, 1)
/* Register Window 4: Xcvr/media bits */
#define Wn4_FIFODiag 4
#define Wn4_NetDiag 6
#define Wn4_FIFODiag 4
#define Wn4_NetDiag 6
#define Wn4_PhysicalMgmt 8
#define Wn4_Media 10
#define Wn4_Media 10
#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */
#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */
#define Media_LnkBeat 0x0800
#define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */
#define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
#define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */
#define Media_LnkBeat 0x0800
/* Register Window 7: Bus Master control */
#define Wn7_MasterAddr 0
#define Wn7_MasterLen 6
#define Wn7_MasterStatus 12
#define Wn7_MasterAddr 0
#define Wn7_MasterLen 6
#define Wn7_MasterStatus 12
/* Boomerang bus master control registers. */
#define PktStatus 0x20
#define PktStatus 0x20
#define DownListPtr 0x24
#define FragAddr 0x28
#define FragLen 0x2c
#define FragAddr 0x28
#define FragLen 0x2c
#define TxFreeThreshold 0x2f
#define UpPktStatus 0x30
#define UpPktStatus 0x30
#define UpListPtr 0x38
/* The Rx and Tx descriptor lists. */

2
board/emk/top5200/top5200.c
View File

@ -190,7 +190,7 @@ void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
}

3
board/esd/cpci5200/cpci5200.c
View File

@ -191,8 +191,7 @@ static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void
) {
void pci_init_board(void) {
pci_mpc5xxx_init(&hose);
}
#endif

3
board/esd/pf5200/pf5200.c
View File

@ -191,8 +191,7 @@ static struct pci_controller hose;
extern void pci_mpc5xxx_init(struct pci_controller *);
void pci_init_board(void
) {
void pci_init_board(void) {
pci_mpc5xxx_init(&hose);
}
#endif

2
board/icecube/icecube.c
View File

@ -316,7 +316,7 @@ void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
/* Deassert reset */

2
board/mpc8349emds/pci.c
View File

@ -74,7 +74,7 @@ pib_init(void)
*/
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
i2c_set_bus_num(1);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);

316
common/cmd_nand.c
View File

@ -684,178 +684,182 @@ extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
size_t len, size_t *retlen, const u_char *buf);
int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int rcode = 0;
int rcode = 0;
switch (argc) {
case 0:
case 1:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strcmp(argv[1],"info") == 0) {
int i;
switch (argc) {
case 0:
case 1:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strcmp (argv[1], "info") == 0) {
int i;
putc ('\n');
putc ('\n');
for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
continue; /* list only known devices */
printf ("Device %d: ", i);
nand_print(&nand_dev_desc[i]);
}
return 0;
} else if (strcmp(argv[1],"device") == 0) {
if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
puts ("\nno devices available\n");
return 1;
}
printf ("\nDevice %d: ", curr_device);
nand_print(&nand_dev_desc[curr_device]);
return 0;
} else if (strcmp(argv[1],"bad") == 0) {
if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
puts ("\nno devices available\n");
return 1;
}
printf ("\nDevice %d bad blocks:\n", curr_device);
nand_print_bad(&nand_dev_desc[curr_device]);
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 3:
if (strcmp(argv[1],"device") == 0) {
int dev = (int)simple_strtoul(argv[2], NULL, 10);
printf ("\nDevice %d: ", dev);
if (dev >= CFG_MAX_NAND_DEVICE) {
puts ("unknown device\n");
return 1;
}
nand_print(&nand_dev_desc[dev]);
/*nand_print (dev);*/
if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
return 1;
}
curr_device = dev;
puts ("... is now current device\n");
return 0;
}
else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
struct nand_chip* nand = &nand_dev_desc[curr_device];
ulong off = 0;
ulong size = nand->totlen;
int ret;
printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
curr_device, off, size);
ret = nand_legacy_erase (nand, off, size, 1);
printf("%s\n", ret ? "ERROR" : "OK");
return ret;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
default:
/* at least 4 args */
if (strncmp(argv[1], "read", 4) == 0 ||
strncmp(argv[1], "write", 5) == 0) {
ulong addr = simple_strtoul(argv[2], NULL, 16);
ulong off = simple_strtoul(argv[3], NULL, 16);
ulong size = simple_strtoul(argv[4], NULL, 16);
int cmd = (strncmp(argv[1], "read", 4) == 0) ?
NANDRW_READ : NANDRW_WRITE;
int ret, total;
char* cmdtail = strchr(argv[1], '.');
if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
/* read out-of-band data */
if (cmd & NANDRW_READ) {
ret = nand_read_oob(nand_dev_desc + curr_device,
off, size, (size_t *)&total,
(u_char*)addr);
for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) {
if (nand_dev_desc[i].ChipID ==
NAND_ChipID_UNKNOWN)
continue; /* list only known devices */
printf ("Device %d: ", i);
nand_print (&nand_dev_desc[i]);
}
else {
ret = nand_write_oob(nand_dev_desc + curr_device,
off, size, (size_t *)&total,
(u_char*)addr);
return 0;
} else if (strcmp (argv[1], "device") == 0) {
if ((curr_device < 0)
|| (curr_device >= CFG_MAX_NAND_DEVICE)) {
puts ("\nno devices available\n");
return 1;
}
printf ("\nDevice %d: ", curr_device);
nand_print (&nand_dev_desc[curr_device]);
return 0;
} else if (strcmp (argv[1], "bad") == 0) {
if ((curr_device < 0)
|| (curr_device >= CFG_MAX_NAND_DEVICE)) {
puts ("\nno devices available\n");
return 1;
}
printf ("\nDevice %d bad blocks:\n", curr_device);
nand_print_bad (&nand_dev_desc[curr_device]);
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 3:
if (strcmp (argv[1], "device") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
printf ("\nDevice %d: ", dev);
if (dev >= CFG_MAX_NAND_DEVICE) {
puts ("unknown device\n");
return 1;
}
nand_print (&nand_dev_desc[dev]);
/*nand_print (dev); */
if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
return 1;
}
curr_device = dev;
puts ("... is now current device\n");
return 0;
} else if (strcmp (argv[1], "erase") == 0
&& strcmp (argv[2], "clean") == 0) {
struct nand_chip *nand = &nand_dev_desc[curr_device];
ulong off = 0;
ulong size = nand->totlen;
int ret;
printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size);
ret = nand_legacy_erase (nand, off, size, 1);
printf ("%s\n", ret ? "ERROR" : "OK");
return ret;
}
else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
cmd |= NANDRW_JFFS2; /* skip bad blocks */
else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
if (cmd & NANDRW_READ)
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
default:
/* at least 4 args */
if (strncmp (argv[1], "read", 4) == 0 ||
strncmp (argv[1], "write", 5) == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong off = simple_strtoul (argv[3], NULL, 16);
ulong size = simple_strtoul (argv[4], NULL, 16);
int cmd = (strncmp (argv[1], "read", 4) == 0) ?
NANDRW_READ : NANDRW_WRITE;
int ret, total;
char *cmdtail = strchr (argv[1], '.');
if (cmdtail && !strncmp (cmdtail, ".oob", 2)) {
/* read out-of-band data */
if (cmd & NANDRW_READ) {
ret = nand_read_oob (nand_dev_desc + curr_device,
off, size, (size_t *) & total,
(u_char *) addr);
} else {
ret = nand_write_oob (nand_dev_desc + curr_device,
off, size, (size_t *) & total,
(u_char *) addr);
}
return ret;
} else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2))
cmd |= NANDRW_JFFS2; /* skip bad blocks */
else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) {
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
if (cmd & NANDRW_READ)
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
}
#ifdef SXNI855T
/* need ".e" same as ".j" for compatibility with older units */
else if (cmdtail && !strcmp(cmdtail, ".e"))
cmd |= NANDRW_JFFS2; /* skip bad blocks */
/* need ".e" same as ".j" for compatibility with older units */
else if (cmdtail && !strcmp (cmdtail, ".e"))
cmd |= NANDRW_JFFS2; /* skip bad blocks */
#endif
#ifdef CFG_NAND_SKIP_BAD_DOT_I
/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
/* ".i" for image -> read skips bad block (no 0xff) */
else if (cmdtail && !strcmp(cmdtail, ".i")) {
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
if (cmd & NANDRW_READ)
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
}
/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
/* ".i" for image -> read skips bad block (no 0xff) */
else if (cmdtail && !strcmp (cmdtail, ".i")) {
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
if (cmd & NANDRW_READ)
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
}
#endif /* CFG_NAND_SKIP_BAD_DOT_I */
else if (cmdtail) {
else if (cmdtail) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
(cmd & NANDRW_READ) ? "read" : "write",
curr_device, off, size);
ret = nand_legacy_rw (nand_dev_desc + curr_device,
cmd, off, size,
(size_t *) & total,
(u_char *) addr);
printf (" %d bytes %s: %s\n", total,
(cmd & NANDRW_READ) ? "read" : "written",
ret ? "ERROR" : "OK");
return ret;
} else if (strcmp (argv[1], "erase") == 0 &&
(argc == 4 || strcmp ("clean", argv[2]) == 0)) {
int clean = argc == 5;
ulong off =
simple_strtoul (argv[2 + clean], NULL, 16);
ulong size =
simple_strtoul (argv[3 + clean], NULL, 16);
int ret;
printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
curr_device, off, size);
ret = nand_legacy_erase (nand_dev_desc + curr_device,
off, size, clean);
printf ("%s\n", ret ? "ERROR" : "OK");
return ret;
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
rcode = 1;
}
printf ("\nNAND %s: device %d offset %ld, size %ld ...\n",
(cmd & NANDRW_READ) ? "read" : "write",
curr_device, off, size);
ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
(size_t *)&total, (u_char*)addr);
printf (" %d bytes %s: %s\n", total,
(cmd & NANDRW_READ) ? "read" : "written",
ret ? "ERROR" : "OK");
return ret;
} else if (strcmp(argv[1],"erase") == 0 &&
(argc == 4 || strcmp("clean", argv[2]) == 0)) {
int clean = argc == 5;
ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
int ret;
printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
curr_device, off, size);
ret = nand_legacy_erase (nand_dev_desc + curr_device,
off, size, clean);
printf("%s\n", ret ? "ERROR" : "OK");
return ret;
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
return rcode;
}
return rcode;
}
}
U_BOOT_CMD(

2
cpu/74xx_7xx/cpu.c
View File

@ -229,7 +229,7 @@ soft_restart(unsigned long addr)
void
do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong addr;
ulong addr;
/* flush and disable I/D cache */
__asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
__asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");

20
cpu/mpc83xx/spd_sdram.c
View File

@ -117,7 +117,7 @@ long int spd_sdram()
unsigned sdram_cfg;
unsigned int ddrc_ecc_enable;
/* Read SPD parameters with I2C */
/* Read SPD parameters with I2C */
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
@ -147,7 +147,7 @@ long int spd_sdram()
spd.ncol_addr);
return 0;
}
/* Setup DDR chip select register */
/* Setup DDR chip select register */
#ifdef CFG_83XX_DDR_USES_CS0
ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[0] = ( 1 << 31
@ -218,13 +218,13 @@ long int spd_sdram()
* CAS Lat DDR I Ctrl
* Clocks SPD Bit Value
* -------+--------+---------
* 1.0 0 001
* 1.5 1 010
* 2.0 2 011
* 2.5 3 100
* 3.0 4 101
* 3.5 5 110
* 4.0 6 111
* 1.0 0 001
* 1.5 1 010
* 2.0 2 011
* 2.5 3 100
* 3.0 4 101
* 3.5 5 110
* 4.0 6 111
*/
caslat = __ilog2(spd.cas_lat);
@ -442,7 +442,7 @@ long int spd_sdram()
/* SS_EN = 0, source synchronous disable
* CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
*/
*/
ddr->sdram_clk_cntl = 0x00000000;
debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);

2
doc/README.mpc8360emds
View File

@ -103,7 +103,7 @@ Freescale MPC8360EMDS Board
Or via tftp:
tftp 10000 u-boot.bin
tftp 10000 u-boot.bin
5.1 Reflash U-boot Image using U-boot

2
drivers/qe/uccf.c
View File

@ -46,7 +46,7 @@ u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
case 6: return QE_CR_SUBBLOCK_UCCFAST7;
case 7: return QE_CR_SUBBLOCK_UCCFAST8;
default: return QE_CR_SUBBLOCK_INVALID;
}
}
}
static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,

791
drivers/qe/uec_phy.c
View File

@ -4,11 +4,11 @@
* Author: Shlomi Gridish
*
* Description: UCC GETH Driver -- PHY handling
* Driver for UEC on QE
* Based on 8260_io/fcc_enet.c
* Driver for UEC on QE
* Based on 8260_io/fcc_enet.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@ -30,16 +30,16 @@
#define UEC_VERBOSE_DEBUG
#define ugphy_printk(format, arg...) \
printf(format "\n", ## arg)
printf(format "\n", ## arg)
#define ugphy_dbg(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_err(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_info(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_warn(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_dbg(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_err(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_info(format, arg...) \
ugphy_printk(format , ## arg)
#define ugphy_warn(format, arg...) \
ugphy_printk(format , ## arg)
#ifdef UEC_VERBOSE_DEBUG
#define ugphy_vdbg ugphy_dbg
@ -47,558 +47,561 @@
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
#endif /* UEC_VERBOSE_DEBUG */
static void config_genmii_advert(struct uec_mii_info *mii_info);
static void genmii_setup_forced(struct uec_mii_info *mii_info);
static void genmii_restart_aneg(struct uec_mii_info *mii_info);
static int gbit_config_aneg(struct uec_mii_info *mii_info);
static int genmii_config_aneg(struct uec_mii_info *mii_info);
static int genmii_update_link(struct uec_mii_info *mii_info);
static int genmii_read_status(struct uec_mii_info *mii_info);
u16 phy_read(struct uec_mii_info *mii_info, u16 regnum);
void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
static void config_genmii_advert (struct uec_mii_info *mii_info);
static void genmii_setup_forced (struct uec_mii_info *mii_info);
static void genmii_restart_aneg (struct uec_mii_info *mii_info);
static int gbit_config_aneg (struct uec_mii_info *mii_info);
static int genmii_config_aneg (struct uec_mii_info *mii_info);
static int genmii_update_link (struct uec_mii_info *mii_info);
static int genmii_read_status (struct uec_mii_info *mii_info);
u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
/* Write value to the PHY for this device to the register at regnum, */
/* waiting until the write is done before it returns. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value)
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
{
uec_private_t *ugeth = (uec_private_t *)dev->priv;
uec_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum;
u32 tmp_reg;
uec_private_t *ugeth = (uec_private_t *) dev->priv;
uec_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
ug_regs = ugeth->uec_regs;
ug_regs = ugeth->uec_regs;
/* Stop the MII management read cycle */
out_be32(&ug_regs->miimcom, 0);
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32(&ug_regs->miimadd, tmp_reg);
/* Stop the MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32 (&ug_regs->miimadd, tmp_reg);
/* Setting up the MII Mangement Control Register with the value */
out_be32(&ug_regs->miimcon, (u32)value);
/* Setting up the MII Mangement Control Register with the value */
out_be32 (&ug_regs->miimcon, (u32) value);
/* Wait till MII management write is complete */
while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY);
/* Wait till MII management write is complete */
while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
udelay(100000);
udelay (100000);
}
/* Reads from register regnum in the PHY for device dev, */
/* returning the value. Clears miimcom first. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
int read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
{
uec_private_t *ugeth = (uec_private_t *)dev->priv;
uec_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum;
u32 tmp_reg;
u16 value;
uec_private_t *ugeth = (uec_private_t *) dev->priv;
uec_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
u16 value;
ug_regs = ugeth->uec_regs;
ug_regs = ugeth->uec_regs;
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ;
out_be32(&ug_regs->miimadd, tmp_reg);
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32 (&ug_regs->miimadd, tmp_reg);
/* Perform an MII management read cycle */
out_be32(&ug_regs->miimcom, 0);
out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
/* Perform an MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
/* Wait till MII management write is complete */
while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY));
/* Wait till MII management write is complete */
while ((in_be32 (&ug_regs->miimind)) &
(MIIMIND_NOT_VALID | MIIMIND_BUSY));
udelay(100000);
udelay (100000);
/* Read MII management status */
value = (u16)in_be32(&ug_regs->miimstat);
if(value == 0xffff)
ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
mii_id, mii_reg, (u32) &(ug_regs->miimcfg));
/* Read MII management status */
value = (u16) in_be32 (&ug_regs->miimstat);
if (value == 0xffff)
ugphy_warn
("read wrong value : mii_id %d,mii_reg %d, base %08x",
mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
return (value);
return (value);
}
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
{
if(mii_info->phyinfo->ack_interrupt)
mii_info->phyinfo->ack_interrupt(mii_info);
if (mii_info->phyinfo->ack_interrupt)
mii_info->phyinfo->ack_interrupt (mii_info);
}
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts)
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts)
{
mii_info->interrupts = interrupts;
if(mii_info->phyinfo->config_intr)
mii_info->phyinfo->config_intr(mii_info);
mii_info->interrupts = interrupts;
if (mii_info->phyinfo->config_intr)
mii_info->phyinfo->config_intr (mii_info);
}
/* Writes MII_ADVERTISE with the appropriate values, after
* sanitizing advertise to make sure only supported features
* are advertised
*/
static void config_genmii_advert(struct uec_mii_info *mii_info)
static void config_genmii_advert (struct uec_mii_info *mii_info)
{
u32 advertise;
u16 adv;
u32 advertise;
u16 adv;
/* Only allow advertising what this PHY supports */
mii_info->advertising &= mii_info->phyinfo->features;
advertise = mii_info->advertising;
/* Only allow advertising what this PHY supports */
mii_info->advertising &= mii_info->phyinfo->features;
advertise = mii_info->advertising;
/* Setup standard advertisement */
adv = phy_read(mii_info, PHY_ANAR);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
phy_write(mii_info, PHY_ANAR, adv);
/* Setup standard advertisement */
adv = phy_read (mii_info, PHY_ANAR);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
phy_write (mii_info, PHY_ANAR, adv);
}
static void genmii_setup_forced(struct uec_mii_info *mii_info)
static void genmii_setup_forced (struct uec_mii_info *mii_info)
{
u16 ctrl;
u32 features = mii_info->phyinfo->features;
u16 ctrl;
u32 features = mii_info->phyinfo->features;
ctrl = phy_read(mii_info, PHY_BMCR);
ctrl = phy_read (mii_info, PHY_BMCR);
ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS|
PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON);
ctrl |= PHY_BMCR_RESET;
ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
ctrl |= PHY_BMCR_RESET;
switch(mii_info->speed) {
case SPEED_1000:
if(features & (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full)) {
ctrl |= PHY_BMCR_1000_MBPS;
break;
}
mii_info->speed = SPEED_100;
case SPEED_100:
if (features & (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full)) {
ctrl |= PHY_BMCR_100_MBPS;
break;
}
mii_info->speed = SPEED_10;
case SPEED_10:
if (features & (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full))
break;
default: /* Unsupported speed! */
ugphy_err("%s: Bad speed!", mii_info->dev->name);
break;
}
switch (mii_info->speed) {
case SPEED_1000:
if (features & (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full)) {
ctrl |= PHY_BMCR_1000_MBPS;
break;
}
mii_info->speed = SPEED_100;
case SPEED_100:
if (features & (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full)) {
ctrl |= PHY_BMCR_100_MBPS;
break;
}
mii_info->speed = SPEED_10;
case SPEED_10:
if (features & (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full))
break;
default: /* Unsupported speed! */
ugphy_err ("%s: Bad speed!", mii_info->dev->name);
break;
}
phy_write(mii_info, PHY_BMCR, ctrl);
phy_write (mii_info, PHY_BMCR, ctrl);
}
/* Enable and Restart Autonegotiation */
static void genmii_restart_aneg(struct uec_mii_info *mii_info)
static void genmii_restart_aneg (struct uec_mii_info *mii_info)
{
u16 ctl;
u16 ctl;
ctl = phy_read(mii_info, PHY_BMCR);
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
phy_write(mii_info, PHY_BMCR, ctl);
ctl = phy_read (mii_info, PHY_BMCR);
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
phy_write (mii_info, PHY_BMCR, ctl);
}
static int gbit_config_aneg(struct uec_mii_info *mii_info)
static int gbit_config_aneg (struct uec_mii_info *mii_info)
{
u16 adv;
u32 advertise;
u16 adv;
u32 advertise;
if(mii_info->autoneg) {
/* Configure the ADVERTISE register */
config_genmii_advert(mii_info);
advertise = mii_info->advertising;
if (mii_info->autoneg) {
/* Configure the ADVERTISE register */
config_genmii_advert (mii_info);
advertise = mii_info->advertising;
adv = phy_read(mii_info, MII_1000BASETCONTROL);
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
MII_1000BASETCONTROL_HALFDUPLEXCAP);
if (advertise & SUPPORTED_1000baseT_Half)
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
if (advertise & SUPPORTED_1000baseT_Full)
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
phy_write(mii_info, MII_1000BASETCONTROL, adv);
adv = phy_read (mii_info, MII_1000BASETCONTROL);
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
MII_1000BASETCONTROL_HALFDUPLEXCAP);
if (advertise & SUPPORTED_1000baseT_Half)
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
if (advertise & SUPPORTED_1000baseT_Full)
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
phy_write (mii_info, MII_1000BASETCONTROL, adv);
/* Start/Restart aneg */
genmii_restart_aneg(mii_info);
} else
genmii_setup_forced(mii_info);
/* Start/Restart aneg */
genmii_restart_aneg (mii_info);
} else
genmii_setup_forced (mii_info);
return 0;
return 0;
}
static int marvell_config_aneg(struct uec_mii_info *mii_info)
static int marvell_config_aneg (struct uec_mii_info *mii_info)
{
/* The Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation */
phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
/* The Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation */
phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
phy_write(mii_info, 0x1d, 0x1f);
phy_write(mii_info, 0x1e, 0x200c);
phy_write(mii_info, 0x1d, 0x5);
phy_write(mii_info, 0x1e, 0);
phy_write(mii_info, 0x1e, 0x100);
phy_write (mii_info, 0x1d, 0x1f);
phy_write (mii_info, 0x1e, 0x200c);
phy_write (mii_info, 0x1d, 0x5);
phy_write (mii_info, 0x1e, 0);
phy_write (mii_info, 0x1e, 0x100);
gbit_config_aneg(mii_info);
gbit_config_aneg (mii_info);
return 0;
return 0;
}
static int genmii_config_aneg(struct uec_mii_info *mii_info)
static int genmii_config_aneg (struct uec_mii_info *mii_info)
{
if (mii_info->autoneg) {
config_genmii_advert(mii_info);
genmii_restart_aneg(mii_info);
} else
genmii_setup_forced(mii_info);
if (mii_info->autoneg) {
config_genmii_advert (mii_info);
genmii_restart_aneg (mii_info);
} else
genmii_setup_forced (mii_info);
return 0;
return 0;
}
static int genmii_update_link(struct uec_mii_info *mii_info)
static int genmii_update_link (struct uec_mii_info *mii_info)
{
u16 status;
u16 status;
/* Do a fake read */
phy_read(mii_info, PHY_BMSR);
/* Do a fake read */
phy_read (mii_info, PHY_BMSR);
/* Read link and autonegotiation status */
status = phy_read(mii_info, PHY_BMSR);
if ((status & PHY_BMSR_LS) == 0)
mii_info->link = 0;
else
mii_info->link = 1;
/* Read link and autonegotiation status */
status = phy_read (mii_info, PHY_BMSR);
if ((status & PHY_BMSR_LS) == 0)
mii_info->link = 0;
else
mii_info->link = 1;
/* If we are autonegotiating, and not done,
* return an error */
if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP))
return -EAGAIN;
/* If we are autonegotiating, and not done,
* return an error */
if (mii_info->autoneg && !(status & PHY_BMSR_AUTN_COMP))
return -EAGAIN;
return 0;
return 0;
}
static int genmii_read_status(struct uec_mii_info *mii_info)
static int genmii_read_status (struct uec_mii_info *mii_info)
{
u16 status;
int err;
u16 status;
int err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link (mii_info);
if (err)
return err;
if (mii_info->autoneg) {
status = phy_read(mii_info, PHY_ANLPAR);
if (mii_info->autoneg) {
status = phy_read (mii_info, PHY_ANLPAR);
if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
mii_info->pause = 0;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
mii_info->pause = 0;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
return 0;
}
static int marvell_read_status(struct uec_mii_info *mii_info)
static int marvell_read_status (struct uec_mii_info *mii_info)
{
u16 status;
int err;
u16 status;
int err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link (mii_info);
if (err)
return err;
/* If the link is up, read the speed and duplex */
/* If we aren't autonegotiating, assume speeds
* are as set */
if (mii_info->autoneg && mii_info->link) {
int speed;
status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
/* If the link is up, read the speed and duplex */
/* If we aren't autonegotiating, assume speeds
* are as set */
if (mii_info->autoneg && mii_info->link) {
int speed;
/* Get the duplexity */
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
/* Get the speed */
speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
switch(speed) {
case MII_M1011_PHY_SPEC_STATUS_1000:
mii_info->speed = SPEED_1000;
break;
case MII_M1011_PHY_SPEC_STATUS_100:
mii_info->speed = SPEED_100;
break;
default:
mii_info->speed = SPEED_10;
break;
}
mii_info->pause = 0;
}
/* Get the duplexity */
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
return 0;
/* Get the speed */
speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
switch (speed) {
case MII_M1011_PHY_SPEC_STATUS_1000:
mii_info->speed = SPEED_1000;
break;
case MII_M1011_PHY_SPEC_STATUS_100:
mii_info->speed = SPEED_100;
break;
default:
mii_info->speed = SPEED_10;
break;
}
mii_info->pause = 0;
}
return 0;
}
static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
{
/* Clear the interrupts by reading the reg */
phy_read(mii_info, MII_M1011_IEVENT);
/* Clear the interrupts by reading the reg */
phy_read (mii_info, MII_M1011_IEVENT);
return 0;
return 0;
}
static int marvell_config_intr(struct uec_mii_info *mii_info)
static int marvell_config_intr (struct uec_mii_info *mii_info)
{
if(mii_info->interrupts == MII_INTERRUPT_ENABLED)
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
else
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
else
phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
return 0;
return 0;
}
static int dm9161_init(struct uec_mii_info *mii_info)
static int dm9161_init (struct uec_mii_info *mii_info)
{
/* Reset the PHY */
phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) |
PHY_BMCR_RESET);
/* PHY and MAC connect*/
phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) &
~PHY_BMCR_ISO);
/* Reset the PHY */
phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
PHY_BMCR_RESET);
/* PHY and MAC connect */
phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
~PHY_BMCR_ISO);
#ifdef CONFIG_RMII_MODE
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT);
phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT);
#else
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
#endif
config_genmii_advert(mii_info);
/* Start/restart aneg */
genmii_config_aneg(mii_info);
/* Delay to wait the aneg compeleted */
udelay(3000000);
config_genmii_advert (mii_info);
/* Start/restart aneg */
genmii_config_aneg (mii_info);
/* Delay to wait the aneg compeleted */
udelay (3000000);
return 0;
return 0;
}
static int dm9161_config_aneg(struct uec_mii_info *mii_info)
static int dm9161_config_aneg (struct uec_mii_info *mii_info)
{
return 0;
return 0;
}
static int dm9161_read_status(struct uec_mii_info *mii_info)
static int dm9161_read_status (struct uec_mii_info *mii_info)
{
u16 status;
int err;
u16 status;
int err;
/* Update the link, but return if there was an error*/
err = genmii_update_link(mii_info);
if (err)
return err;
/* If the link is up, read the speed and duplex
If we aren't autonegotiating assume speeds are as set */
if (mii_info->autoneg && mii_info->link) {
status = phy_read(mii_info, MII_DM9161_SCSR);
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
/* Update the link, but return if there was an error */
err = genmii_update_link (mii_info);
if (err)
return err;
/* If the link is up, read the speed and duplex
If we aren't autonegotiating assume speeds are as set */
if (mii_info->autoneg && mii_info->link) {
status = phy_read (mii_info, MII_DM9161_SCSR);
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
}
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
}
return 0;
return 0;
}
static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
{
/* Clear the interrupt by reading the reg */
phy_read(mii_info, MII_DM9161_INTR);
/* Clear the interrupt by reading the reg */
phy_read (mii_info, MII_DM9161_INTR);
return 0;
return 0;
}
static int dm9161_config_intr(struct uec_mii_info *mii_info)
static int dm9161_config_intr (struct uec_mii_info *mii_info)
{
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
else
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
else
phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
return 0;
return 0;
}
static void dm9161_close(struct uec_mii_info *mii_info)
static void dm9161_close (struct uec_mii_info *mii_info)
{
}
static struct phy_info phy_info_dm9161 = {
.phy_id = 0x0181b880,
.phy_id_mask = 0x0ffffff0,
.name = "Davicom DM9161E",
.init = dm9161_init,
.config_aneg = dm9161_config_aneg,
.read_status = dm9161_read_status,
.close = dm9161_close,
.phy_id = 0x0181b880,
.phy_id_mask = 0x0ffffff0,
.name = "Davicom DM9161E",
.init = dm9161_init,
.config_aneg = dm9161_config_aneg,
.read_status = dm9161_read_status,
.close = dm9161_close,
};
static struct phy_info phy_info_dm9161a = {
.phy_id = 0x0181b8a0,
.phy_id_mask = 0x0ffffff0,
.name = "Davicom DM9161A",
.features = MII_BASIC_FEATURES,
.init = dm9161_init,
.config_aneg = dm9161_config_aneg,
.read_status = dm9161_read_status,
.ack_interrupt = dm9161_ack_interrupt,
.config_intr = dm9161_config_intr,
.close = dm9161_close,
.phy_id = 0x0181b8a0,
.phy_id_mask = 0x0ffffff0,
.name = "Davicom DM9161A",
.features = MII_BASIC_FEATURES,
.init = dm9161_init,
.config_aneg = dm9161_config_aneg,
.read_status = dm9161_read_status,
.ack_interrupt = dm9161_ack_interrupt,
.config_intr = dm9161_config_intr,
.close = dm9161_close,
};
static struct phy_info phy_info_marvell = {
.phy_id = 0x01410c00,
.phy_id_mask = 0xffffff00,
.name = "Marvell 88E11x1",
.features = MII_GBIT_FEATURES,
.config_aneg = &marvell_config_aneg,
.read_status = &marvell_read_status,
.ack_interrupt = &marvell_ack_interrupt,
.config_intr = &marvell_config_intr,
.phy_id = 0x01410c00,
.phy_id_mask = 0xffffff00,
.name = "Marvell 88E11x1",
.features = MII_GBIT_FEATURES,
.config_aneg = &marvell_config_aneg,
.read_status = &marvell_read_status,
.ack_interrupt = &marvell_ack_interrupt,
.config_intr = &marvell_config_intr,
};
static struct phy_info phy_info_genmii= {
.phy_id = 0x00000000,
.phy_id_mask = 0x00000000,
.name = "Generic MII",
.features = MII_BASIC_FEATURES,
.config_aneg = genmii_config_aneg,
.read_status = genmii_read_status,
static struct phy_info phy_info_genmii = {
.phy_id = 0x00000000,
.phy_id_mask = 0x00000000,
.name = "Generic MII",
.features = MII_BASIC_FEATURES,
.config_aneg = genmii_config_aneg,
.read_status = genmii_read_status,
};
static struct phy_info *phy_info[] = {
&phy_info_dm9161,
&phy_info_dm9161a,
&phy_info_marvell,
&phy_info_genmii,
NULL
&phy_info_dm9161,
&phy_info_dm9161a,
&phy_info_marvell,
&phy_info_genmii,
NULL
};
u16 phy_read(struct uec_mii_info *mii_info, u16 regnum)
u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
{
return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
}
void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
{
mii_info->mdio_write(mii_info->dev,
mii_info->mii_id,
regnum, val);
mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
}
/* Use the PHY ID registers to determine what type of PHY is attached
* to device dev. return a struct phy_info structure describing that PHY
*/
struct phy_info * get_phy_info(struct uec_mii_info *mii_info)
struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
{
u16 phy_reg;
u32 phy_ID;
int i;
struct phy_info *theInfo = NULL;
u16 phy_reg;
u32 phy_ID;
int i;
struct phy_info *theInfo = NULL;
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = phy_read(mii_info, PHY_PHYIDR1);
phy_ID = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = phy_read (mii_info, PHY_PHYIDR1);
phy_ID = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR2, and put them in the lower half */
phy_reg = phy_read(mii_info, PHY_PHYIDR2);
phy_ID |= (phy_reg & 0xffff);
/* Grab the bits from PHYIR2, and put them in the lower half */
phy_reg = phy_read (mii_info, PHY_PHYIDR2);
phy_ID |= (phy_reg & 0xffff);
/* loop through all the known PHY types, and find one that */
/* matches the ID we read from the PHY. */
for (i = 0; phy_info[i]; i++)
if (phy_info[i]->phy_id ==
(phy_ID & phy_info[i]->phy_id_mask)) {
theInfo = phy_info[i];
break;
}
/* loop through all the known PHY types, and find one that */
/* matches the ID we read from the PHY. */
for (i = 0; phy_info[i]; i++)
if (phy_info[i]->phy_id ==
(phy_ID & phy_info[i]->phy_id_mask)) {
theInfo = phy_info[i];
break;
}
/* This shouldn't happen, as we have generic PHY support */
if (theInfo == NULL) {
ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
return NULL;
} else {
ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
}
/* This shouldn't happen, as we have generic PHY support */
if (theInfo == NULL) {
ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
return NULL;
} else {
ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
}
return theInfo;
return theInfo;
}
void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
void marvell_phy_interface_mode (struct eth_device *dev,
enet_interface_e mode)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
struct uec_mii_info *mii_info;
uec_private_t *uec = (uec_private_t *) dev->priv;
struct uec_mii_info *mii_info;
if (!uec->mii_info) {
printf("%s: the PHY not intialized\n", __FUNCTION__);
printf ("%s: the PHY not intialized\n", __FUNCTION__);
return;
}
mii_info = uec->mii_info;
if (mode == ENET_100_RGMII) {
phy_write(mii_info, 0x00, 0x9140);
phy_write(mii_info, 0x1d, 0x001f);
phy_write(mii_info, 0x1e, 0x200c);
phy_write(mii_info, 0x1d, 0x0005);
phy_write(mii_info, 0x1e, 0x0000);
phy_write(mii_info, 0x1e, 0x0100);
phy_write(mii_info, 0x09, 0x0e00);
phy_write(mii_info, 0x04, 0x01e1);
phy_write(mii_info, 0x00, 0x9140);
phy_write(mii_info, 0x00, 0x1000);
udelay(100000);
phy_write(mii_info, 0x00, 0x2900);
phy_write(mii_info, 0x14, 0x0cd2);
phy_write(mii_info, 0x00, 0xa100);
phy_write(mii_info, 0x09, 0x0000);
phy_write(mii_info, 0x1b, 0x800b);
phy_write(mii_info, 0x04, 0x05e1);
phy_write(mii_info, 0x00, 0xa100);
phy_write(mii_info, 0x00, 0x2100);
udelay(1000000);
phy_write (mii_info, 0x00, 0x9140);
phy_write (mii_info, 0x1d, 0x001f);
phy_write (mii_info, 0x1e, 0x200c);
phy_write (mii_info, 0x1d, 0x0005);
phy_write (mii_info, 0x1e, 0x0000);
phy_write (mii_info, 0x1e, 0x0100);
phy_write (mii_info, 0x09, 0x0e00);
phy_write (mii_info, 0x04, 0x01e1);
phy_write (mii_info, 0x00, 0x9140);
phy_write (mii_info, 0x00, 0x1000);
udelay (100000);
phy_write (mii_info, 0x00, 0x2900);
phy_write (mii_info, 0x14, 0x0cd2);
phy_write (mii_info, 0x00, 0xa100);
phy_write (mii_info, 0x09, 0x0000);
phy_write (mii_info, 0x1b, 0x800b);
phy_write (mii_info, 0x04, 0x05e1);
phy_write (mii_info, 0x00, 0xa100);
phy_write (mii_info, 0x00, 0x2100);
udelay (1000000);
} else if (mode == ENET_10_RGMII) {
phy_write(mii_info, 0x14, 0x8e40);
phy_write(mii_info, 0x1b, 0x800b);
phy_write(mii_info, 0x14, 0x0c82);
phy_write(mii_info, 0x00, 0x8100);
udelay(1000000);
phy_write (mii_info, 0x14, 0x8e40);
phy_write (mii_info, 0x1b, 0x800b);
phy_write (mii_info, 0x14, 0x0c82);
phy_write (mii_info, 0x00, 0x8100);
udelay (1000000);
}
}
void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
{
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
marvell_phy_interface_mode(dev, mode);
marvell_phy_interface_mode (dev, mode);
#endif
}
#endif /* CONFIG_QE */

299
drivers/qe/uec_phy.h
View File

@ -4,11 +4,11 @@
* Author: Shlomi Gridish <gridish@freescale.com>
*
* Description: UCC ethernet driver -- PHY handling
* Driver for UEC on QE
* Based on 8260_io/fcc_enet.c
* Driver for UEC on QE
* Based on 8260_io/fcc_enet.c
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
@ -19,37 +19,37 @@
#define MII_end ((u32)-2)
#define MII_read ((u32)-1)
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define UGETH_AN_TIMEOUT 2000
#define UGETH_AN_TIMEOUT 2000
/* 1000BT control (Marvell & BCM54xx at least) */
#define MII_1000BASETCONTROL 0x09
#define MII_1000BASETCONTROL 0x09
#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
/* Cicada Extended Control Register 1 */
#define MII_CIS8201_EXT_CON1 0x17
#define MII_CIS8201_EXT_CON1 0x17
#define MII_CIS8201_EXTCON1_INIT 0x0000
/* Cicada Interrupt Mask Register */
#define MII_CIS8201_IMASK 0x19
#define MII_CIS8201_IMASK_IEN 0x8000
#define MII_CIS8201_IMASK_SPEED 0x4000
#define MII_CIS8201_IMASK_LINK 0x2000
#define MII_CIS8201_IMASK 0x19
#define MII_CIS8201_IMASK_IEN 0x8000
#define MII_CIS8201_IMASK_SPEED 0x4000
#define MII_CIS8201_IMASK_LINK 0x2000
#define MII_CIS8201_IMASK_DUPLEX 0x1000
#define MII_CIS8201_IMASK_MASK 0xf000
#define MII_CIS8201_IMASK_MASK 0xf000
/* Cicada Interrupt Status Register */
#define MII_CIS8201_ISTAT 0x1a
#define MII_CIS8201_ISTAT 0x1a
#define MII_CIS8201_ISTAT_STATUS 0x8000
#define MII_CIS8201_ISTAT_SPEED 0x4000
#define MII_CIS8201_ISTAT_LINK 0x2000
#define MII_CIS8201_ISTAT_SPEED 0x4000
#define MII_CIS8201_ISTAT_LINK 0x2000
#define MII_CIS8201_ISTAT_DUPLEX 0x1000
/* Cicada Auxiliary Control/Status Register */
#define MII_CIS8201_AUX_CONSTAT 0x1c
#define MII_CIS8201_AUX_CONSTAT 0x1c
#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
@ -57,155 +57,156 @@
#define MII_CIS8201_AUXCONSTAT_100 0x0008
/* 88E1011 PHY Status Register */
#define MII_M1011_PHY_SPEC_STATUS 0x11
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
#define MII_M1011_PHY_SPEC_STATUS 0x11
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
#define MII_M1011_IEVENT 0x13
#define MII_M1011_IEVENT_CLEAR 0x0000
#define MII_M1011_IEVENT 0x13
#define MII_M1011_IEVENT_CLEAR 0x0000
#define MII_M1011_IMASK 0x12
#define MII_M1011_IMASK_INIT 0x6400
#define MII_M1011_IMASK_CLEAR 0x0000
#define MII_M1011_IMASK 0x12
#define MII_M1011_IMASK_INIT 0x6400
#define MII_M1011_IMASK_CLEAR 0x0000
#define MII_DM9161_SCR 0x10
#define MII_DM9161_SCR_INIT 0x0610
#define MII_DM9161_SCR 0x10
#define MII_DM9161_SCR_INIT 0x0610
#define MII_DM9161_SCR_RMII_INIT 0x0710
/* DM9161 Specified Configuration and Status Register */
#define MII_DM9161_SCSR 0x11
#define MII_DM9161_SCSR_100F 0x8000
#define MII_DM9161_SCSR_100H 0x4000
#define MII_DM9161_SCSR_10F 0x2000
#define MII_DM9161_SCSR_10H 0x1000
#define MII_DM9161_SCSR 0x11
#define MII_DM9161_SCSR_100F 0x8000
#define MII_DM9161_SCSR_100H 0x4000
#define MII_DM9161_SCSR_10F 0x2000
#define MII_DM9161_SCSR_10H 0x1000
/* DM9161 Interrupt Register */
#define MII_DM9161_INTR 0x15
#define MII_DM9161_INTR_PEND 0x8000
#define MII_DM9161_INTR_DPLX_MASK 0x0800
#define MII_DM9161_INTR_SPD_MASK 0x0400
#define MII_DM9161_INTR_LINK_MASK 0x0200
#define MII_DM9161_INTR_MASK 0x0100
#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
#define MII_DM9161_INTR_SPD_CHANGE 0x0008
#define MII_DM9161_INTR_LINK_CHANGE 0x0004
#define MII_DM9161_INTR_INIT 0x0000
#define MII_DM9161_INTR_STOP \
#define MII_DM9161_INTR 0x15
#define MII_DM9161_INTR_PEND 0x8000
#define MII_DM9161_INTR_DPLX_MASK 0x0800
#define MII_DM9161_INTR_SPD_MASK 0x0400
#define MII_DM9161_INTR_LINK_MASK 0x0200
#define MII_DM9161_INTR_MASK 0x0100
#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
#define MII_DM9161_INTR_SPD_CHANGE 0x0008
#define MII_DM9161_INTR_LINK_CHANGE 0x0004
#define MII_DM9161_INTR_INIT 0x0000
#define MII_DM9161_INTR_STOP \
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
| MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
/* DM9161 10BT Configuration/Status */
#define MII_DM9161_10BTCSR 0x12
#define MII_DM9161_10BTCSR_INIT 0x7800
#define MII_DM9161_10BTCSR 0x12
#define MII_DM9161_10BTCSR_INIT 0x7800
#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | \
SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | \
SUPPORTED_TP | \
SUPPORTED_MII)
SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | \
SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | \
SUPPORTED_TP | \
SUPPORTED_MII)
#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
SUPPORTED_1000baseT_Half | \
SUPPORTED_1000baseT_Full)
SUPPORTED_1000baseT_Half | \
SUPPORTED_1000baseT_Full)
#define MII_READ_COMMAND 0x00000001
#define MII_READ_COMMAND 0x00000001
#define MII_INTERRUPT_DISABLED 0x0
#define MII_INTERRUPT_ENABLED 0x1
#define MII_INTERRUPT_DISABLED 0x0
#define MII_INTERRUPT_ENABLED 0x1
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
/* Duplex, half or full. */
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
/* Indicates what features are supported by the interface. */
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_RESV 0x1c00 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_RESV 0x1c00 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Taken from mii_if_info and sungem_phy.h */
struct uec_mii_info {
/* Information about the PHY type */
/* And management functions */
struct phy_info *phyinfo;
/* Information about the PHY type */
/* And management functions */
struct phy_info *phyinfo;
struct eth_device *dev;
struct eth_device *dev;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
int pause;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
int pause;
/* The most recently read link state */
int link;
/* The most recently read link state */
int link;
/* Enabled Interrupts */
u32 interrupts;
/* Enabled Interrupts */
u32 interrupts;
u32 advertising;
int autoneg;
int mii_id;
u32 advertising;
int autoneg;
int mii_id;
/* private data pointer */
/* For use by PHYs to maintain extra state */
void *priv;
/* private data pointer */
/* For use by PHYs to maintain extra state */
void *priv;
/* Provided by ethernet driver */
int (*mdio_read) (struct eth_device *dev, int mii_id, int reg);
void (*mdio_write) (struct eth_device *dev, int mii_id, int reg, int val);
/* Provided by ethernet driver */
int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
int val);
};
/* struct phy_info: a structure which defines attributes for a PHY
@ -221,36 +222,38 @@ struct uec_mii_info {
* Each PHY must declare config_aneg, and read_status.
*/
struct phy_info {
u32 phy_id;
char *name;
unsigned int phy_id_mask;
u32 features;
u32 phy_id;
char *name;
unsigned int phy_id_mask;
u32 features;
/* Called to initialize the PHY */
int (*init)(struct uec_mii_info *mii_info);
/* Called to initialize the PHY */
int (*init) (struct uec_mii_info * mii_info);
/* Called to suspend the PHY for power */
int (*suspend)(struct uec_mii_info *mii_info);
/* Called to suspend the PHY for power */
int (*suspend) (struct uec_mii_info * mii_info);
/* Reconfigures autonegotiation (or disables it) */
int (*config_aneg)(struct uec_mii_info *mii_info);
/* Reconfigures autonegotiation (or disables it) */
int (*config_aneg) (struct uec_mii_info * mii_info);
/* Determines the negotiated speed and duplex */
int (*read_status)(struct uec_mii_info *mii_info);
/* Determines the negotiated speed and duplex */
int (*read_status) (struct uec_mii_info * mii_info);
/* Clears any pending interrupts */
int (*ack_interrupt)(struct uec_mii_info *mii_info);
/* Clears any pending interrupts */
int (*ack_interrupt) (struct uec_mii_info * mii_info);
/* Enables or disables interrupts */
int (*config_intr)(struct uec_mii_info *mii_info);
/* Enables or disables interrupts */
int (*config_intr) (struct uec_mii_info * mii_info);
/* Clears up any memory if needed */
void (*close)(struct uec_mii_info *mii_info);
/* Clears up any memory if needed */
void (*close) (struct uec_mii_info * mii_info);
};
struct phy_info *get_phy_info(struct uec_mii_info *mii_info);
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value);
int read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts);
struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
int value);
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts);
#endif /* __UEC_PHY_H__ */

630
include/asm-ppc/immap_83xx.h
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File diff suppressed because it is too large Load Diff

144
include/configs/MPC8349ITX.h
View File

@ -38,17 +38,17 @@
0xFF80_0000-0xFFFF_FFFF Boot Flash (8 MB)
I2C address list:
Align. Board
Bus Addr Part No. Description Length Location
Align. Board
Bus Addr Part No. Description Length Location
----------------------------------------------------------------
I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
I2C1 0x20 PCF8574 I2C Expander 0 U8
I2C1 0x21 PCF8574 I2C Expander 0 U10
I2C1 0x38 PCF8574A I2C Expander 0 U8
I2C1 0x39 PCF8574A I2C Expander 0 U10
I2C1 0x51 (DDR) DDR EEPROM 1 U1
I2C1 0x68 DS1339 RTC 1 U68
I2C1 0x20 PCF8574 I2C Expander 0 U8
I2C1 0x21 PCF8574 I2C Expander 0 U10
I2C1 0x38 PCF8574A I2C Expander 0 U8
I2C1 0x39 PCF8574A I2C Expander 0 U10
I2C1 0x51 (DDR) DDR EEPROM 1 U1
I2C1 0x68 DS1339 RTC 1 U68
Note that a given board has *either* a pair of 8574s or a pair of 8574As.
*/
@ -80,15 +80,15 @@
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */
#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
@ -96,7 +96,7 @@
#define CFG_I2C_SLAVE 0x7F
/* Don't probe these addresses: */
#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \
#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \
{1, CFG_I2C_8574_ADDR2}, \
{1, CFG_I2C_8574A_ADDR1}, \
{1, CFG_I2C_8574A_ADDR2}}
@ -131,9 +131,9 @@
#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00003000 /* memtest region */
#define CFG_MEMTEST_END 0x07100000 /* only has 128M */
#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00003000 /* memtest region */
#define CFG_MEMTEST_END 0x07100000 /* only has 128M */
/*
* DDR Setup
@ -157,7 +157,7 @@
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#undef CONFIG_DDR_2T_TIMING
#undef CONFIG_DDR_2T_TIMING
#define CFG_83XX_DDR_USES_CS0
#ifndef CONFIG_SPD_EEPROM
@ -214,13 +214,13 @@
#ifdef CONFIG_COMPACT_FLASH
#define CFG_CF_BASE 0xF0000000
#define CFG_CF_BASE 0xF0000000
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V)
#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
#define CFG_LBLAWBAR2_PRELIM CFG_CF_BASE /* Window base at flash base + LED & Board ID */
#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */
#define CFG_LBLAWAR2_PRELIM 0x8000000F /* 64K bytes */
#undef CONFIG_IDE_RESET
#undef CONFIG_IDE_PREINIT
@ -241,27 +241,27 @@
#define CONFIG_DOS_PARTITION
#define CFG_MID_FLASH_JUMP 0x7F000000
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_MID_FLASH_JUMP 0x7F000000
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#undef CFG_RAMBOOT
#endif
#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/*
* Local Bus LCRR and LBCR regs
@ -287,7 +287,7 @@
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
*/
@ -316,9 +316,9 @@
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
@ -329,16 +329,16 @@
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
| CFG_LBC_LSDMR_BSMA1516 \
| CFG_LBC_LSDMR_RFCR8 \
| CFG_LBC_LSDMR_PRETOACT6 \
@ -381,7 +381,7 @@
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@ -430,7 +430,7 @@
#define _IO_BASE 0x00000000 /* points to PCI I/O space */
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#ifdef CONFIG_RTL8139
/* This macro is used by RTL8139 but not defined in PPC architecture */
@ -462,14 +462,14 @@
#ifdef CONFIG_MPC83XX_TSEC1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
#define TSEC2_PHYIDX 0
@ -486,7 +486,7 @@
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH /* Flash is not usable now */
@ -518,13 +518,13 @@
#define CONFIG_COMMANDS_I2C 0
#endif
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CONFIG_COMMANDS_CF | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CONFIG_COMMANDS_I2C | \
CONFIG_COMMANDS_PCI | \
CFG_CMD_SDRAM | \
CFG_CMD_NET | \
CFG_CMD_PING | \
CONFIG_COMMANDS_I2C | \
CONFIG_COMMANDS_PCI | \
CFG_CMD_SDRAM | \
CFG_CMD_DATE | \
CFG_CMD_CACHE | \
CFG_CMD_IRQ)
@ -534,13 +534,13 @@
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_WATCHDOG
#define CFG_WATCHDOG_VALUE 0xFFFFFFC3
#define CFG_WATCHDOG_VALUE 0xFFFFFFC3
#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */
@ -550,7 +550,7 @@
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
@ -569,7 +569,7 @@
#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */
#endif
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define CFG_HRCW_LOW (\
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
@ -623,7 +623,7 @@
#define CFG_HID0_FINAL CFG_HID0_INIT
#define CFG_HID2 HID2_HBE
#define CFG_HID2 HID2_HBE
/* DDR @ 0x00000000 */
#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
@ -741,7 +741,7 @@
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#undef CONFIG_BOOTCOMMAND
#ifdef CONFIG_BOOTCOMMAND
@ -761,7 +761,7 @@
MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \
" console=ttyS0," MK_STR(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
"tftpflash=tftpboot $loadaddr " MK_STR(CONFIG_UBOOTPATH) "; " \
"erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
@ -776,25 +776,25 @@
"tftplinux=tftpboot $loadaddr $bootfile; bootm\0" \
"copyuboot=erase " MK_STR(CONFIG_UBOOTSTART) " " MK_STR(CONFIG_UBOOTEND) "; " \
"cp.b fef00000 " MK_STR(CONFIG_UBOOTSTART) " 80000\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8349emitx.dtb\0" \
""
"fdtaddr=400000\0" \
"fdtfile=mpc8349emitx.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"

82
include/configs/MPC8360EMDS.h
View File

@ -10,7 +10,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -120,7 +120,7 @@
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */
#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */
#endif
@ -141,7 +141,7 @@
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef CFG_RAMBOOT
#undef CFG_RAMBOOT
#endif
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
@ -217,7 +217,7 @@
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* CFG_LBC_SDRAM_BASE should be masked and OR'ed into
@ -233,10 +233,10 @@
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
* 13 rows OR2[23-25] = 100
* 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
* 0 4 8 12 16 20 24 28
* 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
@ -248,13 +248,13 @@
/*
* LSDMR masks
*/
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON 0x0063b723
@ -311,7 +311,7 @@
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@ -335,7 +335,7 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
#define CFG_I2C2_OFFSET 0x3100
/*
* Config on-board RTC
@ -369,7 +369,7 @@
#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#endif /* CONFIG_PCI */
@ -393,7 +393,7 @@
#define CFG_UEC1_TX_CLK QE_CLK9
#define CFG_UEC1_ETH_TYPE GIGA_ETH
#define CFG_UEC1_PHY_ADDR 0
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
#endif
#define CONFIG_UEC_ETH2 /* GETH2 */
@ -404,7 +404,7 @@
#define CFG_UEC2_TX_CLK QE_CLK4
#define CFG_UEC2_ETH_TYPE GIGA_ETH
#define CFG_UEC2_PHY_ADDR 1
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
#endif
/*
@ -414,7 +414,7 @@
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
@ -428,16 +428,16 @@
#if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_PCI \
| CFG_CMD_I2C) \
| CFG_CMD_PCI \
| CFG_CMD_I2C) \
& \
~(CFG_CMD_ENV \
| CFG_CMD_LOADS))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C) \
@ -447,13 +447,13 @@
#endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C)
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \
| CFG_CMD_ASKENV \
| CFG_CMD_I2C )
@ -593,39 +593,39 @@
#if defined(CONFIG_UEC_ETH)
#define CONFIG_ETHADDR 00:04:9f:ef:01:01
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
"fdtaddr=400000\0" \
"fdtfile=mpc8349emds.dtb\0" \
""
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"

1
include/ioports.h
View File

@ -63,4 +63,3 @@ typedef struct {
} qe_iop_conf_t;
#define QE_IOP_TAB_END (-1)

22
lib_ppc/board.c
View File

@ -521,17 +521,17 @@ void board_init_f (ulong bootflag)
bd->bi_pevfreq = gd->pev_clk;
bd->bi_flbfreq = gd->flb_clk;
/* store bootparam to sram (backward compatible), here? */
{
u32 *sram = (u32 *)CFG_SRAM_BASE;
*sram++ = gd->ram_size;
*sram++ = gd->bus_clk;
*sram++ = gd->inp_clk;
*sram++ = gd->cpu_clk;
*sram++ = gd->vco_clk;
*sram++ = gd->flb_clk;
*sram++ = 0xb8c3ba11; /* boot signature */
}
/* store bootparam to sram (backward compatible), here? */
{
u32 *sram = (u32 *)CFG_SRAM_BASE;
*sram++ = gd->ram_size;
*sram++ = gd->bus_clk;
*sram++ = gd->inp_clk;
*sram++ = gd->cpu_clk;
*sram++ = gd->vco_clk;
*sram++ = gd->flb_clk;
*sram++ = 0xb8c3ba11; /* boot signature */
}
#endif
bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */