powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Dipen Dudhat
Kumar Gala
parent
52f90dad60
commit
d793e5a840
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@ -569,6 +569,8 @@ MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freesca
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MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
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P1010RDB_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB
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P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT
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P1010RDB_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,NAND
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P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND
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P1010RDB_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SDCARD
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P1010RDB_SPIFLASH powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,SPIFLASH
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P1010RDB_36BIT_SDCARD powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,SDCARD
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@ -33,6 +33,7 @@
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#ifdef CONFIG_P1010RDB
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#define CONFIG_P1010
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#define CONFIG_NAND_FSL_IFC
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#endif
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#ifdef CONFIG_SDCARD
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@ -47,6 +48,17 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
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#endif
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#ifdef CONFIG_NAND /* NAND Boot */
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#define CONFIG_RAMBOOT_NAND
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#define CONFIG_NAND_U_BOOT
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#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
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#else
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#endif /* CONFIG_NAND_SPL */
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0xeff80000
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#endif
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@ -221,6 +233,11 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_CCSRBAR 0xffe00000
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
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/* Don't relocate CCSRBAR while in NAND_SPL */
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#endif
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/*
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* Memory map
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*
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@ -305,6 +322,12 @@ extern unsigned long get_sdram_size(void);
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| CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
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| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
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/* NAND Flash Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
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FTIM0_NAND_TWP(0x0C) | \
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@ -322,6 +345,22 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_NAND_DDR_LAW 11
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/* Set up IFC registers for boot location NOR/NAND */
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#ifdef CONFIG_NAND_U_BOOT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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@ -336,6 +375,16 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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/* NAND boot: 8K NAND loader config */
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#define CONFIG_SYS_NAND_SPL_SIZE 0x2000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
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#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
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#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x10000
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
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/* CPLD on IFC */
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#define CONFIG_SYS_CPLD_BASE 0xffb00000
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@ -393,6 +442,9 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#ifdef CONFIG_NAND_SPL
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#define CONFIG_NS16550_MIN_FUNCTIONS
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#endif
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#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
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@ -449,6 +501,7 @@ extern unsigned long get_sdram_size(void);
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* SPI interface will not be available in case of NAND boot SPI CS0 will be
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* used for SLIC
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*/
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#ifndef CONFIG_NAND_U_BOOT
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/* eSPI - Enhanced SPI */
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#define CONFIG_FSL_ESPI
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#define CONFIG_SPI_FLASH
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@ -456,6 +509,7 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#endif
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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@ -559,6 +613,11 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#define CONFIG_ENV_SIZE 0x2000
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#elif defined(CONFIG_NAND_U_BOOT)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
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#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_U_BOOT_SIZE
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#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
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#else
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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@ -0,0 +1,141 @@
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#
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# (C) Copyright 2007
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# Stefan Roese, DENX Software Engineering, sr@denx.de.
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#
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# Copyright 2011 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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NAND_SPL := y
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CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
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PAD_TO := 0xff802000
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include $(TOPDIR)/config.mk
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nandobj := $(OBJTREE)/nand_spl/
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LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
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LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
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$(LDFLAGS_FINAL)
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AFLAGS += -DCONFIG_NAND_SPL
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CFLAGS += -DCONFIG_NAND_SPL
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SOBJS = start.o resetvec.o ticks.o
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COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
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nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
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SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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__OBJS := $(SOBJS) $(COBJS)
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LNDIR := $(nandobj)board/$(BOARDDIR)
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ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
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all: $(obj).depend $(ALL)
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$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
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$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
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$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
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$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
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cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
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-Map $(nandobj)u-boot-spl.map \
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-o $(nandobj)u-boot-spl
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$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
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$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
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# create symbolic links for common files
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$(obj)cache.c:
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@rm -f $(obj)cache.c
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ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
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$(obj)cpu_init_early.c:
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@rm -f $(obj)cpu_init_early.c
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ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
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$(obj)cpu_init_nand.c:
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@rm -f $(obj)cpu_init_nand.c
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ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
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$(obj)fsl_law.c:
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@rm -f $(obj)fsl_law.c
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ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
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$(obj)law.c:
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@rm -f $(obj)law.c
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ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
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$(obj)nand_boot_fsl_ifc.c:
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@rm -f $(obj)nand_boot_fsl_ifc.c
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ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
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$(obj)nand_boot_fsl_ifc.c
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$(obj)ns16550.c:
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@rm -f $(obj)ns16550.c
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ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
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$(obj)resetvec.S:
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@rm -f $(obj)resetvec.S
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ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
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$(obj)fixed_ivor.S:
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@rm -f $(obj)fixed_ivor.S
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ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
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$(obj)start.S: $(obj)fixed_ivor.S
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@rm -f $(obj)start.S
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ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
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$(obj)ticks.S:
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@rm -f $(obj)ticks.S
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ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
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$(obj)tlb.c:
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@rm -f $(obj)tlb.c
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ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
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$(obj)tlb_table.c:
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@rm -f $(obj)tlb_table.c
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ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
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ifneq ($(OBJTREE), $(SRCTREE))
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$(obj)nand_boot.c:
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@rm -f $(obj)nand_boot.c
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ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
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endif
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#########################################################################
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$(obj)%.o: $(obj)%.S
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$(CC) $(AFLAGS) -c -o $@ $<
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$(obj)%.o: $(obj)%.c
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$(CC) $(CFLAGS) -c -o $@ $<
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,130 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <mpc85xx.h>
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#include <asm/io.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_law.h>
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#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); }
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unsigned long ddr_freq_mhz;
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void sdram_init(void)
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{
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ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
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out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
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out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
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out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
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if (ddr_freq_mhz < 700) {
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
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out_be32(&ddr->ddr_wrlvl_cntl,
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CONFIG_SYS_DDR_WRLVL_CONTROL_667);
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} else {
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out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
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out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
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out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
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out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
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out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
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out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
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out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
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out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
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out_be32(&ddr->ddr_wrlvl_cntl,
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CONFIG_SYS_DDR_WRLVL_CONTROL_800);
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}
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out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
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out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
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out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
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/* mimic 500us delay, with busy isync() loop */
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udelay(100);
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/* Let the controller go */
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out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
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set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
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||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio, ddr_ratio;
|
||||
unsigned long bus_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
|
||||
ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
||||
ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
/* Initialize the DDR3 */
|
||||
sdram_init();
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
|
||||
CONFIG_SYS_NAND_U_BOOT_RELOC);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
Loading…
Reference in New Issue