arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
This commit is contained in:
Wang Huan
York Sun
parent
d6c1ffc7d2
commit
d60a2099a2
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#
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# Copyright 2014 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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obj-y += clock.o
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obj-y += timer.o
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obj-$(CONFIG_OF_LIBFDT) += fdt.o
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obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <fsl_ifc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#endif
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void get_sys_info(struct sys_info *sys_info)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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#ifdef CONFIG_FSL_IFC
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struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
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u32 ccr;
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#endif
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struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
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unsigned int cpu;
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const u8 core_cplx_pll[6] = {
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[0] = 0, /* CC1 PPL / 1 */
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[1] = 0, /* CC1 PPL / 2 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 1, /* CC2 PPL / 2 */
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};
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const u8 core_cplx_pll_div[6] = {
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[0] = 1, /* CC1 PPL / 1 */
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[1] = 2, /* CC1 PPL / 2 */
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[4] = 1, /* CC2 PPL / 1 */
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[5] = 2, /* CC2 PPL / 2 */
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};
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uint i;
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uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
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uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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sys_info->freq_systembus = sysclk;
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#ifdef CONFIG_DDR_CLK_FREQ
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sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
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#else
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sys_info->freq_ddrbus = sysclk;
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#endif
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sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >>
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RCWSR0_SYS_PLL_RAT_SHIFT) & RCWSR0_SYS_PLL_RAT_MASK;
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sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >>
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RCWSR0_MEM_PLL_RAT_SHIFT) & RCWSR0_MEM_PLL_RAT_MASK;
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for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
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ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
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if (ratio[i] > 4)
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freq_c_pll[i] = sysclk * ratio[i];
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else
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freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
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}
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for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
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u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
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& 0xf;
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u32 cplx_pll = core_cplx_pll[c_pll_sel];
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sys_info->freq_processor[cpu] =
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freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
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}
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#if defined(CONFIG_FSL_IFC)
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ccr = in_be32(&ifc_regs->ifc_ccr);
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ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
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sys_info->freq_localbus = sys_info->freq_systembus / ccr;
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#endif
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}
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int get_clocks(void)
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{
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struct sys_info sys_info;
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus;
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gd->mem_clk = sys_info.freq_ddrbus * 2;
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#if defined(CONFIG_FSL_ESDHC)
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gd->arch.sdhc_clk = gd->bus_clk;
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#endif
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return 0;
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}
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ulong get_bus_freq(ulong dummy)
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{
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return gd->bus_clk;
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}
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ulong get_ddr_freq(ulong dummy)
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{
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return gd->mem_clk;
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}
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int get_serial_clock(void)
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{
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return gd->bus_clk / 2;
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_I2C_CLK:
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return get_bus_freq(0) / 2;
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case MXC_ESDHC_CLK:
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return get_bus_freq(0);
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case MXC_DSPI_CLK:
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return get_bus_freq(0) / 2;
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case MXC_UART_CLK:
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return get_bus_freq(0) / 2;
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default:
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printf("Unsupported clock\n");
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}
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return 0;
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}
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@ -0,0 +1,103 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char buf1[32], buf2[32];
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major, minor, ver, i;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts("CPU: Freescale LayerScape ");
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ver = SVR_SOC_VER(svr);
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switch (ver) {
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case SOC_VER_SLS1020:
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puts("SLS1020");
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break;
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case SOC_VER_LS1020:
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puts("LS1020");
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break;
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case SOC_VER_LS1021:
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puts("LS1021");
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break;
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case SOC_VER_LS1022:
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puts("LS1022");
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break;
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default:
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puts("Unknown");
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break;
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}
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if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
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puts("E");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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puts("Clock Configuration:");
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printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
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printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
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printf("DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
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puts("\n");
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/* Display the RCW, so that no one gets confused as to what RCW
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* we're actually using for this boot.
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*/
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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u32 rcw = in_be32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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return 0;
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}
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#endif
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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#ifdef CONFIG_FSL_ESDHC
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/clock.h>
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#include <linux/ctype.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include <tsec.h>
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DECLARE_GLOBAL_DATA_PTR;
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void ft_fixup_enet_phy_connect_type(void *fdt)
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{
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struct eth_device *dev;
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struct tsec_private *priv;
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const char *enet_path, *phy_path;
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char enet[16];
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char phy[16];
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int phy_node;
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int i = 0;
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int enet_id = 0;
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uint32_t ph;
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while ((dev = eth_get_dev_by_index(i++)) != NULL) {
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if (strstr(dev->name, "eTSEC1"))
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enet_id = 0;
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else if (strstr(dev->name, "eTSEC2"))
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enet_id = 1;
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else if (strstr(dev->name, "eTSEC3"))
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enet_id = 2;
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else
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continue;
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priv = dev->priv;
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if (priv->flags & TSEC_SGMII)
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continue;
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sprintf(enet, "ethernet%d", enet_id);
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enet_path = fdt_get_alias(fdt, enet);
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if (!enet_path)
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continue;
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sprintf(phy, "enet%d_rgmii_phy", enet_id);
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phy_path = fdt_get_alias(fdt, phy);
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if (!phy_path)
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continue;
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phy_node = fdt_path_offset(fdt, phy_path);
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if (phy_node < 0)
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continue;
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ph = fdt_create_phandle(fdt, phy_node);
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if (ph)
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do_fixup_by_path_u32(fdt, enet_path,
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"phy-handle", ph, 1);
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do_fixup_by_path(fdt, enet_path, "phy-connection-type",
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phy_string_for_interface(
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PHY_INTERFACE_MODE_RGMII_ID),
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sizeof(phy_string_for_interface(
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PHY_INTERFACE_MODE_RGMII_ID)),
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1);
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}
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}
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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int off;
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int val;
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const char *sysclk_path;
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unsigned long busclk = get_bus_freq(0);
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fdt_fixup_ethernet(blob);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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val = gd->cpu_clk;
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fdt_setprop(blob, off, "clock-frequency", &val, 4);
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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do_fixup_by_prop_u32(blob, "device_type", "soc",
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4, "bus-frequency", busclk / 2, 1);
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ft_fixup_enet_phy_connect_type(blob);
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#ifdef CONFIG_SYS_NS16550
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do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
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"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
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#endif
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sysclk_path = fdt_get_alias(blob, "sysclk");
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if (sysclk_path)
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do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
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CONFIG_SYS_CLK_FREQ, 1);
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do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
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"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
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#if defined(CONFIG_FSL_ESDHC)
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fdt_fixup_esdhc(blob, bd);
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#endif
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/*
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* platform bus clock = system bus clock/2
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* Here busclk = system bus clock
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* We are using the platform bus clock as 1588 Timer reference
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* clock source select
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*/
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do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
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"timer-frequency", busclk / 2, 1);
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/*
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* clock-freq should change to clock-frequency and
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* flexcan-v1.0 should change to p1010-flexcan respectively
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* in the future.
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*/
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do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
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"clock_freq", busclk / 2, 1);
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do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
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"clock-frequency", busclk / 2, 1);
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do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
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"clock-frequency", busclk / 2, 1);
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}
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@ -0,0 +1,120 @@
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include "fsl_ls1_serdes.h"
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#ifdef CONFIG_SYS_FSL_SRDS_1
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static u64 serdes1_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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static u64 serdes2_prtcl_map;
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#endif
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int is_serdes_configured(enum srds_prtcl device)
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{
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u64 ret = 0;
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#ifdef CONFIG_SYS_FSL_SRDS_1
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ret |= (1ULL << device) & serdes1_prtcl_map;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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ret |= (1ULL << device) & serdes2_prtcl_map;
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#endif
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return !!ret;
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}
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 cfg = in_be32(&gur->rcwsr[4]);
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int i;
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switch (sd) {
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#ifdef CONFIG_SYS_FSL_SRDS_1
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case FSL_SRDS_1:
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cfg &= RCWSR4_SRDS1_PRTCL_MASK;
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cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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case FSL_SRDS_2:
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cfg &= RCWSR4_SRDS2_PRTCL_MASK;
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cfg >>= RCWSR4_SRDS2_PRTCL_SHIFT;
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break;
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#endif
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default:
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printf("invalid SerDes%d\n", sd);
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break;
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}
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/* Is serdes enabled at all? */
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if (unlikely(cfg == 0))
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return -ENODEV;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_get_prtcl(sd, cfg, i) == device)
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return i;
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}
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return -ENODEV;
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}
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u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
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{
|
||||
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
|
||||
u64 serdes_prtcl_map = 0;
|
||||
u32 cfg;
|
||||
int lane;
|
||||
|
||||
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
|
||||
cfg >>= sd_prctl_shift;
|
||||
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
|
||||
|
||||
if (!is_serdes_prtcl_valid(sd, cfg))
|
||||
printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
|
||||
|
||||
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
|
||||
enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
|
||||
|
||||
serdes_prtcl_map |= (1ULL << lane_prtcl);
|
||||
}
|
||||
|
||||
return serdes_prtcl_map;
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_1
|
||||
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR,
|
||||
RCWSR4_SRDS1_PRTCL_MASK,
|
||||
RCWSR4_SRDS1_PRTCL_SHIFT);
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_FSL_SRDS_2
|
||||
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
|
||||
CONFIG_SYS_FSL_SERDES_ADDR +
|
||||
FSL_SRDS_2 * 0x1000,
|
||||
RCWSR4_SRDS2_PRTCL_MASK,
|
||||
RCWSR4_SRDS2_PRTCL_SHIFT);
|
||||
#endif
|
||||
}
|
||||
|
||||
const char *serdes_clock_to_string(u32 clock)
|
||||
{
|
||||
switch (clock) {
|
||||
case SRDS_PLLCR0_RFCK_SEL_100:
|
||||
return "100";
|
||||
case SRDS_PLLCR0_RFCK_SEL_125:
|
||||
return "125";
|
||||
default:
|
||||
return "100";
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_LS1_SERDES_H
|
||||
#define __FSL_LS1_SERDES_H
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl);
|
||||
int serdes_lane_enabled(int lane);
|
||||
#endif /* __FSL_LS1_SERDES_H */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/fsl_serdes.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
|
||||
static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
|
||||
[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1},
|
||||
[0x10] = {PCIE1, SATA1, PCIE2, PCIE2},
|
||||
[0x20] = {PCIE1, SGMII_TSEC1, PCIE2, SGMII_TSEC2},
|
||||
[0x30] = {PCIE1, SATA1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x40] = {PCIE1, PCIE1, SATA1, SGMII_TSEC2},
|
||||
[0x50] = {PCIE1, PCIE1, PCIE2, SGMII_TSEC2},
|
||||
[0x60] = {PCIE1, PCIE1, SGMII_TSEC1, SGMII_TSEC2},
|
||||
[0x70] = {PCIE1, SATA1, PCIE2, SGMII_TSEC2},
|
||||
[0x80] = {PCIE2, PCIE2, PCIE2, PCIE2},
|
||||
};
|
||||
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
||||
{
|
||||
return serdes_cfg_tbl[cfg][lane];
|
||||
}
|
||||
|
||||
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
||||
if (serdes_cfg_tbl[prtcl][i] != NONE)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <div64.h>
|
||||
#include <asm/arch/immap_ls102xa.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* This function is intended for SHORT delays only.
|
||||
* It will overflow at around 10 seconds @ 400MHz,
|
||||
* or 20 seconds @ 200MHz.
|
||||
*/
|
||||
unsigned long usec2ticks(unsigned long usec)
|
||||
{
|
||||
ulong ticks;
|
||||
|
||||
if (usec < 1000)
|
||||
ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
|
||||
else
|
||||
ticks = ((usec / 10) * (get_tbclk() / 100000));
|
||||
|
||||
return ticks;
|
||||
}
|
||||
|
||||
static inline unsigned long long tick_to_time(unsigned long long tick)
|
||||
{
|
||||
unsigned long freq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
tick *= CONFIG_SYS_HZ;
|
||||
do_div(tick, freq);
|
||||
|
||||
return tick;
|
||||
}
|
||||
|
||||
static inline unsigned long long us_to_tick(unsigned long long usec)
|
||||
{
|
||||
unsigned long freq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
usec = usec * freq + 999999;
|
||||
do_div(usec, 1000000);
|
||||
|
||||
return usec;
|
||||
}
|
||||
|
||||
int timer_init(void)
|
||||
{
|
||||
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
|
||||
unsigned long ctrl, val, freq;
|
||||
|
||||
/* Enable System Counter */
|
||||
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);
|
||||
|
||||
freq = GENERIC_TIMER_CLK;
|
||||
asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
|
||||
|
||||
/* Set PL1 Physical Timer Ctrl */
|
||||
ctrl = ARCH_TIMER_CTRL_ENABLE;
|
||||
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
|
||||
|
||||
/* Set PL1 Physical Comp Value */
|
||||
val = TIMER_COMP_VAL;
|
||||
asm("mcrr p15, 2, %Q0, %R0, c14" : : "r" (val));
|
||||
|
||||
gd->arch.tbl = 0;
|
||||
gd->arch.tbu = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long long get_ticks(void)
|
||||
{
|
||||
unsigned long long now;
|
||||
|
||||
asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
|
||||
|
||||
gd->arch.tbl = (unsigned long)(now & 0xffffffff);
|
||||
gd->arch.tbu = (unsigned long)(now >> 32);
|
||||
|
||||
return now;
|
||||
}
|
||||
|
||||
unsigned long get_timer_masked(void)
|
||||
{
|
||||
return tick_to_time(get_ticks());
|
||||
}
|
||||
|
||||
unsigned long get_timer(ulong base)
|
||||
{
|
||||
return get_timer_masked() - base;
|
||||
}
|
||||
|
||||
/* delay x useconds and preserve advance timstamp value */
|
||||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long long start;
|
||||
unsigned long tmo;
|
||||
|
||||
start = get_ticks(); /* get current timestamp */
|
||||
tmo = us_to_tick(usec); /* convert usecs to ticks */
|
||||
|
||||
while ((get_ticks() - start) < tmo)
|
||||
; /* loop till time has passed */
|
||||
}
|
||||
|
||||
/*
|
||||
* This function is derived from PowerPC code (timebase clock frequency).
|
||||
* On ARM it returns the number of timer ticks per second.
|
||||
*/
|
||||
unsigned long get_tbclk(void)
|
||||
{
|
||||
unsigned long freq;
|
||||
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_CLOCK_H_
|
||||
#define __ASM_ARCH_LS102XA_CLOCK_H_
|
||||
|
||||
#include <common.h>
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_UART_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_I2C_CLK,
|
||||
MXC_DSPI_CLK,
|
||||
};
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright 2014, Freescale Semiconductor
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARMV7_LS102XA_CONFIG_
|
||||
#define _ASM_ARMV7_LS102XA_CONFIG_
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
|
||||
#define OCRAM_BASE_ADDR 0x10000000
|
||||
#define OCRAM_SIZE 0x00020000
|
||||
|
||||
#define CONFIG_SYS_IMMR 0x01000000
|
||||
|
||||
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
|
||||
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
|
||||
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
|
||||
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
|
||||
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
|
||||
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
|
||||
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
|
||||
|
||||
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
|
||||
#define CONFIG_SYS_TSEC2_OFFSET 0x01d50000
|
||||
#define CONFIG_SYS_TSEC3_OFFSET 0x01d90000
|
||||
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
|
||||
|
||||
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
|
||||
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
|
||||
|
||||
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)
|
||||
|
||||
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
|
||||
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
|
||||
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
|
||||
|
||||
#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
|
||||
|
||||
#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
|
||||
#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
|
||||
|
||||
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
|
||||
|
||||
#ifdef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_FSL_DDR_BE
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3
|
||||
#define CONFIG_SYS_FSL_DDR
|
||||
#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
||||
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_IFC_BE
|
||||
#define CONFIG_SYS_FSL_ESDHC_BE
|
||||
#define CONFIG_SYS_FSL_WDOG_BE
|
||||
#define CONFIG_SYS_FSL_DSPI_BE
|
||||
#define CONFIG_SYS_FSL_QSPI_BE
|
||||
|
||||
#define CONFIG_SYS_FSL_SRDS_1
|
||||
|
||||
#ifdef CONFIG_LS102XA
|
||||
#define CONFIG_MAX_CPUS 2
|
||||
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#else
|
||||
#error SoC not defined
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
SATA1,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
};
|
||||
|
||||
enum srds {
|
||||
FSL_SRDS_1 = 0,
|
||||
FSL_SRDS_2 = 1,
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
void fsl_serdes_init(void);
|
||||
const char *serdes_clock_to_string(u32 clock);
|
||||
|
||||
int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
|
||||
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
||||
|
|
@ -0,0 +1,493 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_LS102XA_IMMAP_H_
|
||||
#define __ASM_ARCH_LS102XA_IMMAP_H_
|
||||
|
||||
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
|
||||
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
|
||||
#define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
|
||||
#define IS_E_PROCESSOR(svr) (svr & 0x80000)
|
||||
|
||||
#define SOC_VER_SLS1020 0x00
|
||||
#define SOC_VER_LS1020 0x10
|
||||
#define SOC_VER_LS1021 0x11
|
||||
#define SOC_VER_LS1022 0x12
|
||||
|
||||
#define RCWSR0_SYS_PLL_RAT_SHIFT 25
|
||||
#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
|
||||
#define RCWSR0_MEM_PLL_RAT_SHIFT 16
|
||||
#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
|
||||
|
||||
#define RCWSR4_SRDS1_PRTCL_SHIFT 24
|
||||
#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
|
||||
|
||||
#define TIMER_COMP_VAL 0xffffffff
|
||||
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
|
||||
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)
|
||||
|
||||
struct sys_info {
|
||||
unsigned long freq_processor[CONFIG_MAX_CPUS];
|
||||
unsigned long freq_systembus;
|
||||
unsigned long freq_ddrbus;
|
||||
unsigned long freq_localbus;
|
||||
};
|
||||
|
||||
/* Device Configuration and Pin Control */
|
||||
struct ccsr_gur {
|
||||
u32 porsr1; /* POR status 1 */
|
||||
u32 porsr2; /* POR status 2 */
|
||||
u8 res_008[0x20-0x8];
|
||||
u32 gpporcr1; /* General-purpose POR configuration */
|
||||
u32 gpporcr2;
|
||||
u32 dcfg_fusesr; /* Fuse status register */
|
||||
u8 res_02c[0x70-0x2c];
|
||||
u32 devdisr; /* Device disable control */
|
||||
u32 devdisr2; /* Device disable control 2 */
|
||||
u32 devdisr3; /* Device disable control 3 */
|
||||
u32 devdisr4; /* Device disable control 4 */
|
||||
u32 devdisr5; /* Device disable control 5 */
|
||||
u8 res_084[0x94-0x84];
|
||||
u32 coredisru; /* uppper portion for support of 64 cores */
|
||||
u32 coredisrl; /* lower portion for support of 64 cores */
|
||||
u8 res_09c[0xa4-0x9c];
|
||||
u32 svr; /* System version */
|
||||
u8 res_0a8[0xb0-0xa8];
|
||||
u32 rstcr; /* Reset control */
|
||||
u32 rstrqpblsr; /* Reset request preboot loader status */
|
||||
u8 res_0b8[0xc0-0xb8];
|
||||
u32 rstrqmr1; /* Reset request mask */
|
||||
u8 res_0c4[0xc8-0xc4];
|
||||
u32 rstrqsr1; /* Reset request status */
|
||||
u8 res_0cc[0xd4-0xcc];
|
||||
u32 rstrqwdtmrl; /* Reset request WDT mask */
|
||||
u8 res_0d8[0xdc-0xd8];
|
||||
u32 rstrqwdtsrl; /* Reset request WDT status */
|
||||
u8 res_0e0[0xe4-0xe0];
|
||||
u32 brrl; /* Boot release */
|
||||
u8 res_0e8[0x100-0xe8];
|
||||
u32 rcwsr[16]; /* Reset control word status */
|
||||
u8 res_140[0x200-0x140];
|
||||
u32 scratchrw[4]; /* Scratch Read/Write */
|
||||
u8 res_210[0x300-0x210];
|
||||
u32 scratchw1r[4]; /* Scratch Read (Write once) */
|
||||
u8 res_310[0x400-0x310];
|
||||
u32 crstsr;
|
||||
u8 res_404[0x550-0x404];
|
||||
u32 sataliodnr;
|
||||
u8 res_554[0x604-0x554];
|
||||
u32 pamubypenr;
|
||||
u32 dmacr1;
|
||||
u8 res_60c[0x740-0x60c]; /* add more registers when needed */
|
||||
u32 tp_ityp[64]; /* Topology Initiator Type Register */
|
||||
struct {
|
||||
u32 upper;
|
||||
u32 lower;
|
||||
} tp_cluster[1]; /* Core Cluster n Topology Register */
|
||||
u8 res_848[0xe60-0x848];
|
||||
u32 ddrclkdr;
|
||||
u8 res_e60[0xe68-0xe64];
|
||||
u32 ifcclkdr;
|
||||
u8 res_e68[0xe80-0xe6c];
|
||||
u32 sdhcpcr;
|
||||
};
|
||||
|
||||
#define SCFG_SCFGREVCR_REV 0xffffffff
|
||||
#define SCFG_SCFGREVCR_NOREV 0
|
||||
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
|
||||
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
|
||||
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
|
||||
|
||||
/* Supplemental Configuration Unit */
|
||||
struct ccsr_scfg {
|
||||
u32 dpslpcr;
|
||||
u32 resv0[2];
|
||||
u32 etsecclkdpslpcr;
|
||||
u32 resv1[5];
|
||||
u32 fuseovrdcr;
|
||||
u32 pixclkcr;
|
||||
u32 resv2[5];
|
||||
u32 spimsicr;
|
||||
u32 resv3[6];
|
||||
u32 pex1pmwrcr;
|
||||
u32 pex1pmrdsr;
|
||||
u32 resv4[3];
|
||||
u32 usb3prm1cr;
|
||||
u32 usb4prm2cr;
|
||||
u32 pex1rdmsgpldlsbsr;
|
||||
u32 pex1rdmsgpldmsbsr;
|
||||
u32 pex2rdmsgpldlsbsr;
|
||||
u32 pex2rdmsgpldmsbsr;
|
||||
u32 pex1rdmmsgrqsr;
|
||||
u32 pex2rdmmsgrqsr;
|
||||
u32 spimsiclrcr;
|
||||
u32 pex1mscportsr;
|
||||
u32 pex2mscportsr;
|
||||
u32 pex2pmwrcr;
|
||||
u32 resv5[24];
|
||||
u32 mac1_streamid;
|
||||
u32 mac2_streamid;
|
||||
u32 mac3_streamid;
|
||||
u32 pex1_streamid;
|
||||
u32 pex2_streamid;
|
||||
u32 dma_streamid;
|
||||
u32 sata_streamid;
|
||||
u32 usb3_streamid;
|
||||
u32 qe_streamid;
|
||||
u32 sdhc_streamid;
|
||||
u32 adma_streamid;
|
||||
u32 letechsftrstcr;
|
||||
u32 core0_sft_rst;
|
||||
u32 core1_sft_rst;
|
||||
u32 resv6[1];
|
||||
u32 usb_hi_addr;
|
||||
u32 etsecclkadjcr;
|
||||
u32 sai_clk;
|
||||
u32 resv7[1];
|
||||
u32 dcu_streamid;
|
||||
u32 usb2_streamid;
|
||||
u32 ftm_reset;
|
||||
u32 altcbar;
|
||||
u32 qspi_cfg;
|
||||
u32 pmcintecr;
|
||||
u32 pmcintlecr;
|
||||
u32 pmcintsr;
|
||||
u32 qos1;
|
||||
u32 qos2;
|
||||
u32 qos3;
|
||||
u32 cci_cfg;
|
||||
u32 resv8[1];
|
||||
u32 etsecdmamcr;
|
||||
u32 usb3prm3cr;
|
||||
u32 resv9[1];
|
||||
u32 debug_streamid;
|
||||
u32 resv10[5];
|
||||
u32 snpcnfgcr;
|
||||
u32 resv11[1];
|
||||
u32 intpcr;
|
||||
u32 resv12[20];
|
||||
u32 scfgrevcr;
|
||||
u32 coresrencr;
|
||||
u32 pex2pmrdsr;
|
||||
u32 ddrc1cr;
|
||||
u32 ddrc2cr;
|
||||
u32 ddrc3cr;
|
||||
u32 ddrc4cr;
|
||||
u32 ddrgcr;
|
||||
u32 resv13[120];
|
||||
u32 qeioclkcr;
|
||||
u32 etsecmcr;
|
||||
u32 sdhciovserlcr;
|
||||
u32 resv14[61];
|
||||
u32 sparecr;
|
||||
};
|
||||
|
||||
/* Clocking */
|
||||
struct ccsr_clk {
|
||||
struct {
|
||||
u32 clkcncsr; /* core cluster n clock control status */
|
||||
u8 res_004[0x1c];
|
||||
} clkcsr[2];
|
||||
u8 res_040[0x7c0]; /* 0x100 */
|
||||
struct {
|
||||
u32 pllcngsr;
|
||||
u8 res_804[0x1c];
|
||||
} pllcgsr[2];
|
||||
u8 res_840[0x1c0];
|
||||
u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
|
||||
u8 res_a04[0x1fc];
|
||||
u32 pllpgsr; /* 0xc00 Platform PLL General Status */
|
||||
u8 res_c04[0x1c];
|
||||
u32 plldgsr; /* 0xc20 DDR PLL General Status */
|
||||
u8 res_c24[0x3dc];
|
||||
};
|
||||
|
||||
/* System Counter */
|
||||
struct sctr_regs {
|
||||
u32 cntcr;
|
||||
u32 cntsr;
|
||||
u32 cntcv1;
|
||||
u32 cntcv2;
|
||||
u32 resv1[4];
|
||||
u32 cntfid0;
|
||||
u32 cntfid1;
|
||||
u32 resv2[1002];
|
||||
u32 counterid[12];
|
||||
};
|
||||
|
||||
#define MAX_SERDES 1
|
||||
#define SRDS_MAX_LANES 4
|
||||
#define SRDS_MAX_BANK 2
|
||||
|
||||
#define SRDS_RSTCTL_RST 0x80000000
|
||||
#define SRDS_RSTCTL_RSTDONE 0x40000000
|
||||
#define SRDS_RSTCTL_RSTERR 0x20000000
|
||||
#define SRDS_RSTCTL_SWRST 0x10000000
|
||||
#define SRDS_RSTCTL_SDEN 0x00000020
|
||||
#define SRDS_RSTCTL_SDRST_B 0x00000040
|
||||
#define SRDS_RSTCTL_PLLRST_B 0x00000080
|
||||
#define SRDS_PLLCR0_POFF 0x80000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
|
||||
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
|
||||
#define SRDS_PLLCR0_PLL_LCK 0x00800000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
|
||||
#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
|
||||
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
|
||||
|
||||
struct ccsr_serdes {
|
||||
struct {
|
||||
u32 rstctl; /* Reset Control Register */
|
||||
|
||||
u32 pllcr0; /* PLL Control Register 0 */
|
||||
|
||||
u32 pllcr1; /* PLL Control Register 1 */
|
||||
u32 res_0c; /* 0x00c */
|
||||
u32 pllcr3;
|
||||
u32 pllcr4;
|
||||
u8 res_18[0x20-0x18];
|
||||
} bank[2];
|
||||
u8 res_40[0x90-0x40];
|
||||
u32 srdstcalcr; /* 0x90 TX Calibration Control */
|
||||
u8 res_94[0xa0-0x94];
|
||||
u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
|
||||
u8 res_a4[0xb0-0xa4];
|
||||
u32 srdsgr0; /* 0xb0 General Register 0 */
|
||||
u8 res_b4[0xe0-0xb4];
|
||||
u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
|
||||
u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
|
||||
u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
|
||||
u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
|
||||
u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
|
||||
u8 res_f4[0x100-0xf4];
|
||||
struct {
|
||||
u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
|
||||
u8 res_104[0x120-0x104];
|
||||
} srdslnpssr[4];
|
||||
u8 res_180[0x300-0x180];
|
||||
u32 srdspexeqcr;
|
||||
u32 srdspexeqpcr[11];
|
||||
u8 res_330[0x400-0x330];
|
||||
u32 srdspexapcr;
|
||||
u8 res_404[0x440-0x404];
|
||||
u32 srdspexbpcr;
|
||||
u8 res_444[0x800-0x444];
|
||||
struct {
|
||||
u32 gcr0; /* 0x800 General Control Register 0 */
|
||||
u32 gcr1; /* 0x804 General Control Register 1 */
|
||||
u32 gcr2; /* 0x808 General Control Register 2 */
|
||||
u32 sscr0;
|
||||
u32 recr0; /* 0x810 Receive Equalization Control */
|
||||
u32 recr1;
|
||||
u32 tecr0; /* 0x818 Transmit Equalization Control */
|
||||
u32 sscr1;
|
||||
u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
|
||||
u8 res_824[0x83c-0x824];
|
||||
u32 tcsr3;
|
||||
} lane[4]; /* Lane A, B, C, D, E, F, G, H */
|
||||
u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
|
||||
};
|
||||
|
||||
#define DDR_SDRAM_CFG 0x470c0008
|
||||
#define DDR_CS0_BNDS 0x008000bf
|
||||
#define DDR_CS0_CONFIG 0x80014302
|
||||
#define DDR_TIMING_CFG_0 0x50550004
|
||||
#define DDR_TIMING_CFG_1 0xbcb38c56
|
||||
#define DDR_TIMING_CFG_2 0x0040d120
|
||||
#define DDR_TIMING_CFG_3 0x010e1000
|
||||
#define DDR_TIMING_CFG_4 0x00000001
|
||||
#define DDR_TIMING_CFG_5 0x03401400
|
||||
#define DDR_SDRAM_CFG_2 0x00401010
|
||||
#define DDR_SDRAM_MODE 0x00061c60
|
||||
#define DDR_SDRAM_MODE_2 0x00180000
|
||||
#define DDR_SDRAM_INTERVAL 0x18600618
|
||||
#define DDR_DDR_WRLVL_CNTL 0x8655f605
|
||||
#define DDR_DDR_WRLVL_CNTL_2 0x05060607
|
||||
#define DDR_DDR_WRLVL_CNTL_3 0x05050505
|
||||
#define DDR_DDR_CDR1 0x80040000
|
||||
#define DDR_DDR_CDR2 0x00000001
|
||||
#define DDR_SDRAM_CLK_CNTL 0x02000000
|
||||
#define DDR_DDR_ZQ_CNTL 0x89080600
|
||||
#define DDR_CS0_CONFIG_2 0
|
||||
#define DDR_SDRAM_CFG_MEM_EN 0x80000000
|
||||
|
||||
/* DDR memory controller registers */
|
||||
struct ccsr_ddr {
|
||||
u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
|
||||
u32 resv1[1];
|
||||
u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
|
||||
u32 resv2[1];
|
||||
u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
|
||||
u32 resv3[1];
|
||||
u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
|
||||
u32 resv4[25];
|
||||
u32 cs0_config; /* Chip Select Configuration */
|
||||
u32 cs1_config; /* Chip Select Configuration */
|
||||
u32 cs2_config; /* Chip Select Configuration */
|
||||
u32 cs3_config; /* Chip Select Configuration */
|
||||
u32 resv5[12];
|
||||
u32 cs0_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs1_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs2_config_2; /* Chip Select Configuration 2 */
|
||||
u32 cs3_config_2; /* Chip Select Configuration 2 */
|
||||
u32 resv6[12];
|
||||
u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
|
||||
u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
|
||||
u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
|
||||
u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
|
||||
u32 sdram_cfg; /* SDRAM Control Configuration */
|
||||
u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
|
||||
u32 sdram_mode; /* SDRAM Mode Configuration */
|
||||
u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
|
||||
u32 sdram_md_cntl; /* SDRAM Mode Control */
|
||||
u32 sdram_interval; /* SDRAM Interval Configuration */
|
||||
u32 sdram_data_init; /* SDRAM Data initialization */
|
||||
u32 resv7[1];
|
||||
u32 sdram_clk_cntl; /* SDRAM Clock Control */
|
||||
u32 resv8[5];
|
||||
u32 init_addr; /* training init addr */
|
||||
u32 init_ext_addr; /* training init extended addr */
|
||||
u32 resv9[4];
|
||||
u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
|
||||
u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
|
||||
u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
|
||||
u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
|
||||
u32 ddr_zq_cntl; /* ZQ calibration control*/
|
||||
u32 ddr_wrlvl_cntl; /* write leveling control*/
|
||||
u32 resv10[1];
|
||||
u32 ddr_sr_cntr; /* self refresvh counter */
|
||||
u32 ddr_sdram_rcw_1; /* Control Words 1 */
|
||||
u32 ddr_sdram_rcw_2; /* Control Words 2 */
|
||||
u32 resv11[2];
|
||||
u32 ddr_wrlvl_cntl_2; /* write leveling control 2 */
|
||||
u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */
|
||||
u32 resv12[2];
|
||||
u32 ddr_sdram_rcw_3; /* Control Words 3 */
|
||||
u32 ddr_sdram_rcw_4; /* Control Words 4 */
|
||||
u32 ddr_sdram_rcw_5; /* Control Words 5 */
|
||||
u32 ddr_sdram_rcw_6; /* Control Words 6 */
|
||||
u32 resv13[20];
|
||||
u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
|
||||
u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
|
||||
u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
|
||||
u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
|
||||
u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
|
||||
u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
|
||||
u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
|
||||
u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
|
||||
u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
|
||||
u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
|
||||
u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
|
||||
u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
|
||||
u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
|
||||
u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
|
||||
u32 resv14[4];
|
||||
u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
|
||||
u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */
|
||||
u32 resv15[2];
|
||||
u32 sdram_cfg_3; /* SDRAM Control Configuration 3 */
|
||||
u32 resv16[15];
|
||||
u32 deskew_cntl; /* SDRAM Deskew Control */
|
||||
u32 resv17[545];
|
||||
u32 ddr_dsr1; /* Debug Status 1 */
|
||||
u32 ddr_dsr2; /* Debug Status 2 */
|
||||
u32 ddr_cdr1; /* Control Driver 1 */
|
||||
u32 ddr_cdr2; /* Control Driver 2 */
|
||||
u32 resv18[50];
|
||||
u32 ip_rev1; /* IP Block Revision 1 */
|
||||
u32 ip_rev2; /* IP Block Revision 2 */
|
||||
u32 eor; /* Enhanced Optimization Register */
|
||||
u32 resv19[63];
|
||||
u32 mtcr; /* Memory Test Control Register */
|
||||
u32 resv20[7];
|
||||
u32 mtp1; /* Memory Test Pattern 1 */
|
||||
u32 mtp2; /* Memory Test Pattern 2 */
|
||||
u32 mtp3; /* Memory Test Pattern 3 */
|
||||
u32 mtp4; /* Memory Test Pattern 4 */
|
||||
u32 mtp5; /* Memory Test Pattern 5 */
|
||||
u32 mtp6; /* Memory Test Pattern 6 */
|
||||
u32 mtp7; /* Memory Test Pattern 7 */
|
||||
u32 mtp8; /* Memory Test Pattern 8 */
|
||||
u32 mtp9; /* Memory Test Pattern 9 */
|
||||
u32 mtp10; /* Memory Test Pattern 10 */
|
||||
u32 resv21[6];
|
||||
u32 ddr_mt_st_ext_addr; /* Memory Test Start Extended Address */
|
||||
u32 ddr_mt_st_addr; /* Memory Test Start Address */
|
||||
u32 ddr_mt_end_ext_addr; /* Memory Test End Extended Address */
|
||||
u32 ddr_mt_end_addr; /* Memory Test End Address */
|
||||
u32 resv22[36];
|
||||
u32 data_err_inject_hi; /* Data Path Err Injection Mask High */
|
||||
u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */
|
||||
u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */
|
||||
u32 resv23[5];
|
||||
u32 capture_data_hi; /* Data Path Read Capture High */
|
||||
u32 capture_data_lo; /* Data Path Read Capture Low */
|
||||
u32 capture_ecc; /* Data Path Read Capture ECC */
|
||||
u32 resv24[5];
|
||||
u32 err_detect; /* Error Detect */
|
||||
u32 err_disable; /* Error Disable */
|
||||
u32 err_int_en;
|
||||
u32 capture_attributes; /* Error Attrs Capture */
|
||||
u32 capture_address; /* Error Addr Capture */
|
||||
u32 capture_ext_address; /* Error Extended Addr Capture */
|
||||
u32 err_sbe; /* Single-Bit ECC Error Management */
|
||||
u32 resv25[105];
|
||||
};
|
||||
|
||||
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
|
||||
#define CCI400_CTRLORD_EN_BARRIER 0
|
||||
|
||||
/* CCI-400 registers */
|
||||
struct ccsr_cci400 {
|
||||
u32 ctrl_ord; /* Control Override */
|
||||
u32 spec_ctrl; /* Speculation Control */
|
||||
u32 secure_access; /* Secure Access */
|
||||
u32 status; /* Status */
|
||||
u32 impr_err; /* Imprecise Error */
|
||||
u8 res_14[0x100 - 0x14];
|
||||
u32 pmcr; /* Performance Monitor Control */
|
||||
u8 res_104[0xfd0 - 0x104];
|
||||
u32 pid[8]; /* Peripheral ID */
|
||||
u32 cid[4]; /* Component ID */
|
||||
struct {
|
||||
u32 snoop_ctrl; /* Snoop Control */
|
||||
u32 sha_ord; /* Shareable Override */
|
||||
u8 res_1008[0x1100 - 0x1008];
|
||||
u32 rc_qos_ord; /* read channel QoS Value Override */
|
||||
u32 wc_qos_ord; /* read channel QoS Value Override */
|
||||
u8 res_1108[0x110c - 0x1108];
|
||||
u32 qos_ctrl; /* QoS Control */
|
||||
u32 max_ot; /* Max OT */
|
||||
u8 res_1114[0x1130 - 0x1114];
|
||||
u32 target_lat; /* Target Latency */
|
||||
u32 latency_regu; /* Latency Regulation */
|
||||
u32 qos_range; /* QoS Range */
|
||||
u8 res_113c[0x2000 - 0x113c];
|
||||
} slave[5]; /* Slave Interface */
|
||||
u8 res_6000[0x9004 - 0x6000];
|
||||
u32 cycle_counter; /* Cycle counter */
|
||||
u32 count_ctrl; /* Count Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_9010[0xa000 - 0x9010];
|
||||
struct {
|
||||
u32 event_select; /* Event Select */
|
||||
u32 event_count; /* Event Count */
|
||||
u32 counter_ctrl; /* Counter Control */
|
||||
u32 overflow_status; /* Overflow Flag Status */
|
||||
u8 res_a010[0xb000 - 0xa010];
|
||||
} pcounter[4]; /* Performance Counter */
|
||||
u8 res_e004[0x10000 - 0xe004];
|
||||
};
|
||||
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_IMX_REGS_H__
|
||||
#define __ASM_ARCH_IMX_REGS_H__
|
||||
|
||||
#define I2C_QUIRK_REG /* enable 8-bit driver */
|
||||
|
||||
#ifdef CONFIG_LPUART_32B_REG
|
||||
struct lpuart_fsl {
|
||||
u32 baud;
|
||||
u32 stat;
|
||||
u32 ctrl;
|
||||
u32 data;
|
||||
u32 match;
|
||||
u32 modir;
|
||||
u32 fifo;
|
||||
u32 water;
|
||||
};
|
||||
#else
|
||||
struct lpuart_fsl {
|
||||
u8 ubdh;
|
||||
u8 ubdl;
|
||||
u8 uc1;
|
||||
u8 uc2;
|
||||
u8 us1;
|
||||
u8 us2;
|
||||
u8 uc3;
|
||||
u8 ud;
|
||||
u8 uma1;
|
||||
u8 uma2;
|
||||
u8 uc4;
|
||||
u8 uc5;
|
||||
u8 ued;
|
||||
u8 umodem;
|
||||
u8 uir;
|
||||
u8 reserved;
|
||||
u8 upfifo;
|
||||
u8 ucfifo;
|
||||
u8 usfifo;
|
||||
u8 utwfifo;
|
||||
u8 utcfifo;
|
||||
u8 urwfifo;
|
||||
u8 urcfifo;
|
||||
u8 rsvd[28];
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_IMX_REGS_H__ */
|
||||
|
|
@ -23,4 +23,8 @@
|
|||
#include <asm/arch-fsl-lsch3/config.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LS102XA
|
||||
#include <asm/arch/config.h>
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -376,7 +376,12 @@ out:
|
|||
return retval;
|
||||
}
|
||||
|
||||
#elif !defined(readb)
|
||||
#else
|
||||
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
|
||||
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
|
||||
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
|
||||
|
||||
#if !defined(readb)
|
||||
|
||||
#define readb(addr) (__readwrite_bug("readb"),0)
|
||||
#define readw(addr) (__readwrite_bug("readw"),0)
|
||||
|
|
@ -389,6 +394,7 @@ out:
|
|||
|
||||
#define check_signature(io,sig,len) (0)
|
||||
|
||||
#endif
|
||||
#endif /* __mem_pci */
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
|
||||
obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
|
||||
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610))
|
||||
ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa))
|
||||
obj-y += imx_watchdog.o
|
||||
endif
|
||||
obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
|
||||
|
|
|
|||
Loading…
Reference in New Issue