mpc5200: Add a4m2k board port
This patch adds the a4m2k MPC5200B board port. Its a derivate of the a3m071 board with only minor changes. Additionally this patch includes some clean-up changes: - Remove I2C support from a3m071 as its unused - Fix/enhance default env variables - Fix some comments - Add newly introduced CONFIG_SPL_TARGET to automatically build "u-boot-img.bin" - Fix dtb patching in READ desciption for SPL Linux booting: "fdt chosen" needs to get called to patch/create the chosen node. - Add missing call to spl_board_init(): Define CONFIG_SPL_BOARD_INIT so that spl_board_init() will get called in the SPL version. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
Wolfgang Denk
parent
b4dc0bddbf
commit
d4451d3503
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@ -397,6 +397,7 @@ Ricardo Ribalda <ricardo.ribalda@uam.es>
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Stefan Roese <sr@denx.de>
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a3m071 MPC5200
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a4m2k MPC5200
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P3M7448 MPC7448
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@ -62,7 +62,7 @@ the following command:
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All this can be integrated into an environment command:
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=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \
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fdt addr 1800000;fdt boardsetup;erase fc060000 fc07ffff; \
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fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc060000 fc07ffff; \
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cp.b 1800000 fc060000 10000'
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=> saveenv
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@ -24,10 +24,15 @@
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <miiphy.h>
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#include <linux/compiler.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#ifdef CONFIG_A4M2K
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#include "is46r16320d.h"
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#else
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#include "mt46v16m16-75.h"
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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@ -63,6 +68,12 @@ static void sdram_start(int hi_addr)
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/* normal operation */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
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/*
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* Wait a short while for the DLL to lock before accessing
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* the SDRAM
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*/
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udelay(100);
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}
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#endif
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@ -157,12 +168,6 @@ static void get_revisions(int *failsavelevel, int *digiboardversion,
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struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
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u8 val;
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/*
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* Figure out failsavelevel
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* see ticket dsvk#59
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*/
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*failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
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/* read digitalboard-version from TMR[2..4] */
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val = 0;
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val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
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@ -170,6 +175,17 @@ static void get_revisions(int *failsavelevel, int *digiboardversion,
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val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
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*digiboardversion = val;
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/*
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* A4M2K only supports digiboardversion. No failsavelevel and
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* fpgaversion here.
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*/
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#if !defined(CONFIG_A4M2K)
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/*
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* Figure out failsavelevel
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* see ticket dsvk#59
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*/
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*failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
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if (*digiboardversion == 0) {
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*failsavelevel = 1; /* digiboard-version ok */
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@ -183,6 +199,7 @@ static void get_revisions(int *failsavelevel, int *digiboardversion,
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if (*fpgaversion == 1)
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*failsavelevel = 2; /* fpga-version ok */
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}
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#endif
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}
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/*
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@ -196,6 +213,11 @@ void spl_board_init(void)
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struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
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struct mpc5xxx_mmap_ctl *mm =
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(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
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#if defined(CONFIG_A4M2K)
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/* enable CS3 and CS5 (FPGA) */
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setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
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#else
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int digiboardversion;
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int failsavelevel;
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int fpgaversion;
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@ -219,6 +241,7 @@ void spl_board_init(void)
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/* And write new value back to register */
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out_be32(&mm->ipbi_ws_ctrl, val);
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#endif
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/*
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* No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
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@ -234,6 +257,55 @@ void spl_board_init(void)
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*/
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
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#if defined(CONFIG_A4M2K)
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/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
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/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
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gpio->simple_ddr |= 1 << (31 - 15);
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gpio->simple_ddr |= 1 << (31 - 14);
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gpio->simple_ddr |= 1 << (31 - 13);
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gpio->simple_ddr |= 1 << (31 - 12);
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/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 15);
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gpio->simple_gpioe |= 1 << (31 - 14);
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gpio->simple_gpioe |= 1 << (31 - 13);
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gpio->simple_gpioe |= 1 << (31 - 12);
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/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
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/* set PSC2[0..2] (STSLED[0..2]) direction to output */
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gpio->simple_ddr |= 1 << (31 - 27);
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gpio->simple_ddr |= 1 << (31 - 26);
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gpio->simple_ddr |= 1 << (31 - 25);
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/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 27);
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gpio->simple_gpioe |= 1 << (31 - 26);
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gpio->simple_gpioe |= 1 << (31 - 25);
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/* Setup PSC6[2] as MRST2 self reset GPIO output */
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/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
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gpio->simple_ddr |= 1 << (31 - 3);
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/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
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gpio->simple_ode |= 1 << (31 - 3);
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/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
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gpio->simple_dvo |= 1 << (31 - 3);
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/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 3);
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/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
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/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
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gpio->simple_ddr |= 0 << (31 - 2);
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/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
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gpio->simple_gpioe |= 1 << (31 - 2);
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#else
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/* setup GPIOs for status-leds if needed - see ticket #57 */
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if (failsavelevel > 0) {
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/* digiboard-version is OK */
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@ -267,7 +339,7 @@ void spl_board_init(void)
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* already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
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*/
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}
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#endif
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}
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int checkboard(void)
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@ -278,11 +350,16 @@ int checkboard(void)
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get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
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#ifdef CONFIG_A4M2K
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puts("Board: A4M2K\n");
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printf(" digiboard IO version %u\n", digiboardversion);
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#else
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puts("Board: A3M071\n");
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printf("Rev: failsave level %u\n", failsavelevel);
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printf(" digiboard IO version %u\n", digiboardversion);
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if (failsavelevel > 0) /* only if fpga-version red */
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printf(" fpga IO version %u\n", fpgaversion);
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#endif
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return 0;
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}
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@ -0,0 +1,35 @@
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/*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define SDRAM_DDR /* is DDR */
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#if defined(CONFIG_MPC5200)
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/* Settings for XLB = 132 MHz */
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/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
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/* SDRAM Config Standard timing */
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#define SDRAM_MODE 0x008d0000
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#define SDRAM_EMODE 0x40010000
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#define SDRAM_CONTROL 0x70430f00
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#define SDRAM_CONFIG1 0x33622930
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#define SDRAM_CONFIG2 0x46670000
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#define SDRAM_TAPDELAY 0x10000000
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#else
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#error CONFIG_MPC5200 not defined
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#endif
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@ -485,6 +485,7 @@ cmi_mpc5xx powerpc mpc5xx cmi
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PATI powerpc mpc5xx pati mpl
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a3m071 powerpc mpc5xxx a3m071
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a4m072 powerpc mpc5xxx a4m072
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a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K
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BC3450 powerpc mpc5xxx bc3450
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canmb powerpc mpc5xxx
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cm5200 powerpc mpc5xxx
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@ -26,15 +26,22 @@
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#define CONFIG_MPC5200
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#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
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#define CONFIG_A3M071 /* ... on A3M071 board */
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#define CONFIG_MPC5200_DDR /* ... use DDR RAM */
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#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
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#define CONFIG_SPL_TARGET "u-boot-img.bin"
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#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
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#ifdef CONFIG_A4M2K
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#define CONFIG_HOSTNAME a4m2k
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#else
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#define CONFIG_HOSTNAME a3m071
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#endif
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/*
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* Serial console configuration
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*/
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@ -50,9 +57,6 @@
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_REGINFO
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@ -61,7 +65,11 @@
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*/
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#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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/* define for 66MHz speed - undef for 33MHz PCI clock speed */
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
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#else
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#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT
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@ -75,34 +83,11 @@
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#define OF_TBCLK (bd->bi_busfreq / 4)
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#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
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/*
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* I2C configuration
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*/
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
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#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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/*
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* EEPROM configuration
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*/
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*
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* RTC configuration
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*/
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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/*
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* NOR flash configuration
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*/
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#define CONFIG_SYS_FLASH_BASE 0xfc000000
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_FLASH_SIZE 0x02000000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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@ -153,7 +138,11 @@
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*/
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#define CONFIG_MPC5xxx_FEC
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#define CONFIG_MPC5xxx_FEC_MII100
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#ifdef CONFIG_A4M2K
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#define CONFIG_PHY_ADDR 0x01
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#else
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#define CONFIG_PHY_ADDR 0x00
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#endif
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/*
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* GPIO configuration
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@ -166,19 +155,23 @@
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* 2 means fpga ok
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*/
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805
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#else
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/* for failsave-level 0 - full failsave */
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#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
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/* for failsave-level 1 - only digiboard ok */
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#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005
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/* for failsave-level 2 - all ok */
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#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005
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#endif
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/*
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* Configuration matrix
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* MSB LSB
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* failsave 0 0x1005C005 00010000000001011100000001100101 ( full failsave )
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* failsave 1 0x1005C005 00010000000001011100000001100101 ( digib.-ver ok )
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* failsave 2 0x1005C005 00010000000001011100000001100101 ( all ok )
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* failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
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* failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok )
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* failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok )
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* || ||| || | ||| | | | |
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* || ||| || | ||| | | | | bit rev name
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* ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
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@ -254,30 +247,47 @@
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#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
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#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
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#ifdef CONFIG_A4M2K
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/* external MRAM */
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#define CONFIG_SYS_CS1_START 0xf1000000
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#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
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#endif
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#define CONFIG_SYS_CS2_START 0xe0000000
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#define CONFIG_SYS_CS2_SIZE 0x00100000
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/* FPGA slave io (512kiB) - see ticket #66 */
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/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */
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#define CONFIG_SYS_CS3_START 0xE9000000
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_CS3_SIZE 0x00100000
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#else
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#define CONFIG_SYS_CS3_SIZE 0x00080000
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#endif
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/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
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#define CONFIG_SYS_CS3_CFG 0x0032B900
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#ifndef CONFIG_A4M2K
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/* Diagnosis Interface - see ticket #63 */
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#define CONFIG_SYS_CS4_START 0xEA000000
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#define CONFIG_SYS_CS4_SIZE 0x00000001
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/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
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#define CONFIG_SYS_CS4_CFG 0x0002B900
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#endif
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/* FPGA master io (64kiB) - see ticket #66 */
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/* FPGA master io (64kiB / 1MiB) - see ticket #66 */
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#define CONFIG_SYS_CS5_START 0xE8000000
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#ifdef CONFIG_A4M2K
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#define CONFIG_SYS_CS5_SIZE 0x00100000
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#else
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#define CONFIG_SYS_CS5_SIZE 0x00010000
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#endif
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/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
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#define CONFIG_SYS_CS5_CFG 0x0032B900
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#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
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#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
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#define CONFIG_SYS_CS1_CFG 0x0004FB00
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#define CONFIG_SYS_CS1_CFG 0x0008FD00
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#define CONFIG_SYS_CS2_CFG 0x0006F90C
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#else /* for pci_clk = 33 MHz */
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#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
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@ -311,17 +321,25 @@
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#define CONFIG_SYS_OS_BASE 0xfc080000
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#define CONFIG_SYS_FDT_BASE 0xfc060000
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#define xstr(s) str(s)
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#define str(s) #s
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
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"netdev=eth0\0" \
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"verify=no\0" \
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"loadaddr=200000\0" \
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"kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \
|
||||
"kernel_addr_r=1000000\0" \
|
||||
"fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \
|
||||
"fdt_addr_r=1800000\0" \
|
||||
"bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
|
||||
"fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \
|
||||
__stringify(CONFIG_HOSTNAME) ".dtb\0" \
|
||||
"rootpath=/opt/eldk-5.2.1/powerpc/" \
|
||||
"core-image-minimal-mtdutils-dropbear-generic\0" \
|
||||
"consoledev=ttyPSC0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\
|
||||
"mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
|
|
@ -332,18 +350,18 @@
|
|||
"flash_mtd=run mtdargs addip addtty;" \
|
||||
"bootm ${kernel_addr} - ${fdtaddr}\0" \
|
||||
"flash_self=run ramargs addip addtty;" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
|
||||
"net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};" \
|
||||
"tftp c00000 ${fdtfile};" \
|
||||
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
|
||||
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
|
||||
"tftp ${fdt_addr_r} ${fdtfile};" \
|
||||
"run nfsargs addip addtty;" \
|
||||
"bootm ${loadaddr} - c00000\0" \
|
||||
"load=tftp ${loadaddr} u-boot.bin\0" \
|
||||
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
|
||||
"load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \
|
||||
"/u-boot-img.bin\0" \
|
||||
"update=protect off fc000000 fc03ffff; " \
|
||||
"era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\
|
||||
"era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \
|
||||
"fdtfile=dtbFile\0" \
|
||||
"kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \
|
||||
"bootdelay=3\0" \
|
||||
"bootcmd=run net_nfs\0" \
|
||||
""
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run flash_mtd"
|
||||
|
|
@ -353,6 +371,7 @@
|
|||
*/
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#define CONFIG_SPL_NOR_SUPPORT
|
||||
#define CONFIG_SPL_TEXT_BASE 0xfc000000
|
||||
#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
|
||||
|
|
|
|||
Loading…
Reference in New Issue