diff --git a/u-boot/include/configs/ar7240_freq.h b/u-boot/include/configs/ar7240_freq.h new file mode 100644 index 0000000000..d1891e9587 --- /dev/null +++ b/u-boot/include/configs/ar7240_freq.h @@ -0,0 +1,111 @@ + +#undef CFG_HZ +/* + * MIPS32 24K Processor Core Family Software User's Manual + * + * 6.2.9 Count Register (CP0 Register 9, Select 0) + * The Count register acts as a timer, incrementing at a constant + * rate, whether or not an instruction is executed, retired, or + * any forward progress is made through the pipeline. The counter + * increments every other clock, if the DC bit in the Cause register + * is 0. + */ +/* Since the count is incremented every other tick, divide by 2 */ +/* XXX derive this from CFG_PLL_FREQ */ +#define CPU_PLL_DITHER_FRAC_VAL 0x001003e8 +#define CPU_CLK_CONTROL_VAL2 0x00008000 + +#if (CFG_PLL_FREQ == CFG_PLL_200_200_100) +# define CFG_HZ (200000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150) +# define CFG_HZ (300000000/2) + #if CONFIG_40MHZ_XTAL_SUPPORT + #define CPU_PLL_CONFIG_VAL1 0x40813C00 + #define CPU_PLL_CONFIG_VAL2 0x00813C00 + #else + #define CPU_PLL_CONFIG_VAL1 0x40816000 + #define CPU_PLL_CONFIG_VAL2 0x00816000 + #endif +#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175) +# define CFG_HZ (350000000/2) + #if CONFIG_40MHZ_XTAL_SUPPORT + #undef CPU_PLL_DITHER_FRAC_VAL + #define CPU_PLL_DITHER_FRAC_VAL 0x001803E8 + #define CPU_PLL_CONFIG_VAL1 0x40814600 + #define CPU_PLL_CONFIG_VAL2 0x00814600 + #else + #define CPU_PLL_CONFIG_VAL1 0x40817000 + #define CPU_PLL_CONFIG_VAL2 0x00817000 + #endif +#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166) +# define CFG_HZ (333000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133) +# define CFG_HZ (266000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66) +# define CFG_HZ (266000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100) +# define CFG_HZ (400000000/2) + #if CONFIG_40MHZ_XTAL_SUPPORT + #define CPU_PLL_CONFIG_VAL1 0x40815000 + #define CPU_PLL_CONFIG_VAL2 0x00815000 + #else + #define CPU_PLL_CONFIG_VAL1 0x40818000 + #define CPU_PLL_CONFIG_VAL2 0x00818000 + #endif +#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160) +# define CFG_HZ (320000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200) +# define CFG_HZ (410000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200) +# define CFG_HZ (420000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_362_362_181) +# define CFG_HZ (326500000/2) + #define CPU_PLL_CONFIG_VAL1 0x40817400 + #define CPU_PLL_CONFIG_VAL2 0x00817400 +#elif (CFG_PLL_FREQ == CFG_PLL_80_80_40) +# define CFG_HZ (80000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_64_64_32) +# define CFG_HZ (64000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_48_48_24) +# define CFG_HZ (48000000/2) +#elif (CFG_PLL_FREQ == CFG_PLL_32_32_16) +# define CFG_HZ (32000000/2) +#endif + +#if CONFIG_40MHZ_XTAL_SUPPORT + #define CPU_PLL_SETTLE_TIME_VAL 0x00000550 +#else + #define CPU_PLL_SETTLE_TIME_VAL 0x00000352 +#endif + +/* DDR init values */ + +#define CONFIG_NR_DRAM_BANKS 2 +#if CONFIG_40MHZ_XTAL_SUPPORT +#define CFG_DDR_REFRESH_VAL 0x4270 +#else +#define CFG_DDR_REFRESH_VAL 0x4186 +#endif +#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0 +#define CFG_DDR_MODE_VAL_INIT 0x133 +#ifdef LOW_DRIVE_STRENGTH +# define CFG_DDR_EXT_MODE_VAL 0x2 +#else +# define CFG_DDR_EXT_MODE_VAL 0x0 +#endif +#define CFG_DDR_MODE_VAL 0x33 + +#define CFG_DDR_TRTW_VAL 0x1f +#define CFG_DDR_TWTR_VAL 0x1e + +//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0 +#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1 + +#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff + +#define CFG_DDR_TAP0_VAL 0x8 +#define CFG_DDR_TAP1_VAL 0x9 + +/* DDR2 Init values */ +#define CFG_DDR2_EXT_MODE_VAL 0x402 + diff --git a/u-boot/include/configs/carambola2.h b/u-boot/include/configs/carambola2.h index 06d0913797..8851b21b69 100644 --- a/u-boot/include/configs/carambola2.h +++ b/u-boot/include/configs/carambola2.h @@ -11,9 +11,7 @@ #define FLASH_SIZE 16 #define CONFIG_AR7240 1 #define CONFIG_MACH_HORNET 1 -#define CONFIG_40MHZ_XTAL_SUPPORT 1 #define CONFIG_HORNET_1_1_WAR 1 -#define NEW_DDR_TAP_CAL 1 /* enable watchdog */ #define CONFIG_HW_WATCHDOG @@ -62,90 +60,16 @@ #define CONFIG_BOOTARGS "" #define MTDPARTS_DEFAULT "" +/* pll and ddr configuration */ +#define CONFIG_40MHZ_XTAL_SUPPORT 1 +#define NEW_DDR_TAP_CAL 1 + #undef CFG_PLL_FREQ #define CFG_PLL_FREQ CFG_PLL_400_400_200 +#include -#undef CFG_HZ -/* - * MIPS32 24K Processor Core Family Software User's Manual - * - * 6.2.9 Count Register (CP0 Register 9, Select 0) - * The Count register acts as a timer, incrementing at a constant - * rate, whether or not an instruction is executed, retired, or - * any forward progress is made through the pipeline. The counter - * increments every other clock, if the DC bit in the Cause register - * is 0. - */ -/* Since the count is incremented every other tick, divide by 2 */ -/* XXX derive this from CFG_PLL_FREQ */ -#define CPU_PLL_DITHER_FRAC_VAL 0x001003e8 -#define CPU_CLK_CONTROL_VAL2 0x00008000 - -#if (CFG_PLL_FREQ == CFG_PLL_200_200_100) -# define CFG_HZ (200000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150) -# define CFG_HZ (300000000/2) - #if CONFIG_40MHZ_XTAL_SUPPORT - #define CPU_PLL_CONFIG_VAL1 0x40813C00 - #define CPU_PLL_CONFIG_VAL2 0x00813C00 - #else - #define CPU_PLL_CONFIG_VAL1 0x40816000 - #define CPU_PLL_CONFIG_VAL2 0x00816000 - #endif -#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175) -# define CFG_HZ (350000000/2) - #if CONFIG_40MHZ_XTAL_SUPPORT - #undef CPU_PLL_DITHER_FRAC_VAL - #define CPU_PLL_DITHER_FRAC_VAL 0x001803E8 - #define CPU_PLL_CONFIG_VAL1 0x40814600 - #define CPU_PLL_CONFIG_VAL2 0x00814600 - #else - #define CPU_PLL_CONFIG_VAL1 0x40817000 - #define CPU_PLL_CONFIG_VAL2 0x00817000 - #endif -#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166) -# define CFG_HZ (333000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133) -# define CFG_HZ (266000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66) -# define CFG_HZ (266000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100) -# define CFG_HZ (400000000/2) - #if CONFIG_40MHZ_XTAL_SUPPORT - #define CPU_PLL_CONFIG_VAL1 0x40815000 - #define CPU_PLL_CONFIG_VAL2 0x00815000 - #else - #define CPU_PLL_CONFIG_VAL1 0x40818000 - #define CPU_PLL_CONFIG_VAL2 0x00818000 - #endif -#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160) -# define CFG_HZ (320000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200) -# define CFG_HZ (410000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200) -# define CFG_HZ (420000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_362_362_181) -# define CFG_HZ (326500000/2) - #define CPU_PLL_CONFIG_VAL1 0x40817400 - #define CPU_PLL_CONFIG_VAL2 0x00817400 -#elif (CFG_PLL_FREQ == CFG_PLL_80_80_40) -# define CFG_HZ (80000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_64_64_32) -# define CFG_HZ (64000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_48_48_24) -# define CFG_HZ (48000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_32_32_16) -# define CFG_HZ (32000000/2) -#endif - -#if CONFIG_40MHZ_XTAL_SUPPORT - #define CPU_PLL_SETTLE_TIME_VAL 0x00000550 -#else - #define CPU_PLL_SETTLE_TIME_VAL 0x00000352 -#endif - /* * timeout values are in ticks */ @@ -171,37 +95,6 @@ #define CONFIG_BOOTCOMMAND "bootm 0x9f050000" -/* DDR init values */ - -#define CONFIG_NR_DRAM_BANKS 2 -#if CONFIG_40MHZ_XTAL_SUPPORT -#define CFG_DDR_REFRESH_VAL 0x4270 -#else -#define CFG_DDR_REFRESH_VAL 0x4186 -#endif -#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0 -#define CFG_DDR_MODE_VAL_INIT 0x133 -#ifdef LOW_DRIVE_STRENGTH -# define CFG_DDR_EXT_MODE_VAL 0x2 -#else -# define CFG_DDR_EXT_MODE_VAL 0x0 -#endif -#define CFG_DDR_MODE_VAL 0x33 - -#define CFG_DDR_TRTW_VAL 0x1f -#define CFG_DDR_TWTR_VAL 0x1e - -//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0 -#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1 - -#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff - -#define CFG_DDR_TAP0_VAL 0x8 -#define CFG_DDR_TAP1_VAL 0x9 - -/* DDR2 Init values */ -#define CFG_DDR2_EXT_MODE_VAL 0x402 - #define CONFIG_NET_MULTI #define CONFIG_MEMSIZE_IN_BYTES diff --git a/u-boot/include/configs/skylab.h b/u-boot/include/configs/skylab.h index 8d6649edba..ca6595ba33 100644 --- a/u-boot/include/configs/skylab.h +++ b/u-boot/include/configs/skylab.h @@ -12,7 +12,6 @@ #define CONFIG_AR7240 1 #define CONFIG_MACH_HORNET 1 #define CONFIG_HORNET_1_1_WAR 1 -#define NEW_DDR_TAP_CAL 1 /* enable watchdog */ #define CONFIG_HW_WATCHDOG @@ -61,89 +60,13 @@ #define CONFIG_BOOTARGS "" #define MTDPARTS_DEFAULT "" +/* pll and ddr configuration */ +#define NEW_DDR_TAP_CAL 1 + #undef CFG_PLL_FREQ #define CFG_PLL_FREQ CFG_PLL_400_400_200 - - -#undef CFG_HZ -/* - * MIPS32 24K Processor Core Family Software User's Manual - * - * 6.2.9 Count Register (CP0 Register 9, Select 0) - * The Count register acts as a timer, incrementing at a constant - * rate, whether or not an instruction is executed, retired, or - * any forward progress is made through the pipeline. The counter - * increments every other clock, if the DC bit in the Cause register - * is 0. - */ -/* Since the count is incremented every other tick, divide by 2 */ -/* XXX derive this from CFG_PLL_FREQ */ -#define CPU_PLL_DITHER_FRAC_VAL 0x001003e8 -#define CPU_CLK_CONTROL_VAL2 0x00008000 - -#if (CFG_PLL_FREQ == CFG_PLL_200_200_100) -# define CFG_HZ (200000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150) -# define CFG_HZ (300000000/2) - #if CONFIG_40MHZ_XTAL_SUPPORT - #define CPU_PLL_CONFIG_VAL1 0x40813C00 - #define CPU_PLL_CONFIG_VAL2 0x00813C00 - #else - #define CPU_PLL_CONFIG_VAL1 0x40816000 - #define CPU_PLL_CONFIG_VAL2 0x00816000 - #endif -#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175) -# define CFG_HZ (350000000/2) - #if CONFIG_40MHZ_XTAL_SUPPORT - #undef CPU_PLL_DITHER_FRAC_VAL - #define CPU_PLL_DITHER_FRAC_VAL 0x001803E8 - #define CPU_PLL_CONFIG_VAL1 0x40814600 - #define CPU_PLL_CONFIG_VAL2 0x00814600 - #else - #define CPU_PLL_CONFIG_VAL1 0x40817000 - #define CPU_PLL_CONFIG_VAL2 0x00817000 - #endif -#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166) -# define CFG_HZ (333000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133) -# define CFG_HZ (266000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66) -# define CFG_HZ (266000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100) -# define CFG_HZ (400000000/2) - #if CONFIG_40MHZ_XTAL_SUPPORT - #define CPU_PLL_CONFIG_VAL1 0x40815000 - #define CPU_PLL_CONFIG_VAL2 0x00815000 - #else - #define CPU_PLL_CONFIG_VAL1 0x40818000 - #define CPU_PLL_CONFIG_VAL2 0x00818000 - #endif -#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160) -# define CFG_HZ (320000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200) -# define CFG_HZ (410000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200) -# define CFG_HZ (420000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_362_362_181) -# define CFG_HZ (326500000/2) - #define CPU_PLL_CONFIG_VAL1 0x40817400 - #define CPU_PLL_CONFIG_VAL2 0x00817400 -#elif (CFG_PLL_FREQ == CFG_PLL_80_80_40) -# define CFG_HZ (80000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_64_64_32) -# define CFG_HZ (64000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_48_48_24) -# define CFG_HZ (48000000/2) -#elif (CFG_PLL_FREQ == CFG_PLL_32_32_16) -# define CFG_HZ (32000000/2) -#endif - -#if CONFIG_40MHZ_XTAL_SUPPORT - #define CPU_PLL_SETTLE_TIME_VAL 0x00000550 -#else - #define CPU_PLL_SETTLE_TIME_VAL 0x00000352 -#endif +#include /* * timeout values are in ticks @@ -170,37 +93,6 @@ #define CONFIG_BOOTCOMMAND "bootm 0x9f050000" -/* DDR init values */ - -#define CONFIG_NR_DRAM_BANKS 2 -#if CONFIG_40MHZ_XTAL_SUPPORT -#define CFG_DDR_REFRESH_VAL 0x4270 -#else -#define CFG_DDR_REFRESH_VAL 0x4186 -#endif -#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0 -#define CFG_DDR_MODE_VAL_INIT 0x133 -#ifdef LOW_DRIVE_STRENGTH -# define CFG_DDR_EXT_MODE_VAL 0x2 -#else -# define CFG_DDR_EXT_MODE_VAL 0x0 -#endif -#define CFG_DDR_MODE_VAL 0x33 - -#define CFG_DDR_TRTW_VAL 0x1f -#define CFG_DDR_TWTR_VAL 0x1e - -//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0 -#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1 - -#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff - -#define CFG_DDR_TAP0_VAL 0x8 -#define CFG_DDR_TAP1_VAL 0x9 - -/* DDR2 Init values */ -#define CFG_DDR2_EXT_MODE_VAL 0x402 - #define CONFIG_NET_MULTI #define CONFIG_MEMSIZE_IN_BYTES