imx: mx7ulp: Add clock framework and functions
Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
0cb3d82c68
commit
d0f8516d9e
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@ -5,4 +5,4 @@
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#
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#
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obj-y := iomux.o
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obj-y := clock.o iomux.o pcc.o scg.o
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@ -0,0 +1,315 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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int get_clocks(void)
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{
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#ifdef CONFIG_FSL_ESDHC
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#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
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gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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#endif
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#endif
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return 0;
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}
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static u32 get_fast_plat_clk(void)
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{
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return scg_clk_get_rate(SCG_NIC0_CLK);
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}
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static u32 get_slow_plat_clk(void)
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{
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return scg_clk_get_rate(SCG_NIC1_CLK);
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}
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static u32 get_ipg_clk(void)
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{
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return scg_clk_get_rate(SCG_NIC1_BUS_CLK);
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}
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u32 get_lpuart_clk(void)
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{
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int index = 0;
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const u32 lpuart_array[] = {
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LPUART0_RBASE,
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LPUART1_RBASE,
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LPUART2_RBASE,
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LPUART3_RBASE,
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LPUART4_RBASE,
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LPUART5_RBASE,
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LPUART6_RBASE,
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LPUART7_RBASE,
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};
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const enum pcc_clk lpuart_pcc_clks[] = {
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PER_CLK_LPUART4,
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PER_CLK_LPUART5,
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PER_CLK_LPUART6,
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PER_CLK_LPUART7,
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};
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for (index = 0; index < 8; index++) {
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if (lpuart_array[index] == LPUART_BASE)
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break;
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}
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if (index < 4 || index > 7)
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return 0;
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return pcc_clock_get_rate(lpuart_pcc_clks[index - 4]);
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return scg_clk_get_rate(SCG_CORE_CLK);
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case MXC_AXI_CLK:
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return get_fast_plat_clk();
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case MXC_AHB_CLK:
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return get_slow_plat_clk();
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case MXC_IPG_CLK:
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return get_ipg_clk();
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case MXC_I2C_CLK:
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return pcc_clock_get_rate(PER_CLK_LPI2C4);
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case MXC_UART_CLK:
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return get_lpuart_clk();
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case MXC_ESDHC_CLK:
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return pcc_clock_get_rate(PER_CLK_USDHC0);
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case MXC_ESDHC2_CLK:
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return pcc_clock_get_rate(PER_CLK_USDHC1);
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case MXC_DDR_CLK:
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return scg_clk_get_rate(SCG_DDR_CLK);
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default:
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printf("Unsupported mxc_clock %d\n", clk);
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break;
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}
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return 0;
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}
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void init_clk_usdhc(u32 index)
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{
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switch (index) {
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case 0:
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/*Disable the clock before configure it */
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pcc_clock_enable(PER_CLK_USDHC0, false);
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/* 158MHz / 1 = 158MHz */
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pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK);
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pcc_clock_div_config(PER_CLK_USDHC0, false, 1);
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pcc_clock_enable(PER_CLK_USDHC0, true);
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break;
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case 1:
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/*Disable the clock before configure it */
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pcc_clock_enable(PER_CLK_USDHC1, false);
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/* 158MHz / 1 = 158MHz */
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pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK);
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pcc_clock_div_config(PER_CLK_USDHC1, false, 1);
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pcc_clock_enable(PER_CLK_USDHC1, true);
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break;
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default:
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printf("Invalid index for USDHC %d\n", index);
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break;
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}
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}
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#ifdef CONFIG_MXC_OCOTP
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#define OCOTP_CTRL_PCC1_SLOT (38)
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#define OCOTP_CTRL_HIGH4K_PCC1_SLOT (39)
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void enable_ocotp_clk(unsigned char enable)
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{
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u32 val;
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/*
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* Seems the OCOTP CLOCKs have been enabled at default,
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* check its inuse flag
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*/
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val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT);
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if (!(val & PCC_INUSE_MASK))
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writel(PCC_CGC_MASK, (PCC1_RBASE + 4 * OCOTP_CTRL_PCC1_SLOT));
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val = readl(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT);
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if (!(val & PCC_INUSE_MASK))
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writel(PCC_CGC_MASK,
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(PCC1_RBASE + 4 * OCOTP_CTRL_HIGH4K_PCC1_SLOT));
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}
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#endif
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void enable_usboh3_clk(unsigned char enable)
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{
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if (enable) {
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pcc_clock_enable(PER_CLK_USB0, false);
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pcc_clock_sel(PER_CLK_USB0, SCG_NIC1_BUS_CLK);
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pcc_clock_enable(PER_CLK_USB0, true);
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#ifdef CONFIG_USB_MAX_CONTROLLER_COUNT
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if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) {
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pcc_clock_enable(PER_CLK_USB1, false);
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pcc_clock_sel(PER_CLK_USB1, SCG_NIC1_BUS_CLK);
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pcc_clock_enable(PER_CLK_USB1, true);
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}
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#endif
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pcc_clock_enable(PER_CLK_USB_PHY, true);
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pcc_clock_enable(PER_CLK_USB_PL301, true);
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} else {
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pcc_clock_enable(PER_CLK_USB0, false);
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pcc_clock_enable(PER_CLK_USB1, false);
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pcc_clock_enable(PER_CLK_USB_PHY, false);
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pcc_clock_enable(PER_CLK_USB_PL301, false);
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}
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}
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static void lpuart_set_clk(uint32_t index, enum scg_clk clk)
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{
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const enum pcc_clk lpuart_pcc_clks[] = {
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PER_CLK_LPUART4,
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PER_CLK_LPUART5,
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PER_CLK_LPUART6,
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PER_CLK_LPUART7,
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};
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if (index < 4 || index > 7)
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return;
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#ifndef CONFIG_CLK_DEBUG
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pcc_clock_enable(lpuart_pcc_clks[index - 4], false);
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#endif
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pcc_clock_sel(lpuart_pcc_clks[index - 4], clk);
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pcc_clock_enable(lpuart_pcc_clks[index - 4], true);
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}
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static void init_clk_lpuart(void)
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{
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u32 index = 0, i;
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const u32 lpuart_array[] = {
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LPUART0_RBASE,
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LPUART1_RBASE,
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LPUART2_RBASE,
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LPUART3_RBASE,
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LPUART4_RBASE,
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LPUART5_RBASE,
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LPUART6_RBASE,
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LPUART7_RBASE,
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};
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for (i = 0; i < 8; i++) {
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if (lpuart_array[i] == LPUART_BASE) {
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index = i;
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break;
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}
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}
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lpuart_set_clk(index, SCG_SOSC_DIV2_CLK);
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}
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static void init_clk_rgpio2p(void)
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{
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/*Enable RGPIO2P1 clock */
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pcc_clock_enable(PER_CLK_RGPIO2P1, true);
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/*
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* Hard code to enable RGPIO2P0 clock since it is not
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* in clock frame for A7 domain
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*/
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writel(PCC_CGC_MASK, (PCC0_RBASE + 0x3C));
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}
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/* Configure PLL/PFD freq */
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void clock_init(void)
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{
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/*
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* ROM has enabled clocks:
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* A4 side: SIRC 16Mhz (DIV1-3 off), FIRC 48Mhz (DIV1-2 on),
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* Non-LP-boot: SOSC, SPLL PFD0 (scs selected)
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* A7 side: SPLL PFD0 (scs selected, 413Mhz),
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* APLL PFD0 (352Mhz), DDRCLK, all NIC clocks
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* A7 Plat0 (NIC0) = 176Mhz, Plat1 (NIC1) = 176Mhz,
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* IP BUS (NIC1_BUS) = 58.6Mhz
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*
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* In u-boot:
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* 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs.
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* 2. Enable USB PLL
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* 3. Init the clocks of peripherals used in u-boot bu
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* without set rate interface.The clocks for these
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* peripherals are enabled in this intialization.
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* 4.Other peripherals with set clock rate interface
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* does not be set in this function.
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*/
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scg_a7_firc_init();
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scg_a7_soscdiv_init();
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/* APLL PFD1 = 270Mhz, PFD2=480Mhz, PFD3=800Mhz */
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scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35);
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scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 20);
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scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12);
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init_clk_lpuart();
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init_clk_rgpio2p();
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enable_usboh3_clk(1);
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}
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/*
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* Dump some core clockes.
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*/
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int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 addr = 0;
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u32 freq;
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freq = decode_pll(PLL_A7_SPLL);
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printf("PLL_A7_SPLL %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_A7_APLL);
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printf("PLL_A7_APLL %8d MHz\n", freq / 1000000);
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freq = decode_pll(PLL_USB);
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printf("PLL_USB %8d MHz\n", freq / 1000000);
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printf("\n");
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printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000);
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printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
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printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
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printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
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printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
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printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
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printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
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printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
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printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000);
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addr = (u32) clock_init;
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printf("[%s] addr = 0x%08X\r\n", __func__, addr);
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scg_a7_info();
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return 0;
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}
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U_BOOT_CMD(
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clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
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"display clocks",
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""
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);
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@ -0,0 +1,286 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <div64.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/pcc.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PCC_CLKSRC_TYPES 2
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#define PCC_CLKSRC_NUM 7
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static enum scg_clk pcc_clksrc[PCC_CLKSRC_TYPES][PCC_CLKSRC_NUM] = {
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{ SCG_NIC1_BUS_CLK,
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SCG_NIC1_CLK,
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SCG_DDR_CLK,
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SCG_APLL_PFD2_CLK,
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SCG_APLL_PFD1_CLK,
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SCG_APLL_PFD0_CLK,
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USB_PLL_OUT,
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},
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{ SCG_SOSC_DIV2_CLK, /* SOSC BUS clock */
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MIPI_PLL_OUT,
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SCG_FIRC_DIV2_CLK, /* FIRC BUS clock */
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SCG_ROSC_CLK,
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SCG_NIC1_BUS_CLK,
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SCG_NIC1_CLK,
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SCG_APLL_PFD3_CLK,
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},
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};
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static struct pcc_entry pcc_arrays[] = {
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{PCC2_RBASE, DMA1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, RGPIO1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, FLEXBUS0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, SEMA42_1_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, DMA1_CH_MUX0_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, SNVS_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, CAAM_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, LPTPM4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPTPM5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPIT1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPSPI2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPSPI3_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPI2C4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPI2C5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPUART4_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, LPUART5_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, FLEXIO1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC2_RBASE, USBOTG0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USBOTG1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USBPHY_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, USB_PL301_PCC2_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
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{PCC2_RBASE, USDHC0_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, USDHC1_PCC2_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
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{PCC2_RBASE, WDG1_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC2_RBASE, WDG2_PCC2_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
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{PCC3_RBASE, LPTPM6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPTPM7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPI2C6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPI2C7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPUART6_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, LPUART7_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV},
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{PCC3_RBASE, VIU0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
|
||||
{PCC3_RBASE, DSI0_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV},
|
||||
{PCC3_RBASE, LCDIF0_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_HAS_DIV},
|
||||
{PCC3_RBASE, MMDC0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
|
||||
{PCC3_RBASE, PORTC_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
|
||||
{PCC3_RBASE, PORTD_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
|
||||
{PCC3_RBASE, PORTE_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
|
||||
{PCC3_RBASE, PORTF_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV},
|
||||
{PCC3_RBASE, GPU3D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
|
||||
{PCC3_RBASE, GPU2D_PCC3_SLOT, CLKSRC_PER_PLAT, PCC_NO_DIV},
|
||||
};
|
||||
|
||||
int pcc_clock_enable(enum pcc_clk clk, bool enable)
|
||||
{
|
||||
u32 reg, val;
|
||||
|
||||
if (clk >= ARRAY_SIZE(pcc_arrays))
|
||||
return -EINVAL;
|
||||
|
||||
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
|
||||
|
||||
val = readl(reg);
|
||||
|
||||
clk_debug("pcc_clock_enable: clk %d, reg 0x%x, val 0x%x, enable %d\n",
|
||||
clk, reg, val, enable);
|
||||
|
||||
if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK))
|
||||
return -EPERM;
|
||||
|
||||
if (enable)
|
||||
val |= PCC_CGC_MASK;
|
||||
else
|
||||
val &= ~PCC_CGC_MASK;
|
||||
|
||||
writel(val, reg);
|
||||
|
||||
clk_debug("pcc_clock_enable: val 0x%x\n", val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* The clock source select needs clock is disabled */
|
||||
int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src)
|
||||
{
|
||||
u32 reg, val, i, clksrc_type;
|
||||
|
||||
if (clk >= ARRAY_SIZE(pcc_arrays))
|
||||
return -EINVAL;
|
||||
|
||||
clksrc_type = pcc_arrays[clk].clksrc;
|
||||
if (clksrc_type >= CLKSRC_NO_PCS) {
|
||||
printf("No PCS field for the PCC %d, clksrc type %d\n",
|
||||
clk, clksrc_type);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
for (i = 0; i < PCC_CLKSRC_NUM; i++) {
|
||||
if (pcc_clksrc[clksrc_type][i] == src) {
|
||||
/* Find the clock src, then set it to PCS */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == PCC_CLKSRC_NUM) {
|
||||
printf("Not find the parent scg_clk in PCS of PCC %d, invalid scg_clk %d\n", clk, src);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
|
||||
|
||||
val = readl(reg);
|
||||
|
||||
clk_debug("pcc_clock_sel: clk %d, reg 0x%x, val 0x%x, clksrc_type %d\n",
|
||||
clk, reg, val, clksrc_type);
|
||||
|
||||
if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
|
||||
(val & PCC_CGC_MASK)) {
|
||||
printf("Not permit to select clock source val = 0x%x\n", val);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
val &= ~PCC_PCS_MASK;
|
||||
val |= ((i + 1) << PCC_PCS_OFFSET);
|
||||
|
||||
writel(val, reg);
|
||||
|
||||
clk_debug("pcc_clock_sel: val 0x%x\n", val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div)
|
||||
{
|
||||
u32 reg, val;
|
||||
|
||||
if (clk >= ARRAY_SIZE(pcc_arrays) || div > 8 ||
|
||||
(div == 1 && frac != 0))
|
||||
return -EINVAL;
|
||||
|
||||
if (pcc_arrays[clk].div >= PCC_NO_DIV) {
|
||||
printf("No DIV/FRAC field for the PCC %d\n", clk);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
|
||||
|
||||
val = readl(reg);
|
||||
|
||||
if (!(val & PCC_PR_MASK) || (val & PCC_INUSE_MASK) ||
|
||||
(val & PCC_CGC_MASK)) {
|
||||
printf("Not permit to set div/frac val = 0x%x\n", val);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
if (frac)
|
||||
val |= PCC_FRAC_MASK;
|
||||
else
|
||||
val &= ~PCC_FRAC_MASK;
|
||||
|
||||
val &= ~PCC_PCD_MASK;
|
||||
val |= (div - 1) & PCC_PCD_MASK;
|
||||
|
||||
writel(val, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool pcc_clock_is_enable(enum pcc_clk clk)
|
||||
{
|
||||
u32 reg, val;
|
||||
|
||||
if (clk >= ARRAY_SIZE(pcc_arrays))
|
||||
return -EINVAL;
|
||||
|
||||
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
|
||||
val = readl(reg);
|
||||
|
||||
if ((val & PCC_INUSE_MASK) || (val & PCC_CGC_MASK))
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src)
|
||||
{
|
||||
u32 reg, val, clksrc_type;
|
||||
|
||||
if (clk >= ARRAY_SIZE(pcc_arrays))
|
||||
return -EINVAL;
|
||||
|
||||
clksrc_type = pcc_arrays[clk].clksrc;
|
||||
if (clksrc_type >= CLKSRC_NO_PCS) {
|
||||
printf("No PCS field for the PCC %d, clksrc type %d\n",
|
||||
clk, clksrc_type);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
|
||||
|
||||
val = readl(reg);
|
||||
|
||||
clk_debug("pcc_clock_get_clksrc: clk %d, reg 0x%x, val 0x%x, type %d\n",
|
||||
clk, reg, val, clksrc_type);
|
||||
|
||||
if (!(val & PCC_PR_MASK)) {
|
||||
printf("This pcc slot is not present = 0x%x\n", val);
|
||||
return -EPERM;
|
||||
}
|
||||
|
||||
val &= PCC_PCS_MASK;
|
||||
val = (val >> PCC_PCS_OFFSET);
|
||||
|
||||
if (!val) {
|
||||
printf("Clock source is off\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
*src = pcc_clksrc[clksrc_type][val - 1];
|
||||
|
||||
clk_debug("pcc_clock_get_clksrc: parent scg clk %d\n", *src);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 pcc_clock_get_rate(enum pcc_clk clk)
|
||||
{
|
||||
u32 reg, val, rate, frac, div;
|
||||
enum scg_clk parent;
|
||||
int ret;
|
||||
|
||||
ret = pcc_clock_get_clksrc(clk, &parent);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
rate = scg_clk_get_rate(parent);
|
||||
|
||||
clk_debug("pcc_clock_get_rate: parent rate %u\n", rate);
|
||||
|
||||
if (pcc_arrays[clk].div == PCC_HAS_DIV) {
|
||||
reg = pcc_arrays[clk].pcc_base + pcc_arrays[clk].pcc_slot * 4;
|
||||
val = readl(reg);
|
||||
|
||||
frac = (val & PCC_FRAC_MASK) >> PCC_FRAC_OFFSET;
|
||||
div = (val & PCC_PCD_MASK) >> PCC_PCD_OFFSET;
|
||||
|
||||
/*
|
||||
* Theoretically don't have overflow in the calc,
|
||||
* the rate won't exceed 2G
|
||||
*/
|
||||
rate = rate * (frac + 1) / (div + 1);
|
||||
}
|
||||
|
||||
clk_debug("pcc_clock_get_rate: rate %u\n", rate);
|
||||
return rate;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_CLOCK_H
|
||||
#define _ASM_ARCH_CLOCK_H
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pcc.h>
|
||||
#include <asm/arch/scg.h>
|
||||
|
||||
/* Mainly for compatible to imx common code. */
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_AHB_CLK,
|
||||
MXC_IPG_CLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_AXI_CLK,
|
||||
MXC_DDR_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_I2C_CLK,
|
||||
};
|
||||
|
||||
u32 mxc_get_clock(enum mxc_clock clk);
|
||||
u32 get_lpuart_clk(void);
|
||||
#ifdef CONFIG_MXC_OCOTP
|
||||
void enable_ocotp_clk(unsigned char enable);
|
||||
#endif
|
||||
#ifdef CONFIG_USB_EHCI
|
||||
void enable_usboh3_clk(unsigned char enable);
|
||||
#endif
|
||||
void init_clk_usdhc(u32 index);
|
||||
void clock_init(void);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,373 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_PCC_H
|
||||
#define _ASM_ARCH_PCC_H
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/scg.h>
|
||||
|
||||
/* PCC2 */
|
||||
|
||||
enum pcc2_entry {
|
||||
/* On-Platform (32 entries) */
|
||||
RSVD0_PCC2_SLOT = 0,
|
||||
RSVD1_PCC2_SLOT = 1,
|
||||
CA7_GIC_PCC2_SLOT = 2,
|
||||
RSVD3_PCC2_SLOT = 3,
|
||||
RSVD4_PCC2_SLOT = 4,
|
||||
RSVD5_PCC2_SLOT = 5,
|
||||
RSVD6_PCC2_SLOT = 6,
|
||||
RSVD7_PCC2_SLOT = 7,
|
||||
DMA1_PCC2_SLOT = 8,
|
||||
RSVD9_PCC2_SLOT = 9,
|
||||
RSVD10_PCC2_SLOT = 10,
|
||||
RSVD11_PCC2_SLOT = 11,
|
||||
RSVD12_PCC2_SLOT = 12,
|
||||
RSVD13_PCC2_SLOT = 13,
|
||||
RSVD14_PCC2_SLOT = 14,
|
||||
RGPIO1_PCC2_SLOT = 15,
|
||||
FLEXBUS0_PCC2_SLOT = 16,
|
||||
RSVD17_PCC2_SLOT = 17,
|
||||
RSVD18_PCC2_SLOT = 18,
|
||||
RSVD19_PCC2_SLOT = 19,
|
||||
RSVD20_PCC2_SLOT = 20,
|
||||
RSVD21_PCC2_SLOT = 21,
|
||||
RSVD22_PCC2_SLOT = 22,
|
||||
RSVD23_PCC2_SLOT = 23,
|
||||
RSVD24_PCC2_SLOT = 24,
|
||||
RSVD25_PCC2_SLOT = 25,
|
||||
RSVD26_PCC2_SLOT = 26,
|
||||
SEMA42_1_PCC2_SLOT = 27,
|
||||
RSVD28_PCC2_SLOT = 28,
|
||||
RSVD29_PCC2_SLOT = 29,
|
||||
RSVD30_PCC2_SLOT = 30,
|
||||
RSVD31_PCC2_SLOT = 31,
|
||||
|
||||
/* Off-Platform (96 entries) */
|
||||
RSVD32_PCC2_SLOT = 32,
|
||||
DMA1_CH_MUX0_PCC2_SLOT = 33,
|
||||
MU_B_PCC2_SLOT = 34,
|
||||
SNVS_PCC2_SLOT = 35,
|
||||
CAAM_PCC2_SLOT = 36,
|
||||
LPTPM4_PCC2_SLOT = 37,
|
||||
LPTPM5_PCC2_SLOT = 38,
|
||||
LPIT1_PCC2_SLOT = 39,
|
||||
RSVD40_PCC2_SLOT = 40,
|
||||
LPSPI2_PCC2_SLOT = 41,
|
||||
LPSPI3_PCC2_SLOT = 42,
|
||||
LPI2C4_PCC2_SLOT = 43,
|
||||
LPI2C5_PCC2_SLOT = 44,
|
||||
LPUART4_PCC2_SLOT = 45,
|
||||
LPUART5_PCC2_SLOT = 46,
|
||||
RSVD47_PCC2_SLOT = 47,
|
||||
RSVD48_PCC2_SLOT = 48,
|
||||
FLEXIO1_PCC2_SLOT = 49,
|
||||
RSVD50_PCC2_SLOT = 50,
|
||||
USBOTG0_PCC2_SLOT = 51,
|
||||
USBOTG1_PCC2_SLOT = 52,
|
||||
USBPHY_PCC2_SLOT = 53,
|
||||
USB_PL301_PCC2_SLOT = 54,
|
||||
USDHC0_PCC2_SLOT = 55,
|
||||
USDHC1_PCC2_SLOT = 56,
|
||||
RSVD57_PCC2_SLOT = 57,
|
||||
TRGMUX1_PCC2_SLOT = 58,
|
||||
RSVD59_PCC2_SLOT = 59,
|
||||
RSVD60_PCC2_SLOT = 60,
|
||||
WDG1_PCC2_SLOT = 61,
|
||||
SCG1_PCC2_SLOT = 62,
|
||||
PCC2_PCC2_SLOT = 63,
|
||||
PMC1_PCC2_SLOT = 64,
|
||||
SMC1_PCC2_SLOT = 65,
|
||||
RCM1_PCC2_SLOT = 66,
|
||||
WDG2_PCC2_SLOT = 67,
|
||||
RSVD68_PCC2_SLOT = 68,
|
||||
TEST_SPACE1_PCC2_SLOT = 69,
|
||||
TEST_SPACE2_PCC2_SLOT = 70,
|
||||
TEST_SPACE3_PCC2_SLOT = 71,
|
||||
RSVD72_PCC2_SLOT = 72,
|
||||
RSVD73_PCC2_SLOT = 73,
|
||||
RSVD74_PCC2_SLOT = 74,
|
||||
RSVD75_PCC2_SLOT = 75,
|
||||
RSVD76_PCC2_SLOT = 76,
|
||||
RSVD77_PCC2_SLOT = 77,
|
||||
RSVD78_PCC2_SLOT = 78,
|
||||
RSVD79_PCC2_SLOT = 79,
|
||||
RSVD80_PCC2_SLOT = 80,
|
||||
RSVD81_PCC2_SLOT = 81,
|
||||
RSVD82_PCC2_SLOT = 82,
|
||||
RSVD83_PCC2_SLOT = 83,
|
||||
RSVD84_PCC2_SLOT = 84,
|
||||
RSVD85_PCC2_SLOT = 85,
|
||||
RSVD86_PCC2_SLOT = 86,
|
||||
RSVD87_PCC2_SLOT = 87,
|
||||
RSVD88_PCC2_SLOT = 88,
|
||||
RSVD89_PCC2_SLOT = 89,
|
||||
RSVD90_PCC2_SLOT = 90,
|
||||
RSVD91_PCC2_SLOT = 91,
|
||||
RSVD92_PCC2_SLOT = 92,
|
||||
RSVD93_PCC2_SLOT = 93,
|
||||
RSVD94_PCC2_SLOT = 94,
|
||||
RSVD95_PCC2_SLOT = 95,
|
||||
RSVD96_PCC2_SLOT = 96,
|
||||
RSVD97_PCC2_SLOT = 97,
|
||||
RSVD98_PCC2_SLOT = 98,
|
||||
RSVD99_PCC2_SLOT = 99,
|
||||
RSVD100_PCC2_SLOT = 100,
|
||||
RSVD101_PCC2_SLOT = 101,
|
||||
RSVD102_PCC2_SLOT = 102,
|
||||
RSVD103_PCC2_SLOT = 103,
|
||||
RSVD104_PCC2_SLOT = 104,
|
||||
RSVD105_PCC2_SLOT = 105,
|
||||
RSVD106_PCC2_SLOT = 106,
|
||||
RSVD107_PCC2_SLOT = 107,
|
||||
RSVD108_PCC2_SLOT = 108,
|
||||
RSVD109_PCC2_SLOT = 109,
|
||||
RSVD110_PCC2_SLOT = 110,
|
||||
RSVD111_PCC2_SLOT = 111,
|
||||
RSVD112_PCC2_SLOT = 112,
|
||||
RSVD113_PCC2_SLOT = 113,
|
||||
RSVD114_PCC2_SLOT = 114,
|
||||
RSVD115_PCC2_SLOT = 115,
|
||||
RSVD116_PCC2_SLOT = 116,
|
||||
RSVD117_PCC2_SLOT = 117,
|
||||
RSVD118_PCC2_SLOT = 118,
|
||||
RSVD119_PCC2_SLOT = 119,
|
||||
RSVD120_PCC2_SLOT = 120,
|
||||
RSVD121_PCC2_SLOT = 121,
|
||||
RSVD122_PCC2_SLOT = 122,
|
||||
RSVD123_PCC2_SLOT = 123,
|
||||
RSVD124_PCC2_SLOT = 124,
|
||||
RSVD125_PCC2_SLOT = 125,
|
||||
RSVD126_PCC2_SLOT = 126,
|
||||
RSVD127_PCC2_SLOT = 127,
|
||||
};
|
||||
|
||||
enum pcc3_entry {
|
||||
/* On-Platform (32 entries) */
|
||||
RSVD0_PCC3_SLOT = 0,
|
||||
RSVD1_PCC3_SLOT = 1,
|
||||
RSVD2_PCC3_SLOT = 2,
|
||||
RSVD3_PCC3_SLOT = 3,
|
||||
RSVD4_PCC3_SLOT = 4,
|
||||
RSVD5_PCC3_SLOT = 5,
|
||||
RSVD6_PCC3_SLOT = 6,
|
||||
RSVD7_PCC3_SLOT = 7,
|
||||
RSVD8_PCC3_SLOT = 8,
|
||||
RSVD9_PCC3_SLOT = 9,
|
||||
RSVD10_PCC3_SLOT = 10,
|
||||
RSVD11_PCC3_SLOT = 11,
|
||||
RSVD12_PCC3_SLOT = 12,
|
||||
RSVD13_PCC3_SLOT = 13,
|
||||
RSVD14_PCC3_SLOT = 14,
|
||||
RSVD15_PCC3_SLOT = 15,
|
||||
ROMCP1_PCC3_SLOT = 16,
|
||||
RSVD17_PCC3_SLOT = 17,
|
||||
RSVD18_PCC3_SLOT = 18,
|
||||
RSVD19_PCC3_SLOT = 19,
|
||||
RSVD20_PCC3_SLOT = 20,
|
||||
RSVD21_PCC3_SLOT = 21,
|
||||
RSVD22_PCC3_SLOT = 22,
|
||||
RSVD23_PCC3_SLOT = 23,
|
||||
RSVD24_PCC3_SLOT = 24,
|
||||
RSVD25_PCC3_SLOT = 25,
|
||||
RSVD26_PCC3_SLOT = 26,
|
||||
RSVD27_PCC3_SLOT = 27,
|
||||
RSVD28_PCC3_SLOT = 28,
|
||||
RSVD29_PCC3_SLOT = 29,
|
||||
RSVD30_PCC3_SLOT = 30,
|
||||
RSVD31_PCC3_SLOT = 31,
|
||||
|
||||
/* Off-Platform (96 entries) */
|
||||
RSVD32_PCC3_SLOT = 32,
|
||||
LPTPM6_PCC3_SLOT = 33,
|
||||
LPTPM7_PCC3_SLOT = 34,
|
||||
RSVD35_PCC3_SLOT = 35,
|
||||
LPI2C6_PCC3_SLOT = 36,
|
||||
LPI2C7_PCC3_SLOT = 37,
|
||||
LPUART6_PCC3_SLOT = 38,
|
||||
LPUART7_PCC3_SLOT = 39,
|
||||
VIU0_PCC3_SLOT = 40,
|
||||
DSI0_PCC3_SLOT = 41,
|
||||
LCDIF0_PCC3_SLOT = 42,
|
||||
MMDC0_PCC3_SLOT = 43,
|
||||
IOMUXC1_PCC3_SLOT = 44,
|
||||
IOMUXC_DDR_PCC3_SLOT = 45,
|
||||
PORTC_PCC3_SLOT = 46,
|
||||
PORTD_PCC3_SLOT = 47,
|
||||
PORTE_PCC3_SLOT = 48,
|
||||
PORTF_PCC3_SLOT = 49,
|
||||
RSVD50_PCC3_SLOT = 50,
|
||||
PCC3_PCC3_SLOT = 51,
|
||||
RSVD52_PCC3_SLOT = 52,
|
||||
WKPU_PCC3_SLOT = 53,
|
||||
RSVD54_PCC3_SLOT = 54,
|
||||
RSVD55_PCC3_SLOT = 55,
|
||||
RSVD56_PCC3_SLOT = 56,
|
||||
RSVD57_PCC3_SLOT = 57,
|
||||
RSVD58_PCC3_SLOT = 58,
|
||||
RSVD59_PCC3_SLOT = 59,
|
||||
RSVD60_PCC3_SLOT = 60,
|
||||
RSVD61_PCC3_SLOT = 61,
|
||||
RSVD62_PCC3_SLOT = 62,
|
||||
RSVD63_PCC3_SLOT = 63,
|
||||
RSVD64_PCC3_SLOT = 64,
|
||||
RSVD65_PCC3_SLOT = 65,
|
||||
RSVD66_PCC3_SLOT = 66,
|
||||
RSVD67_PCC3_SLOT = 67,
|
||||
RSVD68_PCC3_SLOT = 68,
|
||||
RSVD69_PCC3_SLOT = 69,
|
||||
RSVD70_PCC3_SLOT = 70,
|
||||
RSVD71_PCC3_SLOT = 71,
|
||||
RSVD72_PCC3_SLOT = 72,
|
||||
RSVD73_PCC3_SLOT = 73,
|
||||
RSVD74_PCC3_SLOT = 74,
|
||||
RSVD75_PCC3_SLOT = 75,
|
||||
RSVD76_PCC3_SLOT = 76,
|
||||
RSVD77_PCC3_SLOT = 77,
|
||||
RSVD78_PCC3_SLOT = 78,
|
||||
RSVD79_PCC3_SLOT = 79,
|
||||
RSVD80_PCC3_SLOT = 80,
|
||||
GPU3D_PCC3_SLOT = 81,
|
||||
GPU2D_PCC3_SLOT = 82,
|
||||
RSVD83_PCC3_SLOT = 83,
|
||||
RSVD84_PCC3_SLOT = 84,
|
||||
RSVD85_PCC3_SLOT = 85,
|
||||
RSVD86_PCC3_SLOT = 86,
|
||||
RSVD87_PCC3_SLOT = 87,
|
||||
RSVD88_PCC3_SLOT = 88,
|
||||
RSVD89_PCC3_SLOT = 89,
|
||||
RSVD90_PCC3_SLOT = 90,
|
||||
RSVD91_PCC3_SLOT = 91,
|
||||
RSVD92_PCC3_SLOT = 92,
|
||||
RSVD93_PCC3_SLOT = 93,
|
||||
RSVD94_PCC3_SLOT = 94,
|
||||
RSVD95_PCC3_SLOT = 95,
|
||||
RSVD96_PCC3_SLOT = 96,
|
||||
RSVD97_PCC3_SLOT = 97,
|
||||
RSVD98_PCC3_SLOT = 98,
|
||||
RSVD99_PCC3_SLOT = 99,
|
||||
RSVD100_PCC3_SLOT = 100,
|
||||
RSVD101_PCC3_SLOT = 101,
|
||||
RSVD102_PCC3_SLOT = 102,
|
||||
RSVD103_PCC3_SLOT = 103,
|
||||
RSVD104_PCC3_SLOT = 104,
|
||||
RSVD105_PCC3_SLOT = 105,
|
||||
RSVD106_PCC3_SLOT = 106,
|
||||
RSVD107_PCC3_SLOT = 107,
|
||||
RSVD108_PCC3_SLOT = 108,
|
||||
RSVD109_PCC3_SLOT = 109,
|
||||
RSVD110_PCC3_SLOT = 110,
|
||||
RSVD111_PCC3_SLOT = 111,
|
||||
RSVD112_PCC3_SLOT = 112,
|
||||
RSVD113_PCC3_SLOT = 113,
|
||||
RSVD114_PCC3_SLOT = 114,
|
||||
RSVD115_PCC3_SLOT = 115,
|
||||
RSVD116_PCC3_SLOT = 116,
|
||||
RSVD117_PCC3_SLOT = 117,
|
||||
RSVD118_PCC3_SLOT = 118,
|
||||
RSVD119_PCC3_SLOT = 119,
|
||||
RSVD120_PCC3_SLOT = 120,
|
||||
RSVD121_PCC3_SLOT = 121,
|
||||
RSVD122_PCC3_SLOT = 122,
|
||||
RSVD123_PCC3_SLOT = 123,
|
||||
RSVD124_PCC3_SLOT = 124,
|
||||
RSVD125_PCC3_SLOT = 125,
|
||||
RSVD126_PCC3_SLOT = 126,
|
||||
RSVD127_PCC3_SLOT = 127,
|
||||
};
|
||||
|
||||
|
||||
/* PCC registers */
|
||||
#define PCC_PR_OFFSET 31
|
||||
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
|
||||
#define PCC_CGC_OFFSET 30
|
||||
#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
|
||||
#define PCC_INUSE_OFFSET 29
|
||||
#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
|
||||
#define PCC_PCS_OFFSET 24
|
||||
#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
|
||||
#define PCC_FRAC_OFFSET 4
|
||||
#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
|
||||
#define PCC_PCD_OFFSET 0
|
||||
#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET)
|
||||
|
||||
|
||||
enum pcc_clksrc_type {
|
||||
CLKSRC_PER_PLAT = 0,
|
||||
CLKSRC_PER_BUS = 1,
|
||||
CLKSRC_NO_PCS = 2,
|
||||
};
|
||||
|
||||
enum pcc_div_type {
|
||||
PCC_HAS_DIV,
|
||||
PCC_NO_DIV,
|
||||
};
|
||||
|
||||
/* All peripheral clocks on A7 PCCs */
|
||||
enum pcc_clk {
|
||||
/*PCC2 clocks*/
|
||||
PER_CLK_DMA1 = 0,
|
||||
PER_CLK_RGPIO2P1,
|
||||
PER_CLK_FLEXBUS,
|
||||
PER_CLK_SEMA42_1,
|
||||
PER_CLK_DMA_MUX1,
|
||||
PER_CLK_SNVS,
|
||||
PER_CLK_CAAM,
|
||||
PER_CLK_LPTPM4,
|
||||
PER_CLK_LPTPM5,
|
||||
PER_CLK_LPIT1,
|
||||
PER_CLK_LPSPI2,
|
||||
PER_CLK_LPSPI3,
|
||||
PER_CLK_LPI2C4,
|
||||
PER_CLK_LPI2C5,
|
||||
PER_CLK_LPUART4,
|
||||
PER_CLK_LPUART5,
|
||||
PER_CLK_FLEXIO1,
|
||||
PER_CLK_USB0,
|
||||
PER_CLK_USB1,
|
||||
PER_CLK_USB_PHY,
|
||||
PER_CLK_USB_PL301,
|
||||
PER_CLK_USDHC0,
|
||||
PER_CLK_USDHC1,
|
||||
PER_CLK_WDG1,
|
||||
PER_CLK_WDG2,
|
||||
|
||||
/*PCC3 clocks*/
|
||||
PER_CLK_LPTPM6,
|
||||
PER_CLK_LPTPM7,
|
||||
PER_CLK_LPI2C6,
|
||||
PER_CLK_LPI2C7,
|
||||
PER_CLK_LPUART6,
|
||||
PER_CLK_LPUART7,
|
||||
PER_CLK_VIU,
|
||||
PER_CLK_DSI,
|
||||
PER_CLK_LCDIF,
|
||||
PER_CLK_MMDC,
|
||||
PER_CLK_PCTLC,
|
||||
PER_CLK_PCTLD,
|
||||
PER_CLK_PCTLE,
|
||||
PER_CLK_PCTLF,
|
||||
PER_CLK_GPU3D,
|
||||
PER_CLK_GPU2D,
|
||||
};
|
||||
|
||||
|
||||
/* This structure keeps info for each pcc slot */
|
||||
struct pcc_entry {
|
||||
u32 pcc_base;
|
||||
u32 pcc_slot;
|
||||
enum pcc_clksrc_type clksrc;
|
||||
enum pcc_div_type div;
|
||||
};
|
||||
|
||||
int pcc_clock_enable(enum pcc_clk clk, bool enable);
|
||||
int pcc_clock_sel(enum pcc_clk clk, enum scg_clk src);
|
||||
int pcc_clock_div_config(enum pcc_clk clk, bool frac, u8 div);
|
||||
bool pcc_clock_is_enable(enum pcc_clk clk);
|
||||
int pcc_clock_get_clksrc(enum pcc_clk clk, enum scg_clk *src);
|
||||
u32 pcc_clock_get_rate(enum pcc_clk clk);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SCG_H
|
||||
#define _ASM_ARCH_SCG_H
|
||||
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_CLK_DEBUG
|
||||
#define clk_debug(fmt, args...) printf(fmt, ##args)
|
||||
#else
|
||||
#define clk_debug(fmt, args...)
|
||||
#endif
|
||||
|
||||
#define SCG_CCR_SCS_SHIFT (24)
|
||||
#define SCG_CCR_SCS_MASK ((0xFUL) << SCG_CCR_SCS_SHIFT)
|
||||
#define SCG_CCR_DIVCORE_SHIFT (16)
|
||||
#define SCG_CCR_DIVCORE_MASK ((0xFUL) << SCG_CCR_DIVCORE_SHIFT)
|
||||
#define SCG_CCR_DIVPLAT_SHIFT (12)
|
||||
#define SCG_CCR_DIVPLAT_MASK ((0xFUL) << SCG_CCR_DIVPLAT_SHIFT)
|
||||
#define SCG_CCR_DIVEXT_SHIFT (8)
|
||||
#define SCG_CCR_DIVEXT_MASK ((0xFUL) << SCG_CCR_DIVEXT_SHIFT)
|
||||
#define SCG_CCR_DIVBUS_SHIFT (4)
|
||||
#define SCG_CCR_DIVBUS_MASK ((0xFUL) << SCG_CCR_DIVBUS_SHIFT)
|
||||
#define SCG_CCR_DIVSLOW_SHIFT (0)
|
||||
#define SCG_CCR_DIVSLOW_MASK ((0xFUL) << SCG_CCR_DIVSLOW_SHIFT)
|
||||
|
||||
/* SCG DDR Clock Control Register */
|
||||
#define SCG_DDRCCR_DDRCS_SHIFT (24)
|
||||
#define SCG_DDRCCR_DDRCS_MASK ((0x1UL) << SCG_DDRCCR_DDRCS_SHIFT)
|
||||
|
||||
#define SCG_DDRCCR_DDRDIV_SHIFT (0)
|
||||
#define SCG_DDRCCR_DDRDIV_MASK ((0x7UL) << SCG_DDRCCR_DDRDIV_SHIFT)
|
||||
|
||||
/* SCG NIC Clock Control Register */
|
||||
#define SCG_NICCCR_NICCS_SHIFT (28)
|
||||
#define SCG_NICCCR_NICCS_MASK ((0x1UL) << SCG_NICCCR_NICCS_SHIFT)
|
||||
|
||||
#define SCG_NICCCR_NIC0_DIV_SHIFT (24)
|
||||
#define SCG_NICCCR_NIC0_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC0_DIV_SHIFT)
|
||||
|
||||
#define SCG_NICCCR_GPU_DIV_SHIFT (20)
|
||||
#define SCG_NICCCR_GPU_DIV_MASK ((0xFUL) << SCG_NICCCR_GPU_DIV_SHIFT)
|
||||
|
||||
#define SCG_NICCCR_NIC1_DIV_SHIFT (16)
|
||||
#define SCG_NICCCR_NIC1_DIV_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIV_SHIFT)
|
||||
|
||||
#define SCG_NICCCR_NIC1_DIVEXT_SHIFT (8)
|
||||
#define SCG_NICCCR_NIC1_DIVEXT_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVEXT_SHIFT)
|
||||
|
||||
#define SCG_NICCCR_NIC1_DIVBUS_SHIFT (4)
|
||||
#define SCG_NICCCR_NIC1_DIVBUS_MASK ((0xFUL) << SCG_NICCCR_NIC1_DIVBUS_SHIFT)
|
||||
|
||||
/* SCG NIC clock status register */
|
||||
#define SCG_NICCSR_NICCS_SHIFT (28)
|
||||
#define SCG_NICCSR_NICCS_MASK ((0x1UL) << SCG_NICCSR_NICCS_SHIFT)
|
||||
|
||||
#define SCG_NICCSR_NIC0DIV_SHIFT (24)
|
||||
#define SCG_NICCSR_NIC0DIV_MASK ((0xFUL) << SCG_NICCSR_NIC0DIV_SHIFT)
|
||||
#define SCG_NICCSR_GPUDIV_SHIFT (20)
|
||||
#define SCG_NICCSR_GPUDIV_MASK ((0xFUL) << SCG_NICCSR_GPUDIV_SHIFT)
|
||||
#define SCG_NICCSR_NIC1DIV_SHIFT (16)
|
||||
#define SCG_NICCSR_NIC1DIV_MASK ((0xFUL) << SCG_NICCSR_NIC1DIV_SHIFT)
|
||||
#define SCG_NICCSR_NIC1EXTDIV_SHIFT (8)
|
||||
#define SCG_NICCSR_NIC1EXTDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1EXTDIV_SHIFT)
|
||||
#define SCG_NICCSR_NIC1BUSDIV_SHIFT (4)
|
||||
#define SCG_NICCSR_NIC1BUSDIV_MASK ((0xFUL) << SCG_NICCSR_NIC1BUSDIV_SHIFT)
|
||||
|
||||
/* SCG Slow IRC Control Status Register */
|
||||
#define SCG_SIRC_CSR_SIRCVLD_SHIFT (24)
|
||||
#define SCG_SIRC_CSR_SIRCVLD_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCVLD_SHIFT)
|
||||
|
||||
#define SCG_SIRC_CSR_SIRCEN_SHIFT (0)
|
||||
#define SCG_SIRC_CSR_SIRCEN_MASK ((0x1UL) << SCG_SIRC_CSR_SIRCEN_SHIFT)
|
||||
|
||||
/* SCG Slow IRC Configuration Register */
|
||||
#define SCG_SIRCCFG_RANGE_SHIFT (0)
|
||||
#define SCG_SIRCCFG_RANGE_MASK ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
|
||||
#define SCG_SIRCCFG_RANGE_4M ((0x0UL) << SCG_SIRCCFG_RANGE_SHIFT)
|
||||
#define SCG_SIRCCFG_RANGE_16M ((0x1UL) << SCG_SIRCCFG_RANGE_SHIFT)
|
||||
|
||||
/* SCG Slow IRC Divide Register */
|
||||
#define SCG_SIRCDIV_DIV3_SHIFT (16)
|
||||
#define SCG_SIRCDIV_DIV3_MASK ((0x7UL) << SCG_SIRCDIV_DIV3_SHIFT)
|
||||
|
||||
#define SCG_SIRCDIV_DIV2_SHIFT (8)
|
||||
#define SCG_SIRCDIV_DIV2_MASK ((0x7UL) << SCG_SIRCDIV_DIV2_SHIFT)
|
||||
|
||||
#define SCG_SIRCDIV_DIV1_SHIFT (0)
|
||||
#define SCG_SIRCDIV_DIV1_MASK ((0x7UL) << SCG_SIRCDIV_DIV1_SHIFT)
|
||||
/*
|
||||
* FIRC/SIRC DIV1 ==> xIRC_PLAT_CLK
|
||||
* FIRC/SIRC DIV2 ==> xIRC_BUS_CLK
|
||||
* FIRC/SIRC DIV3 ==> xIRC_SLOW_CLK
|
||||
*/
|
||||
|
||||
/* SCG Fast IRC Control Status Register */
|
||||
#define SCG_FIRC_CSR_FIRCVLD_SHIFT (24)
|
||||
#define SCG_FIRC_CSR_FIRCVLD_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCVLD_SHIFT)
|
||||
|
||||
#define SCG_FIRC_CSR_FIRCEN_SHIFT (0)
|
||||
#define SCG_FIRC_CSR_FIRCEN_MASK ((0x1UL) << SCG_FIRC_CSR_FIRCEN_SHIFT)
|
||||
|
||||
/* SCG Fast IRC Divide Register */
|
||||
#define SCG_FIRCDIV_DIV3_SHIFT (16)
|
||||
#define SCG_FIRCDIV_DIV3_MASK ((0x7UL) << SCG_FIRCDIV_DIV3_SHIFT)
|
||||
|
||||
#define SCG_FIRCDIV_DIV2_SHIFT (8)
|
||||
#define SCG_FIRCDIV_DIV2_MASK ((0x7UL) << SCG_FIRCDIV_DIV2_SHIFT)
|
||||
|
||||
#define SCG_FIRCDIV_DIV1_SHIFT (0)
|
||||
#define SCG_FIRCDIV_DIV1_MASK ((0x7UL) << SCG_FIRCDIV_DIV1_SHIFT)
|
||||
|
||||
#define SCG_FIRCCFG_RANGE_SHIFT (0)
|
||||
#define SCG_FIRCCFG_RANGE_MASK ((0x3UL) << SCG_FIRCCFG_RANGE_SHIFT)
|
||||
|
||||
#define SCG_FIRCCFG_RANGE_SHIFT (0)
|
||||
#define SCG_FIRCCFG_RANGE_48M ((0x0UL) << SCG_FIRCCFG_RANGE_SHIFT)
|
||||
|
||||
/* SCG System OSC Control Status Register */
|
||||
#define SCG_SOSC_CSR_SOSCVLD_SHIFT (24)
|
||||
#define SCG_SOSC_CSR_SOSCVLD_MASK ((0x1UL) << SCG_SOSC_CSR_SOSCVLD_SHIFT)
|
||||
|
||||
/* SCG Fast IRC Divide Register */
|
||||
#define SCG_SOSCDIV_DIV3_SHIFT (16)
|
||||
#define SCG_SOSCDIV_DIV3_MASK ((0x7UL) << SCG_SOSCDIV_DIV3_SHIFT)
|
||||
|
||||
#define SCG_SOSCDIV_DIV2_SHIFT (8)
|
||||
#define SCG_SOSCDIV_DIV2_MASK ((0x7UL) << SCG_SOSCDIV_DIV2_SHIFT)
|
||||
|
||||
#define SCG_SOSCDIV_DIV1_SHIFT (0)
|
||||
#define SCG_SOSCDIV_DIV1_MASK ((0x7UL) << SCG_SOSCDIV_DIV1_SHIFT)
|
||||
|
||||
/* SCG RTC OSC Control Status Register */
|
||||
#define SCG_ROSC_CSR_ROSCVLD_SHIFT (24)
|
||||
#define SCG_ROSC_CSR_ROSCVLD_MASK ((0x1UL) << SCG_ROSC_CSR_ROSCVLD_SHIFT)
|
||||
|
||||
#define SCG_SPLL_CSR_SPLLVLD_SHIFT (24)
|
||||
#define SCG_SPLL_CSR_SPLLVLD_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLVLD_SHIFT)
|
||||
#define SCG_SPLL_CSR_SPLLEN_SHIFT (0)
|
||||
#define SCG_SPLL_CSR_SPLLEN_MASK ((0x1UL) << SCG_SPLL_CSR_SPLLEN_SHIFT)
|
||||
#define SCG_APLL_CSR_APLLEN_SHIFT (0)
|
||||
#define SCG_APLL_CSR_APLLEN_MASK (0x1UL)
|
||||
#define SCG_APLL_CSR_APLLVLD_MASK (0x01000000)
|
||||
|
||||
#define SCG_UPLL_CSR_UPLLVLD_MASK (0x01000000)
|
||||
|
||||
|
||||
#define SCG_PLL_PFD3_GATE_MASK (0x80000000)
|
||||
#define SCG_PLL_PFD2_GATE_MASK (0x00800000)
|
||||
#define SCG_PLL_PFD1_GATE_MASK (0x00008000)
|
||||
#define SCG_PLL_PFD0_GATE_MASK (0x00000080)
|
||||
#define SCG_PLL_PFD3_VALID_MASK (0x40000000)
|
||||
#define SCG_PLL_PFD2_VALID_MASK (0x00400000)
|
||||
#define SCG_PLL_PFD1_VALID_MASK (0x00004000)
|
||||
#define SCG_PLL_PFD0_VALID_MASK (0x00000040)
|
||||
|
||||
#define SCG_PLL_PFD0_FRAC_SHIFT (0)
|
||||
#define SCG_PLL_PFD0_FRAC_MASK ((0x3F) << SCG_PLL_PFD0_FRAC_SHIFT)
|
||||
#define SCG_PLL_PFD1_FRAC_SHIFT (8)
|
||||
#define SCG_PLL_PFD1_FRAC_MASK ((0x3F) << SCG_PLL_PFD1_FRAC_SHIFT)
|
||||
#define SCG_PLL_PFD2_FRAC_SHIFT (16)
|
||||
#define SCG_PLL_PFD2_FRAC_MASK ((0x3F) << SCG_PLL_PFD2_FRAC_SHIFT)
|
||||
#define SCG_PLL_PFD3_FRAC_SHIFT (24)
|
||||
#define SCG_PLL_PFD3_FRAC_MASK ((0x3F) << SCG_PLL_PFD3_FRAC_SHIFT)
|
||||
|
||||
#define SCG_PLL_CFG_POSTDIV2_SHIFT (28)
|
||||
#define SCG_PLL_CFG_POSTDIV2_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV2_SHIFT)
|
||||
#define SCG_PLL_CFG_POSTDIV1_SHIFT (24)
|
||||
#define SCG_PLL_CFG_POSTDIV1_MASK ((0xFUL) << SCG_PLL_CFG_POSTDIV1_SHIFT)
|
||||
#define SCG_PLL_CFG_MULT_SHIFT (16)
|
||||
#define SCG1_SPLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
|
||||
#define SCG_APLL_CFG_MULT_MASK ((0x7FUL) << SCG_PLL_CFG_MULT_SHIFT)
|
||||
#define SCG_PLL_CFG_PFDSEL_SHIFT (14)
|
||||
#define SCG_PLL_CFG_PFDSEL_MASK ((0x3UL) << SCG_PLL_CFG_PFDSEL_SHIFT)
|
||||
#define SCG_PLL_CFG_PREDIV_SHIFT (8)
|
||||
#define SCG_PLL_CFG_PREDIV_MASK ((0x7UL) << SCG_PLL_CFG_PREDIV_SHIFT)
|
||||
#define SCG_PLL_CFG_BYPASS_SHIFT (2)
|
||||
/* 0: SPLL, 1: bypass */
|
||||
#define SCG_PLL_CFG_BYPASS_MASK ((0x1UL) << SCG_PLL_CFG_BYPASS_SHIFT)
|
||||
#define SCG_PLL_CFG_PLLSEL_SHIFT (1)
|
||||
/* 0: pll, 1: pfd */
|
||||
#define SCG_PLL_CFG_PLLSEL_MASK ((0x1UL) << SCG_PLL_CFG_PLLSEL_SHIFT)
|
||||
#define SCG_PLL_CFG_CLKSRC_SHIFT (0)
|
||||
/* 0: Sys-OSC, 1: FIRC */
|
||||
#define SCG_PLL_CFG_CLKSRC_MASK ((0x1UL) << SCG_PLL_CFG_CLKSRC_SHIFT)
|
||||
#define SCG0_SPLL_CFG_MULT_SHIFT (17)
|
||||
/* 0: Multiplier = 20, 1: Multiplier = 22 */
|
||||
#define SCG0_SPLL_CFG_MULT_MASK ((0x1UL) << SCG0_SPLL_CFG_MULT_SHIFT)
|
||||
|
||||
#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6)
|
||||
#define PLL_USB_PWR_MASK (0x01 << 12)
|
||||
#define PLL_USB_ENABLE_MASK (0x01 << 13)
|
||||
#define PLL_USB_BYPASS_MASK (0x01 << 16)
|
||||
#define PLL_USB_REG_ENABLE_MASK (0x01 << 21)
|
||||
#define PLL_USB_DIV_SEL_MASK (0x07 << 22)
|
||||
#define PLL_USB_LOCK_MASK (0x01 << 31)
|
||||
|
||||
enum scg_clk {
|
||||
SCG_SOSC_CLK,
|
||||
SCG_FIRC_CLK,
|
||||
SCG_SIRC_CLK,
|
||||
SCG_ROSC_CLK,
|
||||
SCG_SIRC_DIV1_CLK,
|
||||
SCG_SIRC_DIV2_CLK,
|
||||
SCG_SIRC_DIV3_CLK,
|
||||
SCG_FIRC_DIV1_CLK,
|
||||
SCG_FIRC_DIV2_CLK,
|
||||
SCG_FIRC_DIV3_CLK,
|
||||
SCG_SOSC_DIV1_CLK,
|
||||
SCG_SOSC_DIV2_CLK,
|
||||
SCG_SOSC_DIV3_CLK,
|
||||
SCG_CORE_CLK,
|
||||
SCG_BUS_CLK,
|
||||
SCG_SPLL_PFD0_CLK,
|
||||
SCG_SPLL_PFD1_CLK,
|
||||
SCG_SPLL_PFD2_CLK,
|
||||
SCG_SPLL_PFD3_CLK,
|
||||
SCG_DDR_CLK,
|
||||
SCG_NIC0_CLK,
|
||||
SCG_GPU_CLK,
|
||||
SCG_NIC1_CLK,
|
||||
SCG_NIC1_BUS_CLK,
|
||||
SCG_NIC1_EXT_CLK,
|
||||
SCG_APLL_PFD0_CLK,
|
||||
SCG_APLL_PFD1_CLK,
|
||||
SCG_APLL_PFD2_CLK,
|
||||
SCG_APLL_PFD3_CLK,
|
||||
USB_PLL_OUT,
|
||||
MIPI_PLL_OUT
|
||||
};
|
||||
|
||||
enum scg_sys_src {
|
||||
SCG_SCS_SYS_OSC = 1,
|
||||
SCG_SCS_SLOW_IRC,
|
||||
SCG_SCS_FAST_IRC,
|
||||
SCG_SCS_RTC_OSC,
|
||||
SCG_SCS_AUX_PLL,
|
||||
SCG_SCS_SYS_PLL,
|
||||
SCG_SCS_USBPHY_PLL,
|
||||
};
|
||||
|
||||
/* PLL supported by i.mx7ulp */
|
||||
enum pll_clocks {
|
||||
PLL_M4_SPLL, /* M4 SPLL */
|
||||
PLL_M4_APLL, /* M4 APLL*/
|
||||
PLL_A7_SPLL, /* A7 SPLL */
|
||||
PLL_A7_APLL, /* A7 APLL */
|
||||
PLL_USB, /* USB PLL*/
|
||||
PLL_MIPI, /* MIPI PLL */
|
||||
};
|
||||
|
||||
typedef struct scg_regs {
|
||||
u32 verid; /* VERSION_ID */
|
||||
u32 param; /* PARAMETER */
|
||||
u32 rsvd11[2];
|
||||
|
||||
u32 csr; /* Clock Status Register */
|
||||
u32 rccr; /* Run Clock Control Register */
|
||||
u32 vccr; /* VLPR Clock Control Register */
|
||||
u32 hccr; /* HSRUN Clock Control Register */
|
||||
u32 clkoutcnfg; /* SCG CLKOUT Configuration Register */
|
||||
u32 rsvd12[3];
|
||||
u32 ddrccr; /* SCG DDR Clock Control Register */
|
||||
u32 rsvd13[3];
|
||||
u32 nicccr; /* NIC Clock Control Register */
|
||||
u32 niccsr; /* NIC Clock Status Register */
|
||||
u32 rsvd10[46];
|
||||
|
||||
u32 sosccsr; /* System OSC Control Status Register, offset 0x100 */
|
||||
u32 soscdiv; /* System OSC Divide Register */
|
||||
u32 sosccfg; /* System Oscillator Configuration Register */
|
||||
u32 sosctest; /* System Oscillator Test Register */
|
||||
u32 rsvd20[60];
|
||||
|
||||
u32 sirccsr; /* Slow IRC Control Status Register, offset 0x200 */
|
||||
u32 sircdiv; /* Slow IRC Divide Register */
|
||||
u32 sirccfg; /* Slow IRC Configuration Register */
|
||||
u32 sirctrim; /* Slow IRC Trim Register */
|
||||
u32 loptrim; /* Low Power Oscillator Trim Register */
|
||||
u32 sirctest; /* Slow IRC Test Register */
|
||||
u32 rsvd30[58];
|
||||
|
||||
u32 firccsr; /* Fast IRC Control Status Register, offset 0x300 */
|
||||
u32 fircdiv;
|
||||
u32 firccfg;
|
||||
u32 firctcfg; /* Fast IRC Trim Configuration Register */
|
||||
u32 firctriml; /* Fast IRC Trim Low Register */
|
||||
u32 firctrimh;
|
||||
u32 fircstat; /* Fast IRC Status Register */
|
||||
u32 firctest; /* Fast IRC Test Register */
|
||||
u32 rsvd40[56];
|
||||
|
||||
u32 rtccsr; /* RTC OSC Control Status Register, offset 0x400 */
|
||||
u32 rsvd50[63];
|
||||
|
||||
u32 apllcsr; /* Auxiliary PLL Control Status Register, offset 0x500 */
|
||||
u32 aplldiv; /* Auxiliary PLL Divider Register */
|
||||
u32 apllcfg; /* Auxiliary PLL Configuration Register */
|
||||
u32 apllpfd; /* Auxiliary PLL PFD Register */
|
||||
u32 apllnum; /* Auxiliary PLL Numerator Register */
|
||||
u32 aplldenom; /* Auxiliary PLL Denominator Register */
|
||||
u32 apllss; /* Auxiliary PLL Spread Spectrum Register */
|
||||
u32 rsvd60[55];
|
||||
u32 apllock_cnfg; /* Auxiliary PLL LOCK Configuration Register */
|
||||
u32 rsvd61[1];
|
||||
|
||||
u32 spllcsr; /* System PLL Control Status Register, offset 0x600 */
|
||||
u32 splldiv; /* System PLL Divide Register */
|
||||
u32 spllcfg; /* System PLL Configuration Register */
|
||||
u32 spllpfd; /* System PLL Test Register */
|
||||
u32 spllnum; /* System PLL Numerator Register */
|
||||
u32 splldenom; /* System PLL Denominator Register */
|
||||
u32 spllss; /* System PLL Spread Spectrum Register */
|
||||
u32 rsvd70[55];
|
||||
u32 spllock_cnfg; /* System PLL LOCK Configuration Register */
|
||||
u32 rsvd71[1];
|
||||
|
||||
u32 upllcsr; /* USB PLL Control Status Register, offset 0x700 */
|
||||
u32 uplldiv; /* USB PLL Divide Register */
|
||||
u32 upllcfg; /* USB PLL Configuration Register */
|
||||
} scg_t, *scg_p;
|
||||
|
||||
u32 scg_clk_get_rate(enum scg_clk clk);
|
||||
int scg_enable_pll_pfd(enum scg_clk clk, u32 frac);
|
||||
int scg_enable_usb_pll(bool usb_control);
|
||||
u32 decode_pll(enum pll_clocks pll);
|
||||
|
||||
void scg_a7_rccr_init(void);
|
||||
void scg_a7_spll_init(void);
|
||||
void scg_a7_ddrclk_init(void);
|
||||
void scg_a7_apll_init(void);
|
||||
void scg_a7_firc_init(void);
|
||||
void scg_a7_nicclk_init(void);
|
||||
void scg_a7_sys_clk_sel(enum scg_sys_src clk);
|
||||
void scg_a7_info(void);
|
||||
void scg_a7_soscdiv_init(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue