diff --git a/board/davinci/sysmobts_v2/sysmobts_v2.c b/board/davinci/sysmobts_v2/sysmobts_v2.c
index 9f7f162a7c..24d6e0b856 100644
--- a/board/davinci/sysmobts_v2/sysmobts_v2.c
+++ b/board/davinci/sysmobts_v2/sysmobts_v2.c
@@ -36,9 +36,6 @@
 #define DAVINCI_PLLM      (0x01C40910)	/* PLL 1 Multiplier */
 #define DAVINCI_AWCCR     (0x01E00004)	/* EMIF-A async wait cycle config register. */
 #define DAVINCI_AWCCR_VAL (0x000000FF)	/* EMIF-A async wait cycle config register value. */
-#define DAVINCI_A1CR      (0x01E00010)	/* EMIF-A CS2 config register. */
-#define DAVINCI_A1CR_VAL  (0x44502280)	/* EMIF-A CS2 value for NAND. */
-#define DAVINCI_A1CR_VAL8 (0x44522290)	/* EMIF-A CS2 value for NAND. */
 #define DAVINCI_A2CR      (0x01E00014)	/* EMIF-A CS3 config register. */
 #define DAVINCI_A2CR_VAL  (0x00430491)	/* EMIF-A CS3 value for FPGA.  */
 #define DAVINCI_A2CR_VAL8 (0x00630591)	/* EMIF-A CS3 value for FPGA.  */
@@ -104,19 +101,11 @@ int board_init(void)
 
 	/* DM644X @ 594/297 MHz */
 	if ( (REG(DAVINCI_PLLM) & 0x0FF) < 22 ) {
-
-		/* Configure AEMIF CS2 (nand) */
-		REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL;
-
 		/* Configure AEMIF CS3 (fpga) */
 		REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL;
 
 	/* DM644X @ 810/405 MHz	*/
 	} else {
-
-		/* Configure AEMIF CS2 (nand) */
-		REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL8;
-
 		/* Configure AEMIF CS3 (fpga) */
 		REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL8;
 	}