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sysmobts-v2: UBL is setting the right A1CR values right now 

Remove the code to set the A1CR values. UBL is now doing it for all
the flash chips supported by the sysmobts.
This commit is contained in:
Holger Hans Peter Freyther 2014-07-11 09:39:56 +02:00 committed by Holger Hans Peter Freyther
parent c532cbd899
commit cea9019e5b
1 changed files with 0 additions and 11 deletions
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11
board/davinci/sysmobts_v2/sysmobts_v2.c
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@ -36,9 +36,6 @@
#define DAVINCI_PLLM (0x01C40910) /* PLL 1 Multiplier */
#define DAVINCI_AWCCR (0x01E00004) /* EMIF-A async wait cycle config register. */
#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
#define DAVINCI_A1CR (0x01E00010) /* EMIF-A CS2 config register. */
#define DAVINCI_A1CR_VAL (0x44502280) /* EMIF-A CS2 value for NAND. */
#define DAVINCI_A1CR_VAL8 (0x44522290) /* EMIF-A CS2 value for NAND. */
#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
@ -104,19 +101,11 @@ int board_init(void)
/* DM644X @ 594/297 MHz */
if ( (REG(DAVINCI_PLLM) & 0x0FF) < 22 ) {
/* Configure AEMIF CS2 (nand) */
REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL;
/* Configure AEMIF CS3 (fpga) */
REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL;
/* DM644X @ 810/405 MHz */
} else {
/* Configure AEMIF CS2 (nand) */
REG(DAVINCI_A1CR) = DAVINCI_A1CR_VAL8;
/* Configure AEMIF CS3 (fpga) */
REG(DAVINCI_A2CR) = DAVINCI_A2CR_VAL8;
}