arm: atmel: sama5d3: spl boot from fat fs SD card
Enable Atmel sama5d3xek boart spl boot support, which can load u-boot from SD card with FAT file system. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Bo Shen
Andreas Bießmann
parent
9d9289cb31
commit
c5e8885aab
|
|
@ -12,7 +12,7 @@ obj-y += cache_v7.o
|
|||
obj-y += cpu.o
|
||||
obj-y += syslib.o
|
||||
|
||||
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
|
||||
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
|
||||
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
|
||||
obj-y += lowlevel_init.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -8,4 +8,4 @@
|
|||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-$(CONFIG_SPL_BUILD) += mpddrc.o
|
||||
obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,90 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/at91_common.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/arch/at91_wdt.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <spl.h>
|
||||
|
||||
static void at91_disable_wdt(void)
|
||||
{
|
||||
struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
|
||||
|
||||
writel(AT91_WDT_MR_WDDIS, &wdt->mr);
|
||||
}
|
||||
|
||||
void at91_plla_init(u32 pllar)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
|
||||
writel(pllar, &pmc->pllar);
|
||||
while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
|
||||
;
|
||||
}
|
||||
|
||||
void at91_mck_init(u32 mckr)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 tmp;
|
||||
|
||||
tmp = readl(&pmc->mckr);
|
||||
tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
|
||||
AT91_PMC_MCKR_MDIV_MASK |
|
||||
AT91_PMC_MCKR_PLLADIV_2);
|
||||
tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
|
||||
AT91_PMC_MCKR_MDIV_MASK |
|
||||
AT91_PMC_MCKR_PLLADIV_2);
|
||||
writel(tmp, &pmc->mckr);
|
||||
|
||||
while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
return BOOT_DEVICE_MMC1;
|
||||
#endif
|
||||
return BOOT_DEVICE_NONE;
|
||||
}
|
||||
|
||||
u32 spl_boot_mode(void)
|
||||
{
|
||||
switch (spl_boot_device()) {
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
case BOOT_DEVICE_MMC1:
|
||||
return MMCSD_MODE_FAT;
|
||||
break;
|
||||
#endif
|
||||
case BOOT_DEVICE_NONE:
|
||||
default:
|
||||
hang();
|
||||
}
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
/* disable watchdog */
|
||||
at91_disable_wdt();
|
||||
|
||||
/* PMC configuration */
|
||||
at91_pmc_init();
|
||||
|
||||
at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
|
||||
|
||||
timer_init();
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
mem_init();
|
||||
}
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Texas Instruments, <www.ti.com>
|
||||
* Aneesh V <aneesh@ti.com>
|
||||
*
|
||||
* (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
|
||||
LENGTH = CONFIG_SPL_MAX_SIZE }
|
||||
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
|
||||
LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
__start = .;
|
||||
arch/arm/cpu/armv7/start.o (.text*)
|
||||
*(.text*)
|
||||
} >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
|
||||
|
||||
. = ALIGN(4);
|
||||
__image_copy_end = .;
|
||||
_end = .;
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end = .;
|
||||
} >.sdram
|
||||
}
|
||||
|
|
@ -22,5 +22,9 @@ void at91_spi1_hw_init(unsigned long cs_mask);
|
|||
void at91_udp_hw_init(void);
|
||||
void at91_uhp_hw_init(void);
|
||||
void at91_lcd_hw_init(void);
|
||||
void at91_plla_init(u32 pllar);
|
||||
void at91_mck_init(u32 mckr);
|
||||
void at91_pmc_init(void);
|
||||
void mem_init(void);
|
||||
|
||||
#endif /* AT91_COMMON_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Atmel Corporation
|
||||
* Bo Shen <voice.shen@atmel.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef _ASM_ARCH_SPL_H_
|
||||
#define _ASM_ARCH_SPL_H_
|
||||
|
||||
enum {
|
||||
BOOT_DEVICE_NONE,
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
BOOT_DEVICE_MMC1,
|
||||
BOOT_DEVICE_MMC2,
|
||||
BOOT_DEVICE_MMC2_2,
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -20,6 +20,9 @@
|
|||
#include <micrel.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <spl.h>
|
||||
#include <asm/arch/atmel_mpddrc.h>
|
||||
#include <asm/arch/at91_wdt.h>
|
||||
|
||||
#ifdef CONFIG_USB_GADGET_ATMEL_USBA
|
||||
#include <asm/arch/atmel_usba_udc.h>
|
||||
|
|
@ -296,3 +299,85 @@ void spi_cs_deactivate(struct spi_slave *slave)
|
|||
}
|
||||
}
|
||||
#endif /* CONFIG_ATMEL_SPI */
|
||||
|
||||
/* SPL */
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
void spl_board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
sama5d3xek_mci_hw_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ddr2_conf(struct atmel_mpddr *ddr2)
|
||||
{
|
||||
ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
|
||||
|
||||
ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
|
||||
ATMEL_MPDDRC_CR_NR_ROW_14 |
|
||||
ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
|
||||
ATMEL_MPDDRC_CR_ENRDM_ON |
|
||||
ATMEL_MPDDRC_CR_NB_8BANKS |
|
||||
ATMEL_MPDDRC_CR_NDQS_DISABLED |
|
||||
ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
|
||||
ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
|
||||
/*
|
||||
* As the DDR2-SDRAm device requires a refresh time is 7.8125us
|
||||
* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
|
||||
*/
|
||||
ddr2->rtr = 0x411;
|
||||
|
||||
ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
|
||||
8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
|
||||
|
||||
ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
|
||||
200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
|
||||
28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
|
||||
26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
|
||||
|
||||
ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
|
||||
2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
|
||||
7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
|
||||
8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
|
||||
}
|
||||
|
||||
void mem_init(void)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
struct atmel_mpddr ddr2;
|
||||
|
||||
ddr2_conf(&ddr2);
|
||||
|
||||
/* enable MPDDR clock */
|
||||
at91_periph_clk_enable(ATMEL_ID_MPDDRC);
|
||||
writel(0x4, &pmc->scer);
|
||||
|
||||
/* DDRAM2 Controller initialize */
|
||||
ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
|
||||
}
|
||||
|
||||
void at91_pmc_init(void)
|
||||
{
|
||||
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
|
||||
u32 tmp;
|
||||
|
||||
tmp = AT91_PMC_PLLAR_29 |
|
||||
AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
|
||||
AT91_PMC_PLLXR_MUL(43) |
|
||||
AT91_PMC_PLLXR_DIV(1);
|
||||
at91_plla_init(tmp);
|
||||
|
||||
writel(0x3 << 8, &pmc->pllicpr);
|
||||
|
||||
tmp = AT91_PMC_MCKR_MDIV_4 |
|
||||
AT91_PMC_MCKR_CSS_PLLA;
|
||||
at91_mck_init(tmp);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,7 +24,10 @@
|
|||
#define CONFIG_AT91FAMILY
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#endif
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
|
||||
|
|
@ -93,8 +96,12 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
|
||||
#define CONFIG_SYS_SDRAM_SIZE 0x20000000
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x310000
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
|
||||
#endif
|
||||
|
||||
/* SerialFlash */
|
||||
#define CONFIG_CMD_SF
|
||||
|
|
@ -235,4 +242,31 @@
|
|||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
|
||||
/* SPL */
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_FRAMEWORK
|
||||
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||
#define CONFIG_SPL_MAX_SIZE 0x10000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
#define CONFIG_SPL_GPIO_SUPPORT
|
||||
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||
|
||||
#define CONFIG_SPL_BOARD_INIT
|
||||
#ifdef CONFIG_SYS_USE_MMC
|
||||
#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
|
||||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
|
||||
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
|
||||
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||
#define CONFIG_SPL_FAT_SUPPORT
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue