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arm, am335x: add support for 3 siemens boards 

add support for the am335x based boards from siemens:

dxr2:
  - DDR3 128MiB
  - NAND 256MiB
  - Ethernet with external Switch SMSC LAN9303
  - no PMIC
  - internal Watchdog
  - DFU support

pxm2:
  - DDR2 512 MiB
  - NAND 1024 MiB
  - PMIC
  - PHY atheros ar803x
  - USB Host
  - internal Watchdog
  - DFU support

rut:
  - DDR3 256 MiB
  - NAND 256 MiB
  - PMIC
  - PHY natsemi dp83630
  - external Watchdog
  - DFU support

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Roger Meier <r.meier@siemens.com>
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Cc: Pascal Bach <pascal.bach@siemens.com>
Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Heiko Schocher 2013-08-19 16:39:01 +02:00 committed by Tom Rini
parent b26354cfd5
commit c0dcece7d9
23 changed files with 3434 additions and 0 deletions
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5
MAINTAINERS
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@ -1087,6 +1087,11 @@ Sergey Yanovich <ynvich@gmail.com>
lp8x4x xscale/pxa
Roger Meier <r.meier@siemens.com>
dxr2 ARM ARMV7 (AM335x SoC)
pxm2 ARM ARMV7 (AM335x SoC)
rut ARM ARMV7 (AM335x SoC)
-------------------------------------------------------------------------
Unknown / orphaned boards:

171
board/siemens/common/board.c Normal file
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/*
* Common board functions for siemens AM335X based boards
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* U-Boot file:/board/ti/am335x/board.c
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <watchdog.h>
#include "../common/factoryset.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux();
}
void sdram_init(void)
{
spl_siemens_board_init();
board_init_ddr();
return;
}
#endif /* #ifdef CONFIG_SPL_BUILD */
#ifndef CONFIG_SPL_BUILD
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif /* defined(CONFIG_HW_WATCHDOG) */
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_FACTORYSET
factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
#endif
gpmc_init();
#ifdef CONFIG_VIDEO
board_video_init();
#endif
return 0;
}
#endif /* #ifndef CONFIG_SPL_BUILD */
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
omap_nand_switch_ecc(1, 8);
return 0;
}
#endif
#ifndef CONFIG_SPL_BUILD
#if defined(BOARD_DFU_BUTTON_GPIO)
/*
* This command returns the status of the user button on
* Input - none
* Returns - 1 if button is held down
* 0 if button is not held down
*/
static int
do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int button = 0;
int gpio;
gpio = BOARD_DFU_BUTTON_GPIO;
gpio_request(gpio, "DFU");
gpio_direction_input(gpio);
if (gpio_get_value(gpio))
button = 1;
else
button = 0;
gpio_free(gpio);
if (!button) {
/* LED0 - RED=1: GPIO2_0 2*32 = 64 */
gpio_request(BOARD_DFU_BUTTON_LED, "");
gpio_direction_output(BOARD_DFU_BUTTON_LED, 1);
gpio_set_value(BOARD_DFU_BUTTON_LED, 1);
}
return button;
}
U_BOOT_CMD(
dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton,
"Return the status of the DFU button",
""
);
#endif
static int
do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("\n\n\n Go into infinite loop\n\n\n");
while (1)
;
return 0;
};
U_BOOT_CMD(
testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt,
"Sends U-Boot into infinite loop",
""
);
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
printf("Enable d-cache\n");
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif /* CONFIG_SYS_DCACHE_OFF */
#endif /* !CONFIG_SPL_BUILD */

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board/siemens/common/factoryset.c Normal file
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/*
*
* Read FactorySet information from EEPROM into global structure.
* (C) Copyright 2013 Siemens Schweiz AG
*
* SPDX-License-Identifier: GPL-2.0+
*/
#if !defined(CONFIG_SPL_BUILD)
#include <common.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/sys_proto.h>
#include <asm/unaligned.h>
#include <net.h>
#include <usbdescriptors.h>
#include "factoryset.h"
#define EEPR_PG_SZ 0x80
#define EEPROM_FATORYSET_OFFSET 0x400
#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ
/* Global variable that contains necessary information from FactorySet */
struct factorysetcontainer factory_dat;
#define fact_get_char(i) *((char *)&eeprom_buf[i])
static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2)
{
if (s1 == NULL)
return -1;
while (*s1 == fact_get_char(i2++))
if (*s1++ == '=')
return i2;
if (*s1 == '\0' && fact_get_char(i2-1) == '=')
return i2;
return -1;
}
static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name,
uchar *buf, int len)
{
int i, nxt = 0;
for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) {
int val, n;
for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) {
if (nxt >= size)
return -1;
}
val = fact_match(eeprom_buf, (uchar *)name, i);
if (val < 0)
continue;
/* found; copy out */
for (n = 0; n < len; ++n, ++buf) {
*buf = fact_get_char(val++);
if (*buf == '\0')
return n;
}
if (n)
*--buf = '\0';
printf("env_buf [%d bytes] too small for value of \"%s\"\n",
len, name);
return n;
}
return -1;
}
static
int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record,
uchar *name, uchar *buf, int len)
{
int ret = -1;
int i, nxt = 0;
int c;
unsigned char end = 0xff;
for (i = 0; fact_get_char(i) != end; i = nxt) {
nxt = i + 1;
if (fact_get_char(i) == '>') {
int pos;
int endpos;
int z;
c = strncmp((char *)&eeprom_buf[i + 1], (char *)record,
strlen((char *)record));
if (c == 0) {
/* record found */
pos = i + strlen((char *)record) + 2;
nxt = pos;
/* search for "<" */
c = -1;
for (z = pos; fact_get_char(z) != end; z++) {
if ((fact_get_char(z) == '<') ||
(fact_get_char(z) == '>')) {
endpos = z;
nxt = endpos;
c = 0;
break;
}
}
}
if (c == 0) {
/* end found -> call get_factory_val */
eeprom_buf[endpos] = end;
ret = get_factory_val(&eeprom_buf[pos],
size - pos, name, buf, len);
/* fix buffer */
eeprom_buf[endpos] = '<';
debug("%s: %s.%s = %s\n",
__func__, record, name, buf);
return ret;
}
}
}
return ret;
}
int factoryset_read_eeprom(int i2c_addr)
{
int i, pages = 0, size = 0;
unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
unsigned char *cp, *cp1;
#if defined(CONFIG_DFU_FUNCTION)
factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM;
factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM;
#endif
if (i2c_probe(i2c_addr))
goto err;
if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr)))
goto err;
if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) {
printf("FactorySet is not right in eeprom.\n");
return 1;
}
/* get FactorySet size */
size = (hdr[2] << 8) + hdr[3] + sizeof(hdr);
if (size > 0x3bfa)
size = 0x3bfa;
pages = size / EEPR_PG_SZ;
/*
* read the eeprom using i2c
* I can not read entire eeprom in once, so separate into several
* times. Furthermore, fetch eeprom take longer time, so we fetch
* data after every time we got a record from eeprom
*/
debug("Read eeprom page :\n");
for (i = 0; i < pages; i++)
if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2,
eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ))
goto err;
if (size % EEPR_PG_SZ)
if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2,
eeprom_buf + (pages * EEPR_PG_SZ),
(size % EEPR_PG_SZ)))
goto err;
/* we do below just for eeprom align */
for (i = 0; i < size; i++)
if (eeprom_buf[i] == '\n')
eeprom_buf[i] = 0;
/* skip header */
size -= sizeof(hdr);
cp = (uchar *)eeprom_buf + sizeof(hdr);
/* get mac address */
get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac",
buf, MAX_STRING_LENGTH);
cp1 = buf;
for (i = 0; i < 6; i++) {
factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16);
cp1 += 3;
}
#if defined(CONFIG_DFU_FUNCTION)
/* read vid and pid for dfu mode */
if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
(uchar *)"vid", buf,
MAX_STRING_LENGTH)) {
factory_dat.usb_vendor_id = simple_strtoul((char *)buf,
NULL, 16);
}
if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
(uchar *)"pid", buf,
MAX_STRING_LENGTH)) {
factory_dat.usb_product_id = simple_strtoul((char *)buf,
NULL, 16);
}
printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
factory_dat.usb_product_id);
#endif
if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
(uchar *)"id", buf,
MAX_STRING_LENGTH)) {
if (strncmp((const char *)buf, "PXM50", 5) == 0)
factory_dat.pxm50 = 1;
else
factory_dat.pxm50 = 0;
}
debug("PXM50: %d\n", factory_dat.pxm50);
#if defined(CONFIG_VIDEO)
if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
(uchar *)"name", factory_dat.disp_name,
MAX_STRING_LENGTH)) {
debug("display name: %s\n", factory_dat.disp_name);
}
#endif
return 0;
err:
printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
return 1;
}
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static int factoryset_mac_setenv(void)
{
uint8_t mac_addr[6];
debug("FactorySet: Set mac address\n");
if (is_valid_ether_addr(factory_dat.mac)) {
memcpy(mac_addr, factory_dat.mac, 6);
} else {
uint32_t mac_hi, mac_lo;
debug("Warning: FactorySet: <ethaddr> not set. Fallback to E-fuse\n");
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (!is_valid_ether_addr(mac_addr)) {
printf("Warning: ethaddr not set by FactorySet or E-fuse. Set <ethaddr> variable to overcome this.\n");
return -1;
}
}
eth_setenv_enetaddr("ethaddr", mac_addr);
return 0;
}
int factoryset_setenv(void)
{
int ret = 0;
if (factoryset_mac_setenv() < 0)
ret = -1;
return ret;
}
int g_dnl_bind_fixup(struct usb_device_descriptor *dev)
{
put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
return 0;
}
#endif /* defined(CONFIG_SPL_BUILD) */

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board/siemens/common/factoryset.h Normal file
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/*
* Common board functions for siemens AM335X based boards
* (C) Copyright 2013 Siemens Schweiz AG
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __FACTORYSET_H
#define __FACTORYSET_H
#define MAX_STRING_LENGTH 32
struct factorysetcontainer {
uchar mac[6];
int usb_vendor_id;
int usb_product_id;
int pxm50;
#if defined(CONFIG_VIDEO)
unsigned char disp_name[MAX_STRING_LENGTH];
#endif
};
int factoryset_read_eeprom(int i2c_addr);
int factoryset_setenv(void);
extern struct factorysetcontainer factory_dat;
#endif /* __FACTORYSET_H */

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board/siemens/dxr2/Makefile Normal file
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#
# Makefile
#
# (C) Copyright 2013 Siemens Schweiz AG
# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
ifdef CONFIG_SPL_BUILD
COBJS := mux.o
endif
COBJS += board.o
ifndef CONFIG_SPL_BUILD
COBJS += ../common/factoryset.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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board/siemens/dxr2/board.c Normal file
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/*
* Board functions for TI AM335X based dxr2 board
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
*
* Board functions for TI AM335X based boards
* u-boot:/board/ti/am335x/board.c
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
const struct ddr3_data ddr3_default = {
0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
0x00000618,
};
static void set_default_ddr3_timings(void)
{
printf("Set default DDR3 settings\n");
settings.ddr3 = ddr3_default;
}
static void print_ddr3_timings(void)
{
printf("\n\nDDR3 Timing parameters:\n");
printf("Diff Eeprom Default\n");
PRINTARGS(magic);
PRINTARGS(version);
PRINTARGS(ddr3_sratio);
PRINTARGS(iclkout);
PRINTARGS(dt0rdsratio0);
PRINTARGS(dt0wdsratio0);
PRINTARGS(dt0fwsratio0);
PRINTARGS(dt0wrsratio0);
PRINTARGS(sdram_tim1);
PRINTARGS(sdram_tim2);
PRINTARGS(sdram_tim3);
PRINTARGS(emif_ddr_phy_ctlr_1);
PRINTARGS(sdram_config);
PRINTARGS(ref_ctrl);
}
static void print_chip_data(void)
{
printf("\n");
printf("Device: '%s'\n", settings.chip.sdevname);
printf("HW version: '%s'\n", settings.chip.shwver);
}
#endif /* CONFIG_SPL_BUILD */
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(void)
{
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
return 1;
}
#ifdef CONFIG_SPL_BUILD
/* Read Siemens eeprom data (DDR3) */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
(uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
set_default_ddr3_timings();
}
/* Read Siemens eeprom data (CHIP) */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
(uchar *)&settings.chip, sizeof(settings.chip)))
printf("Could not read chip settings\n");
if (ddr3_default.magic == settings.ddr3.magic &&
ddr3_default.version == settings.ddr3.version) {
printf("Using DDR3 settings from EEPROM\n");
} else {
if (ddr3_default.magic != settings.ddr3.magic)
printf("Error: No valid DDR3 data in eeprom.\n");
if (ddr3_default.version != settings.ddr3.version)
printf("Error: DDR3 data version does not match.\n");
printf("Using default settings\n");
set_default_ddr3_timings();
}
if (MAGIC_CHIP == settings.chip.magic) {
printf("Valid chip data in eeprom\n");
print_chip_data();
} else {
printf("Error: No chip data in eeprom\n");
}
print_ddr3_timings();
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs dxr2_ddr3_emif_reg_data = {
.zq_config = 0x50074BE4,
};
struct ddr_data dxr2_ddr3_data = {
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
.cmd0dldiff = 0,
.cmd1dldiff = 0,
.cmd2dldiff = 0,
};
/* pass values from eeprom */
dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)
{
return;
}
#endif /* if def CONFIG_SPL_BUILD */
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_MII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 4,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
int n = 0;
int rv;
factoryset_setenv();
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
return n;
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
#include "../common/board.c"

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/*
* board.h
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \
settings.ddr3.x, ddr3_default.x
#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y))
#define MAGIC_CHIP 0x50494843
/* Automatic generated definition */
/* Wed, 19 Jun 2013 10:57:48 +0200 */
/* From file: draco/ddr3-data-micron.txt */
struct ddr3_data {
unsigned int magic; /* 0x33524444 */
unsigned int version; /* 0x56312e33 */
unsigned short int ddr3_sratio; /* 0x0100 */
unsigned short int iclkout; /* 0x0001 */
unsigned short int dt0rdsratio0; /* 0x003A */
unsigned short int dt0wdsratio0; /* 0x008A */
unsigned short int dt0fwsratio0; /* 0x010B */
unsigned short int dt0wrsratio0; /* 0x00C4 */
unsigned int sdram_tim1; /* 0x0888A39B */
unsigned int sdram_tim2; /* 0x26247FDA */
unsigned int sdram_tim3; /* 0x501F821F */
unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */
unsigned int sdram_config; /* 0x61C04AB2 */
unsigned int ref_ctrl; /* 0x00000618 */
};
struct chip_data {
unsigned int magic;
char sdevname[16];
char shwver[7];
};
struct dxr2_baseboard_id {
struct ddr3_data ddr3;
struct chip_data chip;
};
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_uart1_pin_mux(void);
void enable_uart2_pin_mux(void);
void enable_uart3_pin_mux(void);
void enable_uart4_pin_mux(void);
void enable_uart5_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(void);
#endif

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/*
* pinmux setup for siemens dxr2 board
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* u-boot:/board/ti/am335x/mux.c
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
static struct module_pin_mux gpios_pin_mux[] = {
/* DFU button GPIO0_27*/
{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
{OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */
{OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */
{-1},
};
static struct module_pin_mux ethernet_pin_mux[] = {
{OFFSET(mii1_col), (MODE(3) | RXACTIVE)},
{OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_txen), (MODE(1))},
{OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)},
{OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_txd1), (MODE(1))},
{OFFSET(mii1_txd0), (MODE(1))},
{OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxd2), (MODE(1))},
{OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
{OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
{OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_uart3_pin_mux(void)
{
configure_module_pin_mux(uart3_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_board_pin_mux(void)
{
enable_uart3_pin_mux();
configure_module_pin_mux(nand_pin_mux);
configure_module_pin_mux(ethernet_pin_mux);
configure_module_pin_mux(gpios_pin_mux);
}

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#
# Makefile
#
# (C) Copyright 2013 Siemens Schweiz AG
# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
ifdef CONFIG_SPL_BUILD
COBJS := mux.o
endif
COBJS += board.o
ifndef CONFIG_SPL_BUILD
COBJS += ../common/factoryset.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* Board functions for TI AM335X based pxm2 board
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* u-boot:/board/ti/am335x/board.c
*
* Board functions for TI AM335X based boards
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include "../../../drivers/video/da8xx-fb.h"
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
#include "pmic.h"
#include <nand.h>
#include <bmp_layout.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs pxm2_ddr3_emif_reg_data = {
.sdram_config = 0x41805332,
.sdram_tim1 = 0x666b3c9,
.sdram_tim2 = 0x243631ca,
.sdram_tim3 = 0x33f,
.emif_ddr_phy_ctlr_1 = 0x100005,
.zq_config = 0,
.ref_ctrl = 0x81a,
};
struct ddr_data pxm2_ddr3_data = {
.datardsratio0 = 0x81204812,
.datawdsratio0 = 0,
.datafwsratio0 = 0x8020080,
.datawrsratio0 = 0x4010040,
.datauserank0delay = 1,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0,
.cmd0iclkout = 0,
.cmd1csratio = 0x80,
.cmd1dldiff = 0,
.cmd1iclkout = 0,
.cmd2csratio = 0x80,
.cmd2dldiff = 0,
.cmd2iclkout = 0,
};
config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
&pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
}
/*
* voltage switching for MPU frequency switching.
* @module = mpu - 0, core - 1
* @vddx_op_vol_sel = vdd voltage to set
*/
#define MPU 0
#define CORE 1
int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
{
uchar buf[4];
unsigned int reg_offset;
if (module == MPU)
reg_offset = PMIC_VDD1_OP_REG;
else
reg_offset = PMIC_VDD2_OP_REG;
/* Select VDDx OP */
if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
buf[0] &= ~PMIC_OP_REG_CMD_MASK;
if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
/* Configure VDDx OP Voltage */
if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
buf[0] &= ~PMIC_OP_REG_SEL_MASK;
buf[0] |= vddx_op_vol_sel;
if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
return 1;
return 0;
}
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_mpu_pxm2 = {
720, OSC-1, 1, -1, -1, -1, -1};
void spl_siemens_board_init(void)
{
uchar buf[4];
/*
* pxm2 PMIC code. All boards currently want an MPU voltage
* of 1.2625V and CORE voltage of 1.1375V to operate at
* 720MHz.
*/
if (i2c_probe(PMIC_CTRL_I2C_ADDR))
return;
/* VDD1/2 voltage selection register access by control i/f */
if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
return;
buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
return;
/* Frequency switching for OPP 120 */
if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
printf("voltage update failed\n");
}
}
#endif /* if def CONFIG_SPL_BUILD */
int read_eeprom(void)
{
/* nothing ToDo here for this board */
return 0;
}
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 1,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 4,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
int n = 0;
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_FACTORYSET
int rv;
if (!is_valid_ether_addr(factory_dat.mac))
printf("Error: no valid mac address\n");
else
eth_setenv_enetaddr("ethaddr", factory_dat.mac);
#endif /* #ifdef CONFIG_FACTORYSET */
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel(RGMII_MODE_ENABLE , &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
return n;
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct da8xx_panel lcd_panels[] = {
/* AUO G156XW01 V1 */
[0] = {
.name = "AUO_G156XW01_V1",
.width = 1376,
.height = 768,
.hfp = 14,
.hbp = 64,
.hsw = 56,
.vfp = 1,
.vbp = 28,
.vsw = 3,
.pxl_clk = 60000000,
.invert_pxl_clk = 0,
},
/* AUO B101EVN06 V0 */
[1] = {
.name = "AUO_B101EVN06_V0",
.width = 1280,
.height = 800,
.hfp = 52,
.hbp = 84,
.hsw = 36,
.vfp = 3,
.vbp = 14,
.vsw = 6,
.pxl_clk = 60000000,
.invert_pxl_clk = 0,
},
/*
* Settings from factoryset
* stored in EEPROM
*/
[2] = {
.name = "factoryset",
.width = 0,
.height = 0,
.hfp = 0,
.hbp = 0,
.hsw = 0,
.vfp = 0,
.vbp = 0,
.vsw = 0,
.pxl_clk = 60000000,
.invert_pxl_clk = 0,
},
};
static const struct display_panel disp_panel = {
WVGA,
32,
16,
COLOR_ACTIVE,
};
static const struct lcd_ctrl_config lcd_cfg = {
&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 32,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
};
static int set_gpio(int gpio, int state)
{
gpio_request(gpio, "temp");
gpio_direction_output(gpio, state);
gpio_set_value(gpio, state);
gpio_free(gpio);
return 0;
}
static int enable_backlight(void)
{
set_gpio(BOARD_LCD_POWER, 1);
set_gpio(BOARD_BACK_LIGHT, 1);
set_gpio(BOARD_TOUCH_POWER, 1);
return 0;
}
static int enable_pwm(void)
{
struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
struct pwmss_ecap_regs *ecap;
int ticks = PWM_TICKS;
int duty = PWM_DUTY;
ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
/* enable clock */
setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
/* TimeStam Counter register */
writel(0xdb9, &ecap->tsctr);
/* config period */
writel(ticks - 1, &ecap->cap3);
writel(ticks - 1, &ecap->cap1);
setbits_le16(&ecap->ecctl2,
(ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
/* config duty */
writel(duty, &ecap->cap2);
writel(duty, &ecap->cap4);
/* start */
setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
return 0;
}
static struct dpll_regs dpll_lcd_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x98,
.cm_idlest_dpll = CM_WKUP + 0x48,
.cm_clksel_dpll = CM_WKUP + 0x54,
};
/* no console on this board */
int board_cfb_skip(void)
{
return 1;
}
#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
#define PLL_GET_N(v) (v & 0x7f)
static int get_clk(struct dpll_regs *dpll_regs)
{
unsigned int val;
unsigned int m, n;
int f = 0;
val = readl(dpll_regs->cm_clksel_dpll);
m = PLL_GET_M(val);
n = PLL_GET_N(val);
f = (m * V_OSCK) / n;
return f;
};
int clk_get(int clk)
{
return get_clk(&dpll_lcd_regs);
};
static int conf_disp_pll(int m, int n)
{
struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
u32 *const clk_domains[] = {
&cmper->lcdclkctrl,
0
};
u32 *const clk_modules_explicit_en[] = {
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
&cmper->epwmss0clkctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
writel(0x0, &cmdpll->clklcdcpixelclk);
do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
return 0;
}
static int board_video_init(void)
{
/* set 300 MHz */
conf_disp_pll(25, 2);
if (factory_dat.pxm50)
da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
else
da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
enable_pwm();
enable_backlight();
return 0;
}
#endif
#include "../common/board.c"

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/*
* board.h
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(void);
#endif

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/*
* pinmux setup for siemens pxm2 board
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* u-boot:/board/ti/am335x/mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */
{-1},
};
#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */
{OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */
{-1},
};
#endif
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
#ifndef CONFIG_NO_ETH
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux rgmii2_pin_mux[] = {
{OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */
{OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */
{OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */
{OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */
{OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */
{OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */
{OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */
{OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */
{OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */
{OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */
{OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
#endif
#ifdef CONFIG_MMC
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */
{-1},
};
#endif
static struct module_pin_mux lcdc_pin_mux[] = {
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */
{OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */
{OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */
{OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */
{OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */
{OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */
{OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */
{OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */
{OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */
{OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */
{OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */
{OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */
{OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */
{-1},
};
static struct module_pin_mux ecap0_pin_mux[] = {
{OFFSET(ecap0_in_pwm0_out), (MODE(0))},
{-1},
};
static struct module_pin_mux gpio_pin_mux[] = {
{OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/
{OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */
{OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */
{-1},
};
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(i2c1_pin_mux);
#ifdef CONFIG_NAND
configure_module_pin_mux(nand_pin_mux);
#endif
#ifndef CONFIG_NO_ETH
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(rgmii2_pin_mux);
#endif
#ifdef CONFIG_MMC
configure_module_pin_mux(mmc0_pin_mux);
#endif
configure_module_pin_mux(lcdc_pin_mux);
configure_module_pin_mux(gpio_pin_mux);
configure_module_pin_mux(ecap0_pin_mux);
}

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/*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef PMIC_H
#define PMIC_H
/*
* The PMIC on this board is a TPS65910.
*/
#define PMIC_SR_I2C_ADDR 0x12
#define PMIC_CTRL_I2C_ADDR 0x2D
/* PMIC Register offsets */
#define PMIC_VDD1_REG 0x21
#define PMIC_VDD1_OP_REG 0x22
#define PMIC_VDD2_REG 0x24
#define PMIC_VDD2_OP_REG 0x25
#define PMIC_DEVCTRL_REG 0x3f
/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
#define PMIC_VGAIN_SEL_MASK (0x3 << 6)
#define PMIC_ILMAX_MASK (0x1 << 5)
#define PMIC_TSTEP_MASK (0x7 << 2)
#define PMIC_ST_MASK (0x3)
#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6)
#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6)
#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6)
#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6)
#define PMIC_REG_ILMAX_1_0_A (0x0 << 5)
#define PMIC_REG_ILMAX_1_5_A (0x1 << 5)
#define PMIC_REG_TSTEP_ (0x0 << 2)
#define PMIC_REG_TSTEP_12_5 (0x1 << 2)
#define PMIC_REG_TSTEP_9_4 (0x2 << 2)
#define PMIC_REG_TSTEP_7_5 (0x3 << 2)
#define PMIC_REG_TSTEP_6_25 (0x4 << 2)
#define PMIC_REG_TSTEP_4_7 (0x5 << 2)
#define PMIC_REG_TSTEP_3_12 (0x6 << 2)
#define PMIC_REG_TSTEP_2_5 (0x7 << 2)
#define PMIC_REG_ST_OFF (0x0)
#define PMIC_REG_ST_ON_HI_POW (0x1)
#define PMIC_REG_ST_OFF_1 (0x2)
#define PMIC_REG_ST_ON_LOW_POW (0x3)
/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
#define PMIC_OP_REG_SEL (0x7F)
#define PMIC_OP_REG_CMD_MASK (0x1 << 7)
#define PMIC_OP_REG_CMD_OP (0x0 << 7)
#define PMIC_OP_REG_CMD_SR (0x1 << 7)
#define PMIC_OP_REG_SEL_MASK (0x7F)
#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
/* Device control register . (DEVCTRL_REG) */
#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
#endif

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#
# Makefile
#
# (C) Copyright 2013 Siemens Schweiz AG
# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
#
# Based on:
# u-boot:/board/ti/am335x/Makefile
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
endif
LIB = $(obj)lib$(BOARD).o
ifdef CONFIG_SPL_BUILD
COBJS := mux.o
endif
COBJS += board.o
ifndef CONFIG_SPL_BUILD
COBJS += ../common/factoryset.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* Board functions for TI AM335X based rut board
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* u-boot:/board/ti/am335x/board.c
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spi.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <video.h>
#include <watchdog.h>
#include "board.h"
#include "../common/factoryset.h"
#include "../../../drivers/video/da8xx-fb.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(void)
{
return 0;
}
#ifdef CONFIG_SPL_BUILD
static void board_init_ddr(void)
{
struct emif_regs rut_ddr3_emif_reg_data = {
.sdram_config = 0x61C04AB2,
.sdram_tim1 = 0x0888A39B,
.sdram_tim2 = 0x26337FDA,
.sdram_tim3 = 0x501F830F,
.emif_ddr_phy_ctlr_1 = 0x6,
.zq_config = 0x50074BE4,
.ref_ctrl = 0x93B,
};
struct ddr_data rut_ddr3_data = {
.datardsratio0 = 0x3b,
.datawdsratio0 = 0x85,
.datafwsratio0 = 0x100,
.datawrsratio0 = 0xc1,
.datauserank0delay = 1,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control rut_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x40,
.cmd0dldiff = 0,
.cmd0iclkout = 1,
.cmd1csratio = 0x40,
.cmd1dldiff = 0,
.cmd1iclkout = 1,
.cmd2csratio = 0x40,
.cmd2dldiff = 0,
.cmd2iclkout = 1,
};
config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)
{
return;
}
#endif /* if def CONFIG_SPL_BUILD */
#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 1,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
int n = 0;
int rv;
#ifndef CONFIG_SPL_BUILD
factoryset_setenv();
#endif
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
return n;
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
#if defined(CONFIG_HW_WATCHDOG)
static bool hw_watchdog_init_done;
static int hw_watchdog_trigger_level;
void hw_watchdog_reset(void)
{
if (!hw_watchdog_init_done)
return;
hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
}
void hw_watchdog_init(void)
{
gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
hw_watchdog_reset();
hw_watchdog_init_done = 1;
}
#endif /* defined(CONFIG_HW_WATCHDOG) */
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct da8xx_panel lcd_panels[] = {
/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
[0] = {
.name = "KWH043MC17-F01",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
/* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
[1] = {
.name = "KWH043ST20-F01",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
/* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
[2] = {
.name = "MI0430VT-1",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
};
static const struct display_panel disp_panels[] = {
[0] = {
WVGA,
16, /* RGB 888 */
16,
COLOR_ACTIVE,
},
[1] = {
WVGA,
16, /* RGB 888 */
16,
COLOR_ACTIVE,
},
[2] = {
WVGA,
24, /* RGB 888 */
16,
COLOR_ACTIVE,
},
};
static const struct lcd_ctrl_config lcd_cfgs[] = {
[0] = {
&disp_panels[0],
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
},
[1] = {
&disp_panels[1],
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
},
[2] = {
&disp_panels[2],
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 24,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
},
};
/* no console on this board */
int board_cfb_skip(void)
{
return 1;
}
#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
#define PLL_GET_N(v) (v & 0x7f)
static struct dpll_regs dpll_lcd_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x98,
.cm_idlest_dpll = CM_WKUP + 0x48,
.cm_clksel_dpll = CM_WKUP + 0x54,
};
static int get_clk(struct dpll_regs *dpll_regs)
{
unsigned int val;
unsigned int m, n;
int f = 0;
val = readl(dpll_regs->cm_clksel_dpll);
m = PLL_GET_M(val);
n = PLL_GET_N(val);
f = (m * V_OSCK) / n;
return f;
};
int clk_get(int clk)
{
return get_clk(&dpll_lcd_regs);
};
static int conf_disp_pll(int m, int n)
{
struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
#endif
u32 *const clk_domains[] = {
&cmper->lcdclkctrl,
0
};
u32 *const clk_modules_explicit_en[] = {
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
&cmper->spi1clkctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
/* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
writel(0x0, &cmdpll->clklcdcpixelclk);
do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12),
&cmwkup->clkmoddplldisp); /* 0x98 */
#endif
return 0;
}
static int set_gpio(int gpio, int state)
{
gpio_request(gpio, "temp");
gpio_direction_output(gpio, state);
gpio_set_value(gpio, state);
gpio_free(gpio);
return 0;
}
static int enable_lcd(void)
{
unsigned char buf[1];
set_gpio(BOARD_LCD_RESET, 1);
/* spi lcd init */
kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
/* backlight on */
buf[0] = 0xf;
i2c_write(0x24, 0x7, 1, buf, 1);
buf[0] = 0x3f;
i2c_write(0x24, 0x8, 1, buf, 1);
return 0;
}
int arch_early_init_r(void)
{
enable_lcd();
return 0;
}
static int board_video_init(void)
{
int i;
int anzdisp = ARRAY_SIZE(lcd_panels);
int display = 1;
for (i = 0; i < anzdisp; i++) {
if (strncmp((const char *)factory_dat.disp_name,
lcd_panels[i].name,
strlen((const char *)factory_dat.disp_name)) == 0) {
printf("DISPLAY: %s\n", factory_dat.disp_name);
break;
}
}
if (i == anzdisp) {
i = 1;
printf("%s: %s not found, using default %s\n", __func__,
factory_dat.disp_name, lcd_panels[i].name);
}
conf_disp_pll(25, 2);
da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
lcd_cfgs[display].bpp);
return 0;
}
#endif /* ifdef CONFIG_VIDEO */
#include "../common/board.c"

22
board/siemens/rut/board.h Normal file
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@ -0,0 +1,22 @@
/*
* board.h
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* TI AM335x boards information header
* u-boot:/board/ti/am335x/board.h
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
void enable_uart0_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(void);
#endif

347
board/siemens/rut/mux.c Normal file
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@ -0,0 +1,347 @@
/*
* pinmux setup for siemens rut board
*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* u-boot:/board/ti/am335x/mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux ddr_pin_mux[] = {
{OFFSET(ddr_resetn), (MODE(0))},
{OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_ck), (MODE(0))},
{OFFSET(ddr_nck), (MODE(0))},
{OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_odt), (MODE(0))},
{OFFSET(ddr_d0), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d1), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d2), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d3), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d4), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d5), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d6), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d7), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d8), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d9), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d10), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d11), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d12), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d13), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d14), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_d15), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)},
{OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)},
{OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux lcd_pin_mux[] = {
{OFFSET(gpmc_ad8), (MODE(1))},
{OFFSET(gpmc_ad9), (MODE(1))},
{OFFSET(gpmc_ad10), (MODE(1))},
{OFFSET(gpmc_ad11), (MODE(1))},
{OFFSET(gpmc_ad12), (MODE(1))},
{OFFSET(gpmc_ad13), (MODE(1))},
{OFFSET(gpmc_ad14), (MODE(1))},
{OFFSET(gpmc_ad15), (MODE(1))},
{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
{OFFSET(lcd_vsync), (MODE(0))},
{OFFSET(lcd_hsync), (MODE(0))},
{OFFSET(lcd_pclk), (MODE(0))},
{OFFSET(lcd_ac_bias_en), (MODE(0))},
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
{-1},
};
static struct module_pin_mux mii_pin_mux[] = {
{OFFSET(mii1_crs), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_txen), (MODE(1))},
{OFFSET(mii1_txd1), (MODE(1))},
{OFFSET(mii1_txd0), (MODE(1))},
{OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)},
{OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)},
{OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)},
{OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)},
{-1},
};
static struct module_pin_mux gpio_pin_mux[] = {
{OFFSET(mii1_col), (MODE(7) | RXACTIVE)},
{OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)},
{OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)},
{OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)},
{OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)},
{OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)},
{OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)},
{OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)},
{OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)},
{OFFSET(mcasp0_fsr), (MODE(7))},
{OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)},
{OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)},
{OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)},
{OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux usb0_pin_mux[] = {
{OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb0_drvvbus), (MODE(0))},
{-1},
};
static struct module_pin_mux usb1_pin_mux[] = {
{OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(usb1_drvvbus), (MODE(0))},
{-1},
};
static struct module_pin_mux spi0_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux spi1_pin_mux[] = {
{OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)},
{OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)},
{OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)},
{OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)},
{-1},
};
static struct module_pin_mux jtag_pin_mux[] = {
{OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(tdo), (MODE(0) | PULLUP_EN)},
{OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(ntrst), (MODE(0) | RXACTIVE)},
{-1},
};
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)},
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)},
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)},
{OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)},
{OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)},
{-1},
};
static struct module_pin_mux ainx_pin_mux[] = {
{OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux rtc_pin_mux[] = {
{OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux gpmc_pin_mux[] = {
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)},
{-1},
};
static struct module_pin_mux pmic_pin_mux[] = {
{OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)},
{-1},
};
static struct module_pin_mux osc_pin_mux[] = {
{OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(osc0_out), (MODE(0) | PULLUP_EN)},
{-1},
};
static struct module_pin_mux pwm_pin_mux[] = {
{OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(gpmc_a2), (MODE(6))},
{OFFSET(gpmc_a3), (MODE(6))},
{-1},
};
static struct module_pin_mux emu_pin_mux[] = {
{OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)},
{-1},
};
static struct module_pin_mux vref_pin_mux[] = {
{OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)},
{-1},
};
static struct module_pin_mux misc_pin_mux[] = {
{OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)},
{OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)},
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
void enable_board_pin_mux(void)
{
configure_module_pin_mux(ddr_pin_mux);
configure_module_pin_mux(lcd_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(mii_pin_mux);
configure_module_pin_mux(gpio_pin_mux);
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(usb0_pin_mux);
configure_module_pin_mux(usb1_pin_mux);
configure_module_pin_mux(spi0_pin_mux);
configure_module_pin_mux(spi1_pin_mux);
configure_module_pin_mux(jtag_pin_mux);
configure_module_pin_mux(nand_pin_mux);
configure_module_pin_mux(ainx_pin_mux);
configure_module_pin_mux(rtc_pin_mux);
configure_module_pin_mux(gpmc_pin_mux);
configure_module_pin_mux(pmic_pin_mux);
configure_module_pin_mux(osc_pin_mux);
configure_module_pin_mux(pwm_pin_mux);
configure_module_pin_mux(emu_pin_mux);
configure_module_pin_mux(vref_pin_mux);
configure_module_pin_mux(misc_pin_mux);
}

3
boards.cfg
View File

@ -254,6 +254,9 @@ am335x_evm_uart5 arm armv7 am335x ti
am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT
am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT
am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1
dxr2 arm armv7 dxr2 siemens am33xx
pxm2 arm armv7 pxm2 siemens am33xx
rut arm armv7 rut siemens am33xx
ti814x_evm arm armv7 ti814x ti am33xx
ti816x_evm arm armv7 ti816x ti am33xx
pcm051 arm armv7 pcm051 phytec am33xx pcm051

94
include/configs/dxr2.h Normal file
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@ -0,0 +1,94 @@
/*
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_DXR2_H
#define __CONFIG_DXR2_H
#define CONFIG_SIEMENS_DXR2
#define MACH_TYPE_DXR2 4315
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DXR2
#include "siemens-am33x-common.h"
#define CONFIG_SYS_MPUCLK 275
#define DXR2_IOCTRL_VAL 0x18b
#define DDR_PLL_FREQ 266
#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K
#define BOARD_DFU_BUTTON_GPIO 27
#define BOARD_DFU_BUTTON_LED 64
#undef CONFIG_DOS_PARTITION
#undef CONFIG_CMD_FAT
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* I2C Configuration */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define EEPROM_ADDR_DDR3 0x90
#define EEPROM_ADDR_CHIP 0x120
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
#undef CONFIG_SPL_NET_SUPPORT
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET
/* Watchdog */
#define CONFIG_OMAP_WATCHDOG
#ifndef CONFIG_SPL_BUILD
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=dxr2\0" \
"nand_img_size=0x300000\0" \
"optargs=\0" \
CONFIG_COMMON_ENV_SETTINGS
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND \
"if dfubutton; then " \
"run dfu_start; " \
"reset; " \
"fi;" \
"if ping ${serverip}; then " \
"run net_nfs; " \
"fi;" \
"run nand_boot;"
#else
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTCOMMAND \
"setenv autoload no; " \
"dhcp; " \
"if tftp 80000000 debrick.scr; then " \
"source 80000000; " \
"fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#endif /* ! __CONFIG_DXR2_H */

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/*
* siemens pxm2
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_PXM2_H
#define __CONFIG_PXM2_H
#define CONFIG_SIEMENS_PXM2
#define MACH_TYPE_PXM2 4309
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2
#include "siemens-am33x-common.h"
#define CONFIG_SYS_MPUCLK 720
#define DXR2_IOCTRL_VAL 0x18b
#define DDR_PLL_FREQ 266
#define BOARD_DFU_BUTTON_GPIO 59
#define BOARD_DFU_BUTTON_LED 117
#define BOARD_LCD_POWER 111
#define BOARD_BACK_LIGHT 112
#define BOARD_TOUCH_POWER 57
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */
/* I2C Configuration */
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300
#undef CONFIG_SPL_NET_SUPPORT
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_ATHEROS
#define CONFIG_FACTORYSET
/* UBI Support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif
/* Watchdog */
#define CONFIG_OMAP_WATCHDOG
#ifndef CONFIG_SPL_BUILD
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=pxm2\0" \
"nand_img_size=0x500000\0" \
"optargs=\0" \
CONFIG_COMMON_ENV_SETTINGS \
"mmc_dev=0\0" \
"mmc_root=/dev/mmcblk0p2 rw\0" \
"mmc_root_fs_type=ext4 rootwait\0" \
"mmc_load_uimage=" \
"mmc rescan; " \
"setenv bootfile uImage;" \
"fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
"loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"mmc_args=run bootargs_defaults;" \
"mtdparts default;" \
"setenv bootargs ${bootargs} " \
"root=${mmc_root} ${mtdparts}" \
"rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
"eth=${ethaddr} " \
"\0" \
"mmc_boot=run mmc_args; " \
"run mmc_load_uimage; " \
"bootm ${kloadaddr}\0" \
""
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND \
"if dfubutton; then " \
"run dfu_start; " \
"reset; " \
"fi; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmc_dev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run mmc_load_uimage; then " \
"run mmc_args;" \
"bootm ${kloadaddr};" \
"fi;" \
"fi;" \
"run nand_boot;" \
"if ping ${serverip}; then " \
"run net_nfs; " \
"fi; "
#else
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTCOMMAND \
"setenv autoload no; " \
"dhcp; " \
"if tftp 80000000 debrick.scr; then " \
"source 80000000; " \
"fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CMD_BMP
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
#define PWM_TICKS 0x1388
#define PWM_DUTY 0x200
#endif
#endif /* ! __CONFIG_PXM2_H */

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/*
* siemens rut
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_RUT_H
#define __CONFIG_RUT_H
#define CONFIG_SIEMENS_RUT
#define MACH_TYPE_RUT 4316
#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
#include "siemens-am33x-common.h"
#define CONFIG_SYS_MPUCLK 600
#define RUT_IOCTRL_VAL 0x18b
#define DDR_PLL_FREQ 303
/* Physical Memory Map */
#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
/* I2C Configuration */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200
#undef CONFIG_SPL_NET_SUPPORT
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
#define CONFIG_PHY_ADDR 1
#define CONFIG_PHY_NATSEMI
#define CONFIG_FACTORYSET
/* UBI Support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#endif
/* Watchdog */
#define WATCHDOG_TRIGGER_GPIO 14
#ifndef CONFIG_SPL_BUILD
/* Default env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=rut\0" \
"splashpos=488,352\0" \
"optargs=fixrtc --no-log consoleblank=0 \0" \
CONFIG_COMMON_ENV_SETTINGS \
"mmc_dev=0\0" \
"mmc_root=/dev/mmcblk0p2 rw\0" \
"mmc_root_fs_type=ext4 rootwait\0" \
"mmc_load_uimage=" \
"mmc rescan; " \
"setenv bootfile uImage;" \
"fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
"loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"mmc_args=run bootargs_defaults;" \
"mtdparts default;" \
"setenv bootargs ${bootargs} " \
"root=${mmc_root} ${mtdparts}" \
"rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
"eth=${ethaddr} " \
"\0" \
"mmc_boot=run mmc_args; " \
"run mmc_load_uimage; " \
"bootm ${kloadaddr}\0" \
""
#ifndef CONFIG_RESTORE_FLASH
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmc_dev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run mmc_load_uimage; then " \
"run mmc_args;" \
"bootm ${kloadaddr};" \
"fi;" \
"fi;" \
"run nand_boot;" \
"if ping ${serverip}; then " \
"run net_nfs; " \
"fi; "
#else
#define CONFIG_BOOTDELAY 0
#define CONFIG_BOOTCOMMAND \
"setenv autoload no; " \
"dhcp; " \
"if tftp 80000000 debrick.scr; then " \
"source 80000000; " \
"fi"
#endif
#endif /* CONFIG_SPL_BUILD */
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_HW_WATCHDOG
#endif
#define CONFIG_VIDEO
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SCREEN_ALIGN
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CMD_BMP
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_FORMIKE
#endif
#endif /* ! __CONFIG_RUT_H */

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/*
* siemens am33x common board options
* (C) Copyright 2013 Siemens Schweiz AG
* (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* Based on:
* U-Boot file:/include/configs/am335x_evm.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H
#define __CONFIG_SIEMENS_AM33X_COMMON_H
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#include <asm/arch/omap.h>
#define CONFIG_DMA_COHERENT
#define CONFIG_DMA_COHERENT_SIZE (1 << 20)
#define CONFIG_ENV_SIZE (0x2000)
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_NO_FLASH
#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SYS_CACHELINE_SIZE 64
/* commands to include */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_CACHE
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#ifndef CONFIG_SPL_BUILD
#define CONFIG_ROOTPATH "/opt/eldk"
#endif
#define CONFIG_ENV_OVERWRITE 1
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_AUTOLOAD "yes"
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 32
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* memtest works on 8 MB in DRAM after skipping 32MB from
* start addr of ram disk
*/
#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_SPI
#define CONFIG_OMAP3_SPI
#define CONFIG_MTD_DEVICE
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_WINBOND
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED (75000000)
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000
#define CONFIG_SYS_NS16550_COM4 0x481a6000
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SERIAL1 1
#define CONFIG_CONS_INDEX 1
/* I2C Configuration */
#define CONFIG_I2C
#define CONFIG_CMD_I2C
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_DRIVER_OMAP24XX_I2C
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (101 * 1024)
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_FS_FAT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_AM33XX_BCH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_ECCSTEPS 4
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
* header. That is 0x800FFFC0--0x80100000 should not be used for any
* other needs.
*/
#define CONFIG_SYS_TEXT_BASE 0x80100000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
/*
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#ifndef CONFIG_SPL_BUILD
/*
* USB configuration
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_MUSB_GADGET
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif
#ifdef CONFIG_MUSB_GADGET
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
#endif /* CONFIG_MUSB_GADGET */
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
/* USB TI's IDs */
#define CONFIG_USBD_HS
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_NAND
#define CONFIG_CMD_DFU
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)
#endif /* CONFIG_SPL_BUILD */
/*
* Default to using SPI for environment, etc. We have multiple copies
* of SPL as the ROM will check these locations.
* 0x0 - 0x20000 : First copy of SPL
* 0x20000 - 0x40000 : Second copy of SPL
* 0x40000 - 0x60000 : Third copy of SPL
* 0x60000 - 0x80000 : Fourth copy of SPL
* 0x80000 - 0xDF000 : U-Boot
* 0xDF000 - 0xE0000 : U-Boot Environment
* 0xE0000 - 0x442000 : Linux Kernel
* 0x442000 - 0x800000 : Userland
*/
#if defined(CONFIG_SPI_BOOT)
# undef CONFIG_ENV_IS_NOWHERE
# define CONFIG_ENV_IS_IN_SPI_FLASH
# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */
# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
#endif /* SPI support */
/* Unsupported features */
#undef CONFIG_USE_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_CMD_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#define CONFIG_NAND
/* NAND support */
#ifdef CONFIG_NAND
#define CONFIG_CMD_NAND
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_NAME_STR "omap2-nand.0"
#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR
#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
"128k(spl)," \
"128k(spl.backup1)," \
"128k(spl.backup2)," \
"128k(spl.backup3)," \
"1920k(u-boot)," \
"128k(uboot.env)," \
"5120k(kernel_a)," \
"5120k(kernel_b)," \
"8192k(mtdoops)," \
"-(rootfs)"
/*
* chip-size = 256MiB
*| name | size | address area |
*-------------------------------------------------------
*| spl | 128.000 KiB | 0x 0..0x 1ffff |
*| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff |
*| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff |
*| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff |
*| u-boot | 1.875 MiB | 0x 80000..0x 25ffff |
*| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff |
*| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff |
*| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff |
*| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff |
*| rootfs | 235.500 MiB | 0x 1480000..0x fffffff |
*-------------------------------------------------------
*/
#define DFU_ALT_INFO_NAND \
"spl part 0 1;" \
"spl.backup1 part 0 2;" \
"spl.backup2 part 0 3;" \
"spl.backup3 part 0 4;" \
"u-boot part 0 5;" \
"u-boot.env part 0 6;" \
"kernel_a part 0 7;" \
"kernel_b part 0 8;" \
"rootfs partubi 0 10"
#define CONFIG_COMMON_ENV_SETTINGS \
"verify=no \0" \
"project_dir=systemone\0" \
"loadaddr=0x82000000\0" \
"kloadaddr=0x81000000\0" \
"script_addr=0x81900000\0" \
"console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
"active_set=a\0" \
"nand_active_ubi_vol=rootfs_a\0" \
"nand_root_fs_type=ubifs rootwait=1\0" \
"nand_src_addr=0x280000\0" \
"nand_src_addr_a=0x280000\0" \
"nand_src_addr_b=0x780000\0" \
"nfsopts=nolock rw mem=128M\0" \
"ip_method=none\0" \
"bootenv=uEnv.txt\0" \
"bootargs_defaults=setenv bootargs " \
"console=${console} " \
"${optargs}\0" \
"nand_args=run bootargs_defaults;" \
"mtdparts default;" \
"setenv nand_active_ubi_vol rootfs_${active_set};" \
"setenv ${active_set} true;" \
"if test -n ${a}; then " \
"setenv nand_src_addr ${nand_src_addr_a};" \
"fi;" \
"if test -n ${b}; then " \
"setenv nand_src_addr ${nand_src_addr_b};" \
"fi;" \
"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
"ubi.mtd=9,2048;" \
"setenv bootargs ${bootargs} " \
"root=${nand_root} noinitrd ${mtdparts} " \
"rootfstype=${nand_root_fs_type} ip=${ip_method} " \
"console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \
"=mtdoops\0" \
"dfu_args=run bootargs_defaults;" \
"setenv bootargs ${bootargs} ;" \
"mtdparts default; " \
"dfu nand 0; \0" \
"dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \
"net_args=run bootargs_defaults;" \
"mtdparts default;" \
"setenv bootfile ${project_dir}/kernel/uImage;" \
"setenv rootpath /home/projects/${project_dir}/rootfs;" \
"setenv bootargs ${bootargs} " \
"root=/dev/nfs ${mtdparts} " \
"nfsroot=${serverip}:${rootpath},${nfsopts} " \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"nand_boot=echo Booting from nand, active set ${active_set} ...; " \
"run nand_args; " \
"nand read.i ${kloadaddr} ${nand_src_addr} " \
"${nand_img_size}; bootm ${kloadaddr}\0" \
"net_nfs=echo Booting from network ...; " \
"run net_args; " \
"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
"bootm ${kloadaddr}\0" \
"flash_self=run nand_boot\0" \
"flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
"run nand_boot\0" \
"dfu_start=echo Preparing for dfu mode ...; " \
"run dfu_args; \0" \
"preboot=echo; "\
"echo Type 'run flash_self' to use kernel and root " \
"filesystem on memory; echo Type 'run flash_self_test' to " \
"use kernel and root filesystem on memory, boot in test " \
"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
"from memory and root filesystem over NFS; echo Type " \
"'run net_nfs' to get Kernel over TFTP and mount root " \
"filesystem over NFS; echo Set active_set variable to 'a' " \
"or 'b' to select kernel and rootfs partition; " \
"echo" \
"\0"
#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND
devices */
#if !defined(CONFIG_SPI_BOOT)
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#endif
#endif
#ifndef CONFIG_SPL_BUILD
#define CONFIG_OMAP_GPIO
#endif
/* Watchdog */
#define CONFIG_HW_WATCHDOG
/* Stop autoboot with ESC ESC key detected */
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b"
#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
"press \"<Esc><Esc>\" to stop\n", bootdelay
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */

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