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drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 7K/8K 

This version is based on the Marvell U-Boot version with this patch
applied as latest patch:

Git ID 7f408573: "fix: comphy: cp110: add comphy initialization for usb
device mode" from 2016-07-05.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
This commit is contained in:
Stefan Roese 2016-08-30 16:48:20 +02:00
parent 01e62c7f11
commit c0132f6005
7 changed files with 1904 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/phy/marvell/Makefile
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@ -5,3 +5,4 @@
obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_core.o
obj-$(CONFIG_MVEBU_COMPHY_SUPPORT) += comphy_mux.o
obj-$(CONFIG_ARMADA_3700) += comphy_a3700.o
obj-$(CONFIG_ARMADA_8K) += comphy_cp110.o

18
drivers/phy/marvell/comphy.h
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@ -60,6 +60,9 @@
#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
(0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
/* ToDo: Get this address via DT */
#define MVEBU_CP0_REGS_BASE 0xF2000000UL
#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
@ -117,10 +120,21 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg,
return -1;
}
#endif
int comphy_ap806_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
#ifdef CONFIG_ARMADA_8K
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
#else
static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
/*
* This function should never be called in this configuration, so
* lets return an error here.
*/
return -1;
}
#endif
void comphy_dedicated_phys_init(void);

3
drivers/phy/marvell/comphy_core.c
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@ -139,6 +139,9 @@ static int comphy_probe(struct udevice *dev)
if (of_device_is_compatible(dev, "marvell,comphy-armada-3700"))
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
if (of_device_is_compatible(dev, "marvell,comphy-cp110"))
chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
/*
* Bail out if no chip_init function is defined, e.g. no
* compatible node is found

1726
drivers/phy/marvell/comphy_cp110.c Normal file
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File diff suppressed because it is too large Load Diff

38
drivers/phy/marvell/comphy_hpipe.h
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@ -78,6 +78,14 @@
#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
(0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
#define HPIPE_CAL_REG1_REG 0xc
#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
(0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
(0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
#define HPIPE_DFE_REG0 0x01C
@ -94,6 +102,9 @@
(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
#define HPIPE_G1_SET_0_REG 0x034
#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
(0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
(0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
@ -145,6 +156,14 @@
#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
(0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
#define HPIPE_G1_SET_2_REG 0xf4
#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
(0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
#define HPIPE_PCIE_REG0 0x120
@ -164,6 +183,9 @@
#define HPIPE_MISC_CLK100M_125M_OFFSET 4
#define HPIPE_MISC_CLK100M_125M_MASK \
(0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
#define HPIPE_MISC_ICP_FORCE_OFFSET 5
#define HPIPE_MISC_ICP_FORCE_MASK \
(0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
#define HPIPE_MISC_TXDCLK_2X_MASK \
(0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
@ -197,6 +219,14 @@
#define HPIPE_SMAPLER_MASK \
(0x1 << HPIPE_SMAPLER_OFFSET)
#define HPIPE_TX_REG1_REG 0x174
#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
(0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
#define HPIPE_TX_REG1_SLC_EN_MASK \
(0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
#define HPIPE_PWR_CTR_DTL_REG 0x184
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
@ -262,6 +292,9 @@
(0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
#define HPIPE_G1_SETTINGS_3_REG 0x440
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
(0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
#define HPIPE_G1_SETTINGS_4_REG 0x444
#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
@ -289,6 +322,11 @@
#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
(0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
#define HPIPE_G1_SETTING_5_REG 0x538
#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
(0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
#define HPIPE_LANE_CONFIG0_REG 0x600
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \

30
drivers/phy/marvell/sata.h Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (C) 2015-2016 Marvell International Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SATA_H_
#define _SATA_H_
/* SATA3 Unit address */
#define SATA3_VENDOR_ADDRESS 0xA0
#define SATA3_VENDOR_ADDR_OFSSET 0
#define SATA3_VENDOR_ADDR_MASK (0xFFFFFFFF << SATA3_VENDOR_ADDR_OFSSET)
#define SATA3_VENDOR_DATA 0xA4
#define SATA_CONTROL_REG 0x0
#define SATA3_CTRL_SATA0_PD_OFFSET 6
#define SATA3_CTRL_SATA0_PD_MASK (1 << SATA3_CTRL_SATA0_PD_OFFSET)
#define SATA3_CTRL_SATA1_PD_OFFSET 14
#define SATA3_CTRL_SATA1_PD_MASK (1 << SATA3_CTRL_SATA1_PD_OFFSET)
#define SATA3_CTRL_SATA1_ENABLE_OFFSET 22
#define SATA3_CTRL_SATA1_ENABLE_MASK (1 << SATA3_CTRL_SATA1_ENABLE_OFFSET)
#define SATA3_CTRL_SATA_SSU_OFFSET 23
#define SATA3_CTRL_SATA_SSU_MASK (1 << SATA3_CTRL_SATA_SSU_OFFSET)
#define SATA_MBUS_SIZE_SELECT_REG 0x4
#define SATA_MBUS_REGRET_EN_OFFSET 7
#define SATA_MBUS_REGRET_EN_MASK (0x1 << SATA_MBUS_REGRET_EN_OFFSET)
#endif /* _SATA_H_ */

90
drivers/phy/marvell/utmi_phy.h Normal file
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@ -0,0 +1,90 @@
/*
* Copyright (C) 2015-2016 Marvell International Ltd.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _UTMI_PHY_H_
#define _UTMI_PHY_H_
#define UTMI_USB_CFG_DEVICE_EN_OFFSET 0
#define UTMI_USB_CFG_DEVICE_EN_MASK \
(0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET)
#define UTMI_USB_CFG_DEVICE_MUX_OFFSET 1
#define UTMI_USB_CFG_DEVICE_MUX_MASK \
(0x1 << UTMI_USB_CFG_DEVICE_MUX_OFFSET)
#define UTMI_USB_CFG_PLL_OFFSET 25
#define UTMI_USB_CFG_PLL_MASK \
(0x1 << UTMI_USB_CFG_PLL_OFFSET)
#define UTMI_PHY_CFG_PU_OFFSET 5
#define UTMI_PHY_CFG_PU_MASK \
(0x1 << UTMI_PHY_CFG_PU_OFFSET)
#define UTMI_PLL_CTRL_REG 0x0
#define UTMI_PLL_CTRL_REFDIV_OFFSET 0
#define UTMI_PLL_CTRL_REFDIV_MASK \
(0x7f << UTMI_PLL_CTRL_REFDIV_OFFSET)
#define UTMI_PLL_CTRL_FBDIV_OFFSET 16
#define UTMI_PLL_CTRL_FBDIV_MASK \
(0x1FF << UTMI_PLL_CTRL_FBDIV_OFFSET)
#define UTMI_PLL_CTRL_SEL_LPFR_OFFSET 28
#define UTMI_PLL_CTRL_SEL_LPFR_MASK \
(0x3 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET)
#define UTMI_PLL_CTRL_PLL_RDY_OFFSET 31
#define UTMI_PLL_CTRL_PLL_RDY_MASK \
(0x1 << UTMI_PLL_CTRL_PLL_RDY_OFFSET)
#define UTMI_CALIB_CTRL_REG 0x8
#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
#define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31
#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
#define UTMI_TX_CH_CTRL_REG 0xC
#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
#define UTMI_RX_CH_CTRL0_REG 0x14
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28
#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
#define UTMI_RX_CH_CTRL1_REG 0x18
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
(0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
#define UTMI_CTRL_STATUS0_REG 0x24
#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
#define UTMI_CTRL_STATUS0_TEST_SEL_OFFSET 25
#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
#define UTMI_CHGDTC_CTRL_REG 0x38
#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
#define UTMI_CHGDTC_CTRL_VDAT_MASK \
(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
#define UTMI_CHGDTC_CTRL_VSRC_OFFSET 10
#define UTMI_CHGDTC_CTRL_VSRC_MASK \
(0x3 << UTMI_CHGDTC_CTRL_VSRC_OFFSET)
#endif /* _UTMI_PHY_H_ */