diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
index fccabcd2c0..9a59075afc 100644
--- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -425,6 +425,14 @@ enum {
 
 #define START_CMD			(1u << 31)
 
+/*
+ * DDRCONF
+ * [5:4] row(13+n)
+ * [1:0] col(9+n), assume bw=2
+ */
+#define DDRCONF_ROW_SHIFT		4
+#define DDRCONF_COL_SHIFT		0
+
 /* DEVTODEV */
 #define BUSWRTORD_SHIFT			4
 #define BUSRDTOWR_SHIFT			2
diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
index 89fd8e6bff..868b96d51a 100644
--- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
@@ -596,16 +596,16 @@ static void dram_all_config(const struct dram_info *dram,
 const int ddrconf_table[] = {
 	/* row	    col,bw */
 	0,
-	((1 << 4) | 1),
-	((2 << 4) | 1),
-	((3 << 4) | 1),
-	((4 << 4) | 1),
-	((1 << 4) | 2),
-	((2 << 4) | 2),
-	((3 << 4) | 2),
-	((1 << 4) | 0),
-	((2 << 4) | 0),
-	((3 << 4) | 0),
+	((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+	((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+	((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+	((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
+	((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+	((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+	((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
+	((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+	((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
+	((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
 	0,
 	0,
 	0,