Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: M28: Cleanup memsize.o OOT build i.MX28: Move SPL to arch/arm/cpu/arm926ejs/mx28 M28: Fix typo M28: Document that units has to be set to sectors on SD bootcard i.mx: i.mx6q: add the initial support for i.mx6q ARM2 board i.mx: mxc_gpio: add the i.mx6q support i.mx: add the initial support for freescale i.MX6Q processor i.mx: introduce the armv7/imx-common folder S5PC2XX: Rename S5pc2XX to exynos tegra2: Don't use board pointer before it is set up tegra2: Remove unneeded 'dynamic ram size' message tegra2: Remove unused low-level Tegra2 UART code tegra2: Remove unneeded config option tegra2: Remove unneeded boot code tegra2: Enable instruction cache arm: Move CP15 init out of cpu_init_crit() tegra2: Simplify tegra_start() boot path tegra2: Add arch_cpu_init() to fire up Cortex-A9 tegra2: Use new GPIO APIs in gpio_config_uart() tegra2: Add support for Ventana tegra2: Modify MMC driver to handle power and cd GPIOs tegra2: Move board_mmc_init into board files
This commit is contained in:
Wolfgang Denk
commit
b96a661aea
12
MAINTAINERS
12
MAINTAINERS
|
|
@ -578,6 +578,7 @@ Jason Liu <r64343@freescale.com>
|
|||
|
||||
mx53evk i.MX53
|
||||
mx53loco i.MX53
|
||||
mx6qarm2 i.MX6Q
|
||||
|
||||
Enric Balletbo i Serra <eballetbo@iseebcn.com>
|
||||
|
||||
|
|
@ -697,12 +698,12 @@ Minkyu Kang <mk7.kang@samsung.com>
|
|||
|
||||
SMDKC100 ARM ARMV7 (S5PC100 SoC)
|
||||
s5p_goni ARM ARMV7 (S5PC110 SoC)
|
||||
s5pc210_universal ARM ARMV7 (S5PC210 SoC)
|
||||
s5pc210_universal ARM ARMV7 (EXYNOS4210 SoC)
|
||||
|
||||
Chander Kashyap <k.chander@samsung.com>
|
||||
|
||||
origen ARM ARMV7 (S5PC210 SoC)
|
||||
SMDKV310 ARM ARMV7 (S5PC210 SoC)
|
||||
origen ARM ARMV7 (EXYNOS4210 SoC)
|
||||
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
|
||||
|
||||
Torsten Koschorrek <koschorrek@synertronixx.de>
|
||||
scb9328 ARM920T (i.MXL)
|
||||
|
|
@ -880,6 +881,11 @@ Tom Warren <twarren@nvidia.com>
|
|||
harmony Tegra2 (ARM7 & A9 Dual Core)
|
||||
seaboard Tegra2 (ARM7 & A9 Dual Core)
|
||||
|
||||
Tom Warren <twarren@nvidia.com>
|
||||
Stephen Warren <swarren@nvidia.com>
|
||||
|
||||
ventana Tegra2 (ARM7 & A9 Dual Core)
|
||||
|
||||
Thomas Weber <weber@corscience.de>
|
||||
|
||||
devkit8000 ARM ARMV7 (OMAP3530 SoC)
|
||||
|
|
|
|||
10
Makefile
10
Makefile
|
|
@ -296,10 +296,18 @@ LIBS += post/libpost.o
|
|||
ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
|
||||
LIBS += $(CPUDIR)/omap-common/libomap-common.o
|
||||
endif
|
||||
|
||||
ifeq ($(SOC),mx5)
|
||||
LIBS += $(CPUDIR)/imx-common/libimx-common.o
|
||||
endif
|
||||
ifeq ($(SOC),mx6)
|
||||
LIBS += $(CPUDIR)/imx-common/libimx-common.o
|
||||
endif
|
||||
|
||||
ifeq ($(SOC),s5pc1xx)
|
||||
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
|
||||
endif
|
||||
ifeq ($(SOC),s5pc2xx)
|
||||
ifeq ($(SOC),exynos)
|
||||
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
|
||||
endif
|
||||
|
||||
|
|
|
|||
|
|
@ -27,6 +27,10 @@ LIB = $(obj)lib$(SOC).o
|
|||
|
||||
COBJS = clock.o mx28.o iomux.o timer.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
COBJS += spl_boot.o spl_mem_init.o spl_power_init.o
|
||||
endif
|
||||
|
||||
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Freescale i.MX28 Boot setup
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/iomux-mx28.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#include "mx28_init.h"
|
||||
|
||||
/*
|
||||
* This delay function is intended to be used only in early stage of boot, where
|
||||
* clock are not set up yet. The timer used here is reset on every boot and
|
||||
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
|
||||
* code simple, it doesn't take rolling into consideration.
|
||||
*/
|
||||
#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
|
||||
void early_delay(int delay)
|
||||
{
|
||||
uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
|
||||
st += delay;
|
||||
while (st > readl(HW_DIGCTRL_MICROSECONDS))
|
||||
;
|
||||
}
|
||||
|
||||
void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
|
||||
const unsigned int iomux_size)
|
||||
{
|
||||
mxs_iomux_setup_multiple_pads(iomux_setup, iomux_size);
|
||||
mx28_power_init();
|
||||
mx28_mem_init();
|
||||
mx28_power_wait_pswitch();
|
||||
}
|
||||
|
||||
/* Support aparatus */
|
||||
inline void board_init_f(unsigned long bootflag)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
inline void board_init_r(gd_t *id, ulong dest_addr)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
void serial_putc(const char c) {}
|
||||
void serial_puts(const char *s) {}
|
||||
void hang(void) __attribute__ ((noreturn));
|
||||
void hang(void)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
|
@ -29,7 +29,7 @@
|
|||
#include <asm/arch/iomux-mx28.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#include "m28_init.h"
|
||||
#include "mx28_init.h"
|
||||
|
||||
uint32_t dram_vals[] = {
|
||||
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#include "m28_init.h"
|
||||
#include "mx28_init.h"
|
||||
|
||||
void mx28_power_clock2xtal(void)
|
||||
{
|
||||
|
|
@ -37,7 +37,7 @@ SECTIONS
|
|||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
board/denx/m28evk/start.o (.text)
|
||||
arch/arm/cpu/arm926ejs/mx28/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
|
|
@ -67,16 +67,16 @@ SECTIONS
|
|||
*(.dynsym)
|
||||
}
|
||||
|
||||
_end = .;
|
||||
|
||||
.bss __rel_dyn_start (OVERLAY) : {
|
||||
.bss : {
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
*(.bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
}
|
||||
|
||||
/DISCARD/ : { *(.bss*) }
|
||||
_end = .;
|
||||
|
||||
/DISCARD/ : { *(.dynstr*) }
|
||||
/DISCARD/ : { *(.dynsym*) }
|
||||
/DISCARD/ : { *(.dynamic*) }
|
||||
|
|
@ -30,11 +30,11 @@
|
|||
#define CONFIG_SYS_CLK_FREQ_C210 24000000
|
||||
#endif
|
||||
|
||||
/* s5pc210: return pll clock frequency */
|
||||
static unsigned long s5pc210_get_pll_clk(int pllreg)
|
||||
/* exynos4: return pll clock frequency */
|
||||
static unsigned long exynos4_get_pll_clk(int pllreg)
|
||||
{
|
||||
struct s5pc210_clock *clk =
|
||||
(struct s5pc210_clock *)samsung_get_base_clock();
|
||||
struct exynos4_clock *clk =
|
||||
(struct exynos4_clock *)samsung_get_base_clock();
|
||||
unsigned long r, m, p, s, k = 0, mask, fout;
|
||||
unsigned int freq;
|
||||
|
||||
|
|
@ -96,11 +96,11 @@ static unsigned long s5pc210_get_pll_clk(int pllreg)
|
|||
return fout;
|
||||
}
|
||||
|
||||
/* s5pc210: return ARM clock frequency */
|
||||
static unsigned long s5pc210_get_arm_clk(void)
|
||||
/* exynos4: return ARM clock frequency */
|
||||
static unsigned long exynos4_get_arm_clk(void)
|
||||
{
|
||||
struct s5pc210_clock *clk =
|
||||
(struct s5pc210_clock *)samsung_get_base_clock();
|
||||
struct exynos4_clock *clk =
|
||||
(struct exynos4_clock *)samsung_get_base_clock();
|
||||
unsigned long div;
|
||||
unsigned long dout_apll;
|
||||
unsigned int apll_ratio;
|
||||
|
|
@ -115,11 +115,11 @@ static unsigned long s5pc210_get_arm_clk(void)
|
|||
return dout_apll;
|
||||
}
|
||||
|
||||
/* s5pc210: return pwm clock frequency */
|
||||
static unsigned long s5pc210_get_pwm_clk(void)
|
||||
/* exynos4: return pwm clock frequency */
|
||||
static unsigned long exynos4_get_pwm_clk(void)
|
||||
{
|
||||
struct s5pc210_clock *clk =
|
||||
(struct s5pc210_clock *)samsung_get_base_clock();
|
||||
struct exynos4_clock *clk =
|
||||
(struct exynos4_clock *)samsung_get_base_clock();
|
||||
unsigned long pclk, sclk;
|
||||
unsigned int sel;
|
||||
unsigned int ratio;
|
||||
|
|
@ -158,11 +158,11 @@ static unsigned long s5pc210_get_pwm_clk(void)
|
|||
return pclk;
|
||||
}
|
||||
|
||||
/* s5pc210: return uart clock frequency */
|
||||
static unsigned long s5pc210_get_uart_clk(int dev_index)
|
||||
/* exynos4: return uart clock frequency */
|
||||
static unsigned long exynos4_get_uart_clk(int dev_index)
|
||||
{
|
||||
struct s5pc210_clock *clk =
|
||||
(struct s5pc210_clock *)samsung_get_base_clock();
|
||||
struct exynos4_clock *clk =
|
||||
(struct exynos4_clock *)samsung_get_base_clock();
|
||||
unsigned long uclk, sclk;
|
||||
unsigned int sel;
|
||||
unsigned int ratio;
|
||||
|
|
@ -205,11 +205,11 @@ static unsigned long s5pc210_get_uart_clk(int dev_index)
|
|||
return uclk;
|
||||
}
|
||||
|
||||
/* s5pc210: set the mmc clock */
|
||||
static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
|
||||
/* exynos4: set the mmc clock */
|
||||
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
|
||||
{
|
||||
struct s5pc210_clock *clk =
|
||||
(struct s5pc210_clock *)samsung_get_base_clock();
|
||||
struct exynos4_clock *clk =
|
||||
(struct exynos4_clock *)samsung_get_base_clock();
|
||||
unsigned int addr;
|
||||
unsigned int val;
|
||||
|
||||
|
|
@ -234,25 +234,25 @@ static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
|
|||
|
||||
unsigned long get_pll_clk(int pllreg)
|
||||
{
|
||||
return s5pc210_get_pll_clk(pllreg);
|
||||
return exynos4_get_pll_clk(pllreg);
|
||||
}
|
||||
|
||||
unsigned long get_arm_clk(void)
|
||||
{
|
||||
return s5pc210_get_arm_clk();
|
||||
return exynos4_get_arm_clk();
|
||||
}
|
||||
|
||||
unsigned long get_pwm_clk(void)
|
||||
{
|
||||
return s5pc210_get_pwm_clk();
|
||||
return exynos4_get_pwm_clk();
|
||||
}
|
||||
|
||||
unsigned long get_uart_clk(int dev_index)
|
||||
{
|
||||
return s5pc210_get_uart_clk(dev_index);
|
||||
return exynos4_get_uart_clk(dev_index);
|
||||
}
|
||||
|
||||
void set_mmc_clk(int dev_index, unsigned int div)
|
||||
{
|
||||
s5pc210_set_mmc_clk(dev_index, div);
|
||||
exynos4_set_mmc_clk(dev_index, div);
|
||||
}
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)libimx-common.o
|
||||
|
||||
COBJS = timer.o cpu.o speed.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Sascha Hauer, Pengutronix
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
u32 cause;
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
cause = readl(&src_regs->srsr);
|
||||
writel(cause, &src_regs->srsr);
|
||||
|
||||
switch (cause) {
|
||||
case 0x00001:
|
||||
return "POR";
|
||||
case 0x00004:
|
||||
return "CSU";
|
||||
case 0x00008:
|
||||
return "IPP USER";
|
||||
case 0x00010:
|
||||
return "WDOG";
|
||||
case 0x00020:
|
||||
return "JTAG HIGH-Z";
|
||||
case 0x00040:
|
||||
return "JTAG SW";
|
||||
case 0x10000:
|
||||
return "WARM BOOT";
|
||||
default:
|
||||
return "unknown reset";
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
u32 cpurev;
|
||||
|
||||
cpurev = get_cpu_rev();
|
||||
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
|
||||
(cpurev & 0xFF000) >> 12,
|
||||
(cpurev & 0x000F0) >> 4,
|
||||
(cpurev & 0x0000F) >> 0,
|
||||
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
||||
printf("Reset cause: %s\n", get_reset_cause());
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
rc = fecmxc_initialize(bis);
|
||||
#endif
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initializes on-chip MMC controllers.
|
||||
* to override, implement board_mmc_init()
|
||||
*/
|
||||
int cpu_mmc_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
return fsl_esdhc_mmc_init(bis);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
__raw_writew(4, WDOG1_BASE_ADDR);
|
||||
}
|
||||
17
arch/arm/cpu/armv7/mx5/timer.c → arch/arm/cpu/armv7/imx-common/timer.c
Normal file → Executable file
17
arch/arm/cpu/armv7/mx5/timer.c → arch/arm/cpu/armv7/imx-common/timer.c
Normal file → Executable file
|
|
@ -39,10 +39,11 @@ struct mxc_gpt {
|
|||
static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
|
||||
|
||||
/* General purpose timers bitfields */
|
||||
#define GPTCR_SWR (1<<15) /* Software reset */
|
||||
#define GPTCR_FRR (1<<9) /* Freerun / restart */
|
||||
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
|
||||
#define GPTCR_TEN (1) /* Timer enable */
|
||||
#define GPTCR_SWR (1 << 15) /* Software reset */
|
||||
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
|
||||
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
|
||||
#define GPTCR_TEN 1 /* Timer enable */
|
||||
#define CLK_32KHZ 32768 /* 32Khz input */
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
|
@ -68,7 +69,7 @@ int timer_init(void)
|
|||
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
|
||||
|
||||
val = __raw_readl(&cur_gpt->counter);
|
||||
lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
|
||||
lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
|
||||
timestamp = 0;
|
||||
|
||||
return 0;
|
||||
|
|
@ -77,11 +78,11 @@ int timer_init(void)
|
|||
ulong get_timer_masked(void)
|
||||
{
|
||||
ulong val = __raw_readl(&cur_gpt->counter);
|
||||
val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
|
||||
val /= (CLK_32KHZ / CONFIG_SYS_HZ);
|
||||
if (val >= lastinc)
|
||||
timestamp += (val - lastinc);
|
||||
else
|
||||
timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
|
||||
timestamp += ((0xFFFFFFFF / (CLK_32KHZ / CONFIG_SYS_HZ))
|
||||
- lastinc) + val;
|
||||
lastinc = val;
|
||||
return timestamp;
|
||||
|
|
@ -96,7 +97,7 @@ ulong get_timer(ulong base)
|
|||
void __udelay(unsigned long usec)
|
||||
{
|
||||
unsigned long now, start, tmo;
|
||||
tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
|
||||
tmo = usec * (CLK_32KHZ / 1000) / 1000;
|
||||
|
||||
if (!tmo)
|
||||
tmo = 1;
|
||||
|
|
@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS = soc.o clock.o iomux.o timer.o speed.o
|
||||
COBJS = soc.o clock.o iomux.o
|
||||
SOBJS = lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
|
|
|||
|
|
@ -31,10 +31,6 @@
|
|||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
#include <fsl_esdhc.h>
|
||||
#endif
|
||||
|
||||
#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
|
||||
#error "CPU_TYPE not defined"
|
||||
#endif
|
||||
|
|
@ -75,61 +71,6 @@ u32 get_cpu_rev(void)
|
|||
return system_rev;
|
||||
}
|
||||
|
||||
static char *get_reset_cause(void)
|
||||
{
|
||||
u32 cause;
|
||||
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
|
||||
|
||||
cause = readl(&src_regs->srsr);
|
||||
writel(cause, &src_regs->srsr);
|
||||
|
||||
switch (cause) {
|
||||
case 0x00001:
|
||||
return "POR";
|
||||
case 0x00004:
|
||||
return "CSU";
|
||||
case 0x00008:
|
||||
return "IPP USER";
|
||||
case 0x00010:
|
||||
return "WDOG";
|
||||
case 0x00020:
|
||||
return "JTAG HIGH-Z";
|
||||
case 0x00040:
|
||||
return "JTAG SW";
|
||||
case 0x10000:
|
||||
return "WARM BOOT";
|
||||
default:
|
||||
return "unknown reset";
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DISPLAY_CPUINFO)
|
||||
int print_cpuinfo(void)
|
||||
{
|
||||
u32 cpurev;
|
||||
|
||||
cpurev = get_cpu_rev();
|
||||
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
|
||||
(cpurev & 0xFF000) >> 12,
|
||||
(cpurev & 0x000F0) >> 4,
|
||||
(cpurev & 0x0000F) >> 0,
|
||||
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
||||
printf("Reset cause: %s\n", get_reset_cause());
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int cpu_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
rc = fecmxc_initialize(bis);
|
||||
#endif
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
void imx_get_mac_from_fuse(unsigned char *mac)
|
||||
{
|
||||
|
|
@ -144,19 +85,6 @@ void imx_get_mac_from_fuse(unsigned char *mac)
|
|||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initializes on-chip MMC controllers.
|
||||
* to override, implement board_mmc_init()
|
||||
*/
|
||||
int cpu_mmc_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
return fsl_esdhc_mmc_init(bis);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
|
||||
void set_chipselect_size(int const cs_size)
|
||||
{
|
||||
unsigned int reg;
|
||||
|
|
@ -187,8 +115,3 @@ void set_chipselect_size(int const cs_size)
|
|||
|
||||
writel(reg, &iomuxc_regs->gpr1);
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
__raw_writew(4, WDOG1_BASE_ADDR);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
||||
COBJS = soc.o clock.o iomux-v3.o
|
||||
SOBJS = lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,366 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/ccm_regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
||||
enum pll_clocks {
|
||||
PLL_SYS, /* System PLL */
|
||||
PLL_BUS, /* System Bus PLL*/
|
||||
PLL_USBOTG, /* OTG USB PLL */
|
||||
PLL_ENET, /* ENET PLL */
|
||||
};
|
||||
|
||||
struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
|
||||
{
|
||||
u32 div;
|
||||
|
||||
switch (pll) {
|
||||
case PLL_SYS:
|
||||
div = __raw_readl(&imx_ccm->analog_pll_sys);
|
||||
div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
|
||||
|
||||
return infreq * (div >> 1);
|
||||
case PLL_BUS:
|
||||
div = __raw_readl(&imx_ccm->analog_pll_528);
|
||||
div &= BM_ANADIG_PLL_528_DIV_SELECT;
|
||||
|
||||
return infreq * (20 + (div << 1));
|
||||
case PLL_USBOTG:
|
||||
div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
|
||||
div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
|
||||
|
||||
return infreq * (20 + (div << 1));
|
||||
case PLL_ENET:
|
||||
div = __raw_readl(&imx_ccm->analog_pll_enet);
|
||||
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
|
||||
|
||||
return (div == 3 ? 125000000 : 25000000 * (div << 1));
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
static u32 get_mcu_main_clk(void)
|
||||
{
|
||||
u32 reg, freq;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cacrr);
|
||||
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
|
||||
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
|
||||
freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
|
||||
|
||||
return freq / (reg + 1);
|
||||
}
|
||||
|
||||
static u32 get_periph_clk(void)
|
||||
{
|
||||
u32 reg, freq = 0;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cbcdr);
|
||||
if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
|
||||
reg = __raw_readl(&imx_ccm->cbcmr);
|
||||
reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
|
||||
reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
|
||||
|
||||
switch (reg) {
|
||||
case 0:
|
||||
freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
|
||||
break;
|
||||
case 1:
|
||||
case 2:
|
||||
freq = CONFIG_SYS_MX6_HCLK;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
reg = __raw_readl(&imx_ccm->cbcmr);
|
||||
reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
|
||||
reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
|
||||
|
||||
switch (reg) {
|
||||
case 0:
|
||||
freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
|
||||
break;
|
||||
case 1:
|
||||
freq = PLL2_PFD2_FREQ;
|
||||
break;
|
||||
case 2:
|
||||
freq = PLL2_PFD0_FREQ;
|
||||
break;
|
||||
case 3:
|
||||
freq = PLL2_PFD2_DIV_FREQ;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
|
||||
static u32 get_ahb_clk(void)
|
||||
{
|
||||
u32 reg, ahb_podf;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cbcdr);
|
||||
reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
|
||||
ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
|
||||
|
||||
return get_periph_clk() / (ahb_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_ipg_clk(void)
|
||||
{
|
||||
u32 reg, ipg_podf;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cbcdr);
|
||||
reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
|
||||
ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
|
||||
|
||||
return get_ahb_clk() / (ipg_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_ipg_per_clk(void)
|
||||
{
|
||||
u32 reg, perclk_podf;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cscmr1);
|
||||
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
|
||||
|
||||
return get_ipg_clk() / (perclk_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_uart_clk(void)
|
||||
{
|
||||
u32 reg, uart_podf;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cscdr1);
|
||||
reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
|
||||
uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
|
||||
|
||||
return PLL3_80M / (uart_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_cspi_clk(void)
|
||||
{
|
||||
u32 reg, cspi_podf;
|
||||
|
||||
reg = __raw_readl(&imx_ccm->cscdr2);
|
||||
reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
|
||||
cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
|
||||
|
||||
return PLL3_60M / (cspi_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_axi_clk(void)
|
||||
{
|
||||
u32 root_freq, axi_podf;
|
||||
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
|
||||
|
||||
axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
|
||||
axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
|
||||
|
||||
if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
|
||||
if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
|
||||
root_freq = PLL2_PFD2_FREQ;
|
||||
else
|
||||
root_freq = PLL3_PFD1_FREQ;
|
||||
} else
|
||||
root_freq = get_periph_clk();
|
||||
|
||||
return root_freq / (axi_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_emi_slow_clk(void)
|
||||
{
|
||||
u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
|
||||
|
||||
cscmr1 = __raw_readl(&imx_ccm->cscmr1);
|
||||
emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
|
||||
emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
|
||||
emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
|
||||
emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
|
||||
|
||||
switch (emi_clk_sel) {
|
||||
case 0:
|
||||
root_freq = get_axi_clk();
|
||||
break;
|
||||
case 1:
|
||||
root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
|
||||
break;
|
||||
case 2:
|
||||
root_freq = PLL2_PFD2_FREQ;
|
||||
break;
|
||||
case 3:
|
||||
root_freq = PLL2_PFD0_FREQ;
|
||||
break;
|
||||
}
|
||||
|
||||
return root_freq / (emi_slow_pof + 1);
|
||||
}
|
||||
|
||||
static u32 get_mmdc_ch0_clk(void)
|
||||
{
|
||||
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
|
||||
u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
|
||||
MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
|
||||
|
||||
return get_periph_clk() / (mmdc_ch0_podf + 1);
|
||||
}
|
||||
|
||||
static u32 get_usdhc_clk(u32 port)
|
||||
{
|
||||
u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
|
||||
u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
|
||||
u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
|
||||
|
||||
switch (port) {
|
||||
case 0:
|
||||
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
|
||||
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
|
||||
|
||||
break;
|
||||
case 1:
|
||||
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
|
||||
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
|
||||
|
||||
break;
|
||||
case 2:
|
||||
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
|
||||
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
|
||||
|
||||
break;
|
||||
case 3:
|
||||
usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
|
||||
MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
|
||||
clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (clk_sel)
|
||||
root_freq = PLL2_PFD0_FREQ;
|
||||
else
|
||||
root_freq = PLL2_PFD2_FREQ;
|
||||
|
||||
return root_freq / (usdhc_podf + 1);
|
||||
}
|
||||
|
||||
u32 imx_get_uartclk(void)
|
||||
{
|
||||
return get_uart_clk();
|
||||
}
|
||||
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk)
|
||||
{
|
||||
switch (clk) {
|
||||
case MXC_ARM_CLK:
|
||||
return get_mcu_main_clk();
|
||||
case MXC_PER_CLK:
|
||||
return get_periph_clk();
|
||||
case MXC_AHB_CLK:
|
||||
return get_ahb_clk();
|
||||
case MXC_IPG_CLK:
|
||||
return get_ipg_clk();
|
||||
case MXC_IPG_PERCLK:
|
||||
return get_ipg_per_clk();
|
||||
case MXC_UART_CLK:
|
||||
return get_uart_clk();
|
||||
case MXC_CSPI_CLK:
|
||||
return get_cspi_clk();
|
||||
case MXC_AXI_CLK:
|
||||
return get_axi_clk();
|
||||
case MXC_EMI_SLOW_CLK:
|
||||
return get_emi_slow_clk();
|
||||
case MXC_DDR_CLK:
|
||||
return get_mmdc_ch0_clk();
|
||||
case MXC_ESDHC_CLK:
|
||||
return get_usdhc_clk(0);
|
||||
case MXC_ESDHC2_CLK:
|
||||
return get_usdhc_clk(1);
|
||||
case MXC_ESDHC3_CLK:
|
||||
return get_usdhc_clk(2);
|
||||
case MXC_ESDHC4_CLK:
|
||||
return get_usdhc_clk(3);
|
||||
case MXC_SATA_CLK:
|
||||
return get_ahb_clk();
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Dump some core clockes.
|
||||
*/
|
||||
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
u32 freq;
|
||||
freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
|
||||
printf("PLL_SYS %8d MHz\n", freq / 1000000);
|
||||
freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
|
||||
printf("PLL_BUS %8d MHz\n", freq / 1000000);
|
||||
freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
|
||||
printf("PLL_OTG %8d MHz\n", freq / 1000000);
|
||||
freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
|
||||
printf("PLL_NET %8d MHz\n", freq / 1000000);
|
||||
|
||||
printf("\n");
|
||||
printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
|
||||
printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
|
||||
printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
|
||||
printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
|
||||
printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
|
||||
printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
|
||||
printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
|
||||
printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
|
||||
printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
|
||||
printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
|
||||
printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
|
||||
printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************/
|
||||
|
||||
U_BOOT_CMD(
|
||||
clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,
|
||||
"display clocks",
|
||||
""
|
||||
);
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Based on the iomux-v3.c from Linux kernel:
|
||||
* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
|
||||
* <armlinux@phytec.de>
|
||||
*
|
||||
* Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/iomux-v3.h>
|
||||
|
||||
static void *base = (void *)IOMUXC_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* configures a single pad in the iomuxer
|
||||
*/
|
||||
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
|
||||
{
|
||||
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
|
||||
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
|
||||
u32 sel_input_ofs =
|
||||
(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
|
||||
u32 sel_input =
|
||||
(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
|
||||
u32 pad_ctrl_ofs =
|
||||
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
|
||||
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
|
||||
|
||||
if (mux_ctrl_ofs)
|
||||
__raw_writel(mux_mode, base + mux_ctrl_ofs);
|
||||
|
||||
if (sel_input_ofs)
|
||||
__raw_writel(sel_input, base + sel_input_ofs);
|
||||
|
||||
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
|
||||
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
|
||||
{
|
||||
iomux_v3_cfg_t *p = pad_list;
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
ret = imx_iomux_v3_setup_pad(*p);
|
||||
if (ret)
|
||||
return ret;
|
||||
p++;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
.section ".text.init", "x"
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Sascha Hauer, Pengutronix
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
u32 get_cpu_rev(void)
|
||||
{
|
||||
int system_rev = 0x61000 | CHIP_REV_1_0;
|
||||
|
||||
return system_rev;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARCH_CPU_INIT
|
||||
void init_aips(void)
|
||||
{
|
||||
u32 reg = AIPS1_BASE_ADDR;
|
||||
|
||||
/*
|
||||
* Set all MPROTx to be non-bufferable, trusted for R/W,
|
||||
* not forced to user-mode.
|
||||
*/
|
||||
writel(0x77777777, reg + 0x00);
|
||||
writel(0x77777777, reg + 0x04);
|
||||
|
||||
reg = AIPS2_BASE_ADDR;
|
||||
writel(0x77777777, reg + 0x00);
|
||||
writel(0x77777777, reg + 0x04);
|
||||
}
|
||||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
init_aips();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_FEC_MXC)
|
||||
void imx_get_mac_from_fuse(unsigned char *mac)
|
||||
{
|
||||
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
|
||||
struct fuse_bank *bank = &iim->bank[4];
|
||||
struct fuse_bank4_regs *fuse =
|
||||
(struct fuse_bank4_regs *)bank->fuse_regs;
|
||||
|
||||
u32 mac_lo = readl(&fuse->mac_addr_low);
|
||||
u32 mac_hi = readl(&fuse->mac_addr_high);
|
||||
|
||||
*(u32 *)mac = mac_lo;
|
||||
|
||||
mac[4] = mac_hi & 0xff;
|
||||
mac[5] = (mac_hi >> 8) & 0xff;
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
@ -82,18 +82,6 @@ _end_vect:
|
|||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#ifdef CONFIG_TEGRA2
|
||||
/*
|
||||
* Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
|
||||
* U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
|
||||
* muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
|
||||
* to pick up its reset vector, which points here.
|
||||
*/
|
||||
.globl _armboot_start
|
||||
_armboot_start:
|
||||
.word _start
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These are defined in the board-specific linker script.
|
||||
*/
|
||||
|
|
@ -162,6 +150,7 @@ reset:
|
|||
|
||||
/* the mask ROM code should have PLL and others stable */
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
bl cpu_init_cp15
|
||||
bl cpu_init_crit
|
||||
#endif
|
||||
|
||||
|
|
@ -299,17 +288,16 @@ jump_2_ram:
|
|||
_board_init_r_ofs:
|
||||
.word board_init_r - _start
|
||||
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/*************************************************************************
|
||||
*
|
||||
* CPU_init_critical registers
|
||||
* cpu_init_cp15
|
||||
*
|
||||
* setup important registers
|
||||
* setup memory timing
|
||||
* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
|
||||
* CONFIG_SYS_ICACHE_OFF is defined.
|
||||
*
|
||||
*************************************************************************/
|
||||
cpu_init_crit:
|
||||
.globl cpu_init_cp15
|
||||
cpu_init_cp15:
|
||||
/*
|
||||
* Invalidate L1 I/D
|
||||
*/
|
||||
|
|
@ -334,7 +322,19 @@ cpu_init_crit:
|
|||
orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
|
||||
#endif
|
||||
mcr p15, 0, r0, c1, c0, 0
|
||||
mov pc, lr @ back to my caller
|
||||
|
||||
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/*************************************************************************
|
||||
*
|
||||
* CPU_init_critical registers
|
||||
*
|
||||
* setup important registers
|
||||
* setup memory timing
|
||||
*
|
||||
*************************************************************************/
|
||||
cpu_init_crit:
|
||||
/*
|
||||
* Jump to board specific initialization...
|
||||
* The Mask ROM will have already initialized
|
||||
|
|
|
|||
|
|
@ -23,6 +23,11 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# The AVP is ARMv4T architecture so we must use special compiler
|
||||
# flags for any startup files it might use.
|
||||
CFLAGS_arch/arm/cpu/armv7/tegra2/ap20.o += -march=armv4t
|
||||
CFLAGS_arch/arm/cpu/armv7/tegra2/clock.o += -march=armv4t
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).o
|
||||
|
|
|
|||
|
|
@ -31,7 +31,12 @@
|
|||
#include <asm/arch/scu.h>
|
||||
#include <common.h>
|
||||
|
||||
u32 s_first_boot = 1;
|
||||
/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
|
||||
static int ap20_cpu_is_cortexa9(void)
|
||||
{
|
||||
u32 id = readb(NV_PA_PG_UP_BASE + PG_UP_TAG_0);
|
||||
return id == (PG_UP_TAG_0_PID_CPU & 0xff);
|
||||
}
|
||||
|
||||
void init_pllx(void)
|
||||
{
|
||||
|
|
@ -283,38 +288,37 @@ void init_pmc_scratch(void)
|
|||
writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
|
||||
}
|
||||
|
||||
void cpu_start(void)
|
||||
void tegra2_start(void)
|
||||
{
|
||||
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
|
||||
|
||||
/* enable JTAG */
|
||||
writel(0xC0, &pmt->pmt_cfg_ctl);
|
||||
/* If we are the AVP, start up the first Cortex-A9 */
|
||||
if (!ap20_cpu_is_cortexa9()) {
|
||||
/* enable JTAG */
|
||||
writel(0xC0, &pmt->pmt_cfg_ctl);
|
||||
|
||||
if (s_first_boot) {
|
||||
/*
|
||||
* Need to set this before cold-booting,
|
||||
* otherwise we'll end up in an infinite loop.
|
||||
*/
|
||||
s_first_boot = 0;
|
||||
cold_boot();
|
||||
}
|
||||
}
|
||||
* If we are ARM7 - give it a different stack. We are about to
|
||||
* start up the A9 which will want to use this one.
|
||||
*/
|
||||
asm volatile("ldr sp, =%c0\n"
|
||||
: : "i"(AVP_EARLY_BOOT_STACK_LIMIT));
|
||||
|
||||
void tegra2_start()
|
||||
{
|
||||
if (s_first_boot) {
|
||||
/* Init Debug UART Port (115200 8n1) */
|
||||
uart_init();
|
||||
|
||||
/* Init PMC scratch memory */
|
||||
init_pmc_scratch();
|
||||
start_cpu((u32)_start);
|
||||
halt_avp();
|
||||
/* not reached */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ENABLE_CORTEXA9
|
||||
/* take the mpcore out of reset */
|
||||
cpu_start();
|
||||
/* Init PMC scratch memory */
|
||||
init_pmc_scratch();
|
||||
|
||||
/* configure cache */
|
||||
cache_configure();
|
||||
#endif
|
||||
enable_scu();
|
||||
|
||||
/* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
|
||||
asm volatile(
|
||||
"mrc p15, 0, r0, c1, c0, 1\n"
|
||||
"orr r0, r0, #0x41\n"
|
||||
"mcr p15, 0, r0, c1, c0, 1\n");
|
||||
|
||||
/* FIXME: should have ap20's L2 disabled too? */
|
||||
}
|
||||
|
|
|
|||
|
|
@ -95,10 +95,8 @@
|
|||
#define HALT_COP_EVENT_IRQ_1 (1 << 11)
|
||||
#define HALT_COP_EVENT_FIQ_1 (1 << 9)
|
||||
|
||||
/* Prototypes */
|
||||
|
||||
/* Start up the tegra2 SOC */
|
||||
void tegra2_start(void);
|
||||
void uart_init(void);
|
||||
void udelay(unsigned long);
|
||||
void cold_boot(void);
|
||||
void cache_configure(void);
|
||||
|
||||
/* This is the main entry into U-Boot, used by the Cortex-A9 */
|
||||
extern void _start(void);
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include "ap20.h"
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/arch/tegra2.h>
|
||||
#include <asm/arch/pmc.h>
|
||||
|
|
@ -54,28 +55,10 @@ unsigned int query_sdram_size(void)
|
|||
}
|
||||
}
|
||||
|
||||
void s_init(void)
|
||||
{
|
||||
#ifndef CONFIG_ICACHE_OFF
|
||||
icache_enable();
|
||||
#endif
|
||||
invalidate_dcache();
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
unsigned long rs;
|
||||
|
||||
/* We do not initialise DRAM here. We just query the size */
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size();
|
||||
|
||||
/* Now check it dynamically */
|
||||
rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size);
|
||||
if (rs) {
|
||||
printf("dynamic ram_size = %lu\n", rs);
|
||||
gd->bd->bi_dram[0].size = gd->ram_size = rs;
|
||||
}
|
||||
gd->ram_size = query_sdram_size();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -86,3 +69,17 @@ int checkboard(void)
|
|||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_DISPLAY_BOARDINFO */
|
||||
|
||||
#ifdef CONFIG_ARCH_CPU_INIT
|
||||
/*
|
||||
* Note this function is executed by the ARM7TDMI AVP. It does not return
|
||||
* in this case. It is also called once the A9 starts up, but does nothing in
|
||||
* that case.
|
||||
*/
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
/* Fire up the Cortex A9 */
|
||||
tegra2_start();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,5 +24,8 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI.
|
||||
PLATFORM_CPPFLAGS += -march=armv4
|
||||
# Tegra has an ARMv4T CPU which runs board_init_f(), so we must build this
|
||||
# file with compatible flags
|
||||
ifdef CONFIG_TEGRA2
|
||||
CFLAGS_arch/arm/lib/board.o += -march=armv4t
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -26,14 +26,6 @@
|
|||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
|
||||
_TEXT_BASE:
|
||||
.word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
|
||||
|
||||
.global invalidate_dcache
|
||||
invalidate_dcache:
|
||||
mov pc, lr
|
||||
|
||||
.align 5
|
||||
.global reset_cpu
|
||||
reset_cpu:
|
||||
|
|
@ -47,113 +39,3 @@ _loop_forever:
|
|||
b _loop_forever
|
||||
rstctl:
|
||||
.word PRM_RSTCTRL
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
ldr sp, SRAM_STACK
|
||||
str ip, [sp]
|
||||
mov ip, lr
|
||||
bl s_init @ go setup pll, mux & memory
|
||||
ldr ip, [sp]
|
||||
mov lr, ip
|
||||
|
||||
mov pc, lr @ back to arch calling code
|
||||
|
||||
|
||||
.globl startup_cpu
|
||||
startup_cpu:
|
||||
@ Initialize the AVP, clocks, and memory controller
|
||||
@ SDRAM is guaranteed to be on at this point
|
||||
|
||||
ldr r0, =cold_boot @ R0 = reset vector for CPU
|
||||
bl start_cpu @ start the CPU
|
||||
|
||||
@ Transfer control to the AVP code
|
||||
bl halt_avp
|
||||
|
||||
@ Should never get here
|
||||
_loop_forever2:
|
||||
b _loop_forever2
|
||||
|
||||
.globl cache_configure
|
||||
cache_configure:
|
||||
stmdb r13!,{r14}
|
||||
@ invalidate instruction cache
|
||||
mov r1, #0
|
||||
mcr p15, 0, r1, c7, c5, 0
|
||||
|
||||
@ invalidate the i&d tlb entries
|
||||
mcr p15, 0, r1, c8, c5, 0
|
||||
mcr p15, 0, r1, c8, c6, 0
|
||||
|
||||
@ enable instruction cache
|
||||
mrc p15, 0, r1, c1, c0, 0
|
||||
orr r1, r1, #(1<<12)
|
||||
mcr p15, 0, r1, c1, c0, 0
|
||||
|
||||
bl enable_scu
|
||||
|
||||
@ enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg
|
||||
mrc p15, 0, r0, c1, c0, 1
|
||||
orr r0, r0, #0x41
|
||||
mcr p15, 0, r0, c1, c0, 1
|
||||
|
||||
@ Now flush the Dcache
|
||||
mov r0, #0
|
||||
@ 256 cache lines
|
||||
mov r1, #256
|
||||
|
||||
invalidate_loop:
|
||||
add r1, r1, #-1
|
||||
mov r0, r1, lsl #5
|
||||
@ invalidate d-cache using line (way0)
|
||||
mcr p15, 0, r0, c7, c6, 2
|
||||
|
||||
orr r2, r0, #(1<<30)
|
||||
@ invalidate d-cache using line (way1)
|
||||
mcr p15, 0, r2, c7, c6, 2
|
||||
|
||||
orr r2, r0, #(2<<30)
|
||||
@ invalidate d-cache using line (way2)
|
||||
mcr p15, 0, r2, c7, c6, 2
|
||||
|
||||
orr r2, r0, #(3<<30)
|
||||
@ invalidate d-cache using line (way3)
|
||||
mcr p15, 0, r2, c7, c6, 2
|
||||
cmp r1, #0
|
||||
bne invalidate_loop
|
||||
|
||||
@ FIXME: should have ap20's L2 disabled too?
|
||||
invalidate_done:
|
||||
ldmia r13!,{pc}
|
||||
|
||||
.globl cold_boot
|
||||
cold_boot:
|
||||
msr cpsr_c, #0xD3
|
||||
@ Check current processor: CPU or AVP?
|
||||
@ If CPU, go to CPU boot code, else continue on AVP path
|
||||
|
||||
ldr r0, =NV_PA_PG_UP_BASE
|
||||
ldr r1, [r0]
|
||||
ldr r2, =PG_UP_TAG_AVP
|
||||
|
||||
@ are we the CPU?
|
||||
ldr sp, CPU_STACK
|
||||
cmp r1, r2
|
||||
@ yep, we are the CPU
|
||||
bne _armboot_start
|
||||
|
||||
@ AVP initialization follows this path
|
||||
ldr sp, AVP_STACK
|
||||
@ Init AVP and start CPU
|
||||
b startup_cpu
|
||||
|
||||
@ the literal pools origin
|
||||
.ltorg
|
||||
|
||||
SRAM_STACK:
|
||||
.word LOW_LEVEL_SRAM_STACK
|
||||
AVP_STACK:
|
||||
.word EARLY_AVP_STACK
|
||||
CPU_STACK:
|
||||
.word EARLY_CPU_STACK
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
#define __ASM_ARM_ARCH_CLOCK_H_
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct s5pc210_clock {
|
||||
struct exynos4_clock {
|
||||
unsigned char res1[0x4200];
|
||||
unsigned int src_leftbus;
|
||||
unsigned char res2[0x1fc];
|
||||
|
|
@ -19,33 +19,33 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#ifndef _S5PC2XX_CPU_H
|
||||
#define _S5PC2XX_CPU_H
|
||||
#ifndef _EXYNOS4_CPU_H
|
||||
#define _EXYNOS4_CPU_H
|
||||
|
||||
#define S5PC2XX_ADDR_BASE 0x10000000
|
||||
#define EXYNOS4_ADDR_BASE 0x10000000
|
||||
|
||||
/* S5PC210 */
|
||||
#define S5PC210_GPIO_PART3_BASE 0x03860000
|
||||
#define S5PC210_PRO_ID 0x10000000
|
||||
#define S5PC210_POWER_BASE 0x10020000
|
||||
#define S5PC210_SWRESET 0x10020400
|
||||
#define S5PC210_CLOCK_BASE 0x10030000
|
||||
#define S5PC210_SYSTIMER_BASE 0x10050000
|
||||
#define S5PC210_WATCHDOG_BASE 0x10060000
|
||||
#define S5PC210_MIU_BASE 0x10600000
|
||||
#define S5PC210_DMC0_BASE 0x10400000
|
||||
#define S5PC210_DMC1_BASE 0x10410000
|
||||
#define S5PC210_GPIO_PART2_BASE 0x11000000
|
||||
#define S5PC210_GPIO_PART1_BASE 0x11400000
|
||||
#define S5PC210_FIMD_BASE 0x11C00000
|
||||
#define S5PC210_USBOTG_BASE 0x12480000
|
||||
#define S5PC210_MMC_BASE 0x12510000
|
||||
#define S5PC210_SROMC_BASE 0x12570000
|
||||
#define S5PC210_USBPHY_BASE 0x125B0000
|
||||
#define S5PC210_UART_BASE 0x13800000
|
||||
#define S5PC210_ADC_BASE 0x13910000
|
||||
#define S5PC210_PWMTIMER_BASE 0x139D0000
|
||||
#define S5PC210_MODEM_BASE 0x13A00000
|
||||
/* EXYNOS4 */
|
||||
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
|
||||
#define EXYNOS4_PRO_ID 0x10000000
|
||||
#define EXYNOS4_POWER_BASE 0x10020000
|
||||
#define EXYNOS4_SWRESET 0x10020400
|
||||
#define EXYNOS4_CLOCK_BASE 0x10030000
|
||||
#define EXYNOS4_SYSTIMER_BASE 0x10050000
|
||||
#define EXYNOS4_WATCHDOG_BASE 0x10060000
|
||||
#define EXYNOS4_MIU_BASE 0x10600000
|
||||
#define EXYNOS4_DMC0_BASE 0x10400000
|
||||
#define EXYNOS4_DMC1_BASE 0x10410000
|
||||
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
|
||||
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
|
||||
#define EXYNOS4_FIMD_BASE 0x11C00000
|
||||
#define EXYNOS4_USBOTG_BASE 0x12480000
|
||||
#define EXYNOS4_MMC_BASE 0x12510000
|
||||
#define EXYNOS4_SROMC_BASE 0x12570000
|
||||
#define EXYNOS4_USBPHY_BASE 0x125B0000
|
||||
#define EXYNOS4_UART_BASE 0x13800000
|
||||
#define EXYNOS4_ADC_BASE 0x13910000
|
||||
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
|
||||
#define EXYNOS4_MODEM_BASE 0x13A00000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/io.h>
|
||||
|
|
@ -60,12 +60,12 @@ static inline int s5p_get_cpu_rev(void)
|
|||
|
||||
static inline void s5p_set_cpu_id(void)
|
||||
{
|
||||
s5p_cpu_id = readl(S5PC210_PRO_ID);
|
||||
s5p_cpu_id = readl(EXYNOS4_PRO_ID);
|
||||
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
|
||||
|
||||
/*
|
||||
* 0xC200: S5PC210 EVT0
|
||||
* 0xC210: S5PC210 EVT1
|
||||
* 0xC200: EXYNOS4210 EVT0
|
||||
* 0xC210: EXYNOS4210 EVT1
|
||||
*/
|
||||
if (s5p_cpu_id == 0xC200) {
|
||||
s5p_cpu_id |= 0x10;
|
||||
|
|
@ -81,13 +81,13 @@ static inline int cpu_is_##type(void) \
|
|||
return s5p_cpu_id == id ? 1 : 0; \
|
||||
}
|
||||
|
||||
IS_SAMSUNG_TYPE(s5pc210, 0xc210)
|
||||
IS_SAMSUNG_TYPE(exynos4, 0xc210)
|
||||
|
||||
#define SAMSUNG_BASE(device, base) \
|
||||
static inline unsigned int samsung_get_base_##device(void) \
|
||||
{ \
|
||||
if (cpu_is_s5pc210()) \
|
||||
return S5PC210_##base; \
|
||||
if (cpu_is_exynos4()) \
|
||||
return EXYNOS4_##base; \
|
||||
else \
|
||||
return 0; \
|
||||
}
|
||||
|
|
@ -110,4 +110,4 @@ SAMSUNG_BASE(usb_otg, USBOTG_BASE)
|
|||
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
|
||||
#endif
|
||||
|
||||
#endif /* _S5PC2XX_CPU_H */
|
||||
#endif /* _EXYNOS4_CPU_H */
|
||||
|
|
@ -32,7 +32,7 @@ struct s5p_gpio_bank {
|
|||
unsigned char res1[8];
|
||||
};
|
||||
|
||||
struct s5pc210_gpio_part1 {
|
||||
struct exynos4_gpio_part1 {
|
||||
struct s5p_gpio_bank a0;
|
||||
struct s5p_gpio_bank a1;
|
||||
struct s5p_gpio_bank b;
|
||||
|
|
@ -51,7 +51,7 @@ struct s5pc210_gpio_part1 {
|
|||
struct s5p_gpio_bank f3;
|
||||
};
|
||||
|
||||
struct s5pc210_gpio_part2 {
|
||||
struct exynos4_gpio_part2 {
|
||||
struct s5p_gpio_bank j0;
|
||||
struct s5p_gpio_bank j1;
|
||||
struct s5p_gpio_bank k0;
|
||||
|
|
@ -75,7 +75,7 @@ struct s5pc210_gpio_part2 {
|
|||
struct s5p_gpio_bank x3;
|
||||
};
|
||||
|
||||
struct s5pc210_gpio_part3 {
|
||||
struct exynos4_gpio_part3 {
|
||||
struct s5p_gpio_bank z;
|
||||
};
|
||||
|
||||
|
|
@ -92,27 +92,27 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
|
|||
/* GPIO pins per bank */
|
||||
#define GPIO_PER_BANK 8
|
||||
|
||||
#define s5pc210_gpio_part1_get_nr(bank, pin) \
|
||||
((((((unsigned int) &(((struct s5pc210_gpio_part1 *) \
|
||||
S5PC210_GPIO_PART1_BASE)->bank)) \
|
||||
- S5PC210_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
#define exynos4_gpio_part1_get_nr(bank, pin) \
|
||||
((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
|
||||
EXYNOS4_GPIO_PART1_BASE)->bank)) \
|
||||
- EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin)
|
||||
|
||||
#define GPIO_PART1_MAX ((sizeof(struct s5pc210_gpio_part1) \
|
||||
#define GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define s5pc210_gpio_part2_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct s5pc210_gpio_part2 *) \
|
||||
S5PC210_GPIO_PART2_BASE)->bank)) \
|
||||
- S5PC210_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
#define exynos4_gpio_part2_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
|
||||
EXYNOS4_GPIO_PART2_BASE)->bank)) \
|
||||
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
|
||||
|
||||
static inline unsigned int s5p_gpio_base(int nr)
|
||||
{
|
||||
if (nr < GPIO_PART1_MAX)
|
||||
return S5PC210_GPIO_PART1_BASE;
|
||||
return EXYNOS4_GPIO_PART1_BASE;
|
||||
else
|
||||
return S5PC210_GPIO_PART2_BASE;
|
||||
return EXYNOS4_GPIO_PART2_BASE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -29,4 +29,10 @@ int mx28_wait_mask_clr(struct mx28_register *reg, uint32_t mask, int timeout);
|
|||
|
||||
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#include <asm/arch/iomux-mx28.h>
|
||||
void mx28_common_spl_init(const iomux_cfg_t *iomux_setup,
|
||||
const unsigned int iomux_size);
|
||||
#endif
|
||||
|
||||
#endif /* __MX28_H__ */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,892 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
|
||||
#define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
|
||||
|
||||
struct imx_ccm_reg {
|
||||
u32 ccr; /* 0x0000 */
|
||||
u32 ccdr;
|
||||
u32 csr;
|
||||
u32 ccsr;
|
||||
u32 cacrr; /* 0x0010*/
|
||||
u32 cbcdr;
|
||||
u32 cbcmr;
|
||||
u32 cscmr1;
|
||||
u32 cscmr2; /* 0x0020 */
|
||||
u32 cscdr1;
|
||||
u32 cs1cdr;
|
||||
u32 cs2cdr;
|
||||
u32 cdcdr; /* 0x0030 */
|
||||
u32 chscdr;
|
||||
u32 cscdr2;
|
||||
u32 cscdr3;
|
||||
u32 cscdr4; /* 0x0040 */
|
||||
u32 resv0;
|
||||
u32 cdhipr;
|
||||
u32 cdcr;
|
||||
u32 ctor; /* 0x0050 */
|
||||
u32 clpcr;
|
||||
u32 cisr;
|
||||
u32 cimr;
|
||||
u32 ccosr; /* 0x0060 */
|
||||
u32 cgpr;
|
||||
u32 CCGR0;
|
||||
u32 CCGR1;
|
||||
u32 CCGR2; /* 0x0070 */
|
||||
u32 CCGR3;
|
||||
u32 CCGR4;
|
||||
u32 CCGR5;
|
||||
u32 CCGR6; /* 0x0080 */
|
||||
u32 CCGR7;
|
||||
u32 cmeor;
|
||||
u32 resv[0xfdd];
|
||||
u32 analog_pll_sys; /* 0x4000 */
|
||||
u32 analog_pll_sys_set;
|
||||
u32 analog_pll_sys_clr;
|
||||
u32 analog_pll_sys_tog;
|
||||
u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
|
||||
u32 analog_usb1_pll_480_ctrl_set;
|
||||
u32 analog_usb1_pll_480_ctrl_clr;
|
||||
u32 analog_usb1_pll_480_ctrl_tog;
|
||||
u32 analog_reserved0[4];
|
||||
u32 analog_pll_528; /* 0x4030 */
|
||||
u32 analog_pll_528_set;
|
||||
u32 analog_pll_528_clr;
|
||||
u32 analog_pll_528_tog;
|
||||
u32 analog_pll_528_ss; /* 0x4040 */
|
||||
u32 analog_reserved1[3];
|
||||
u32 analog_pll_528_num; /* 0x4050 */
|
||||
u32 analog_reserved2[3];
|
||||
u32 analog_pll_528_denom; /* 0x4060 */
|
||||
u32 analog_reserved3[3];
|
||||
u32 analog_pll_audio; /* 0x4070 */
|
||||
u32 analog_pll_audio_set;
|
||||
u32 analog_pll_audio_clr;
|
||||
u32 analog_pll_audio_tog;
|
||||
u32 analog_pll_audio_num; /* 0x4080*/
|
||||
u32 analog_reserved4[3];
|
||||
u32 analog_pll_audio_denom; /* 0x4090 */
|
||||
u32 analog_reserved5[3];
|
||||
u32 analog_pll_video; /* 0x40a0 */
|
||||
u32 analog_pll_video_set;
|
||||
u32 analog_pll_video_clr;
|
||||
u32 analog_pll_video_tog;
|
||||
u32 analog_pll_video_num; /* 0x40b0 */
|
||||
u32 analog_reserved6[3];
|
||||
u32 analog_pll_vedio_denon; /* 0x40c0 */
|
||||
u32 analog_reserved7[7];
|
||||
u32 analog_pll_enet; /* 0x40e0 */
|
||||
u32 analog_pll_enet_set;
|
||||
u32 analog_pll_enet_clr;
|
||||
u32 analog_pll_enet_tog;
|
||||
u32 analog_pfd_480; /* 0x40f0 */
|
||||
u32 analog_pfd_480_set;
|
||||
u32 analog_pfd_480_clr;
|
||||
u32 analog_pfd_480_tog;
|
||||
u32 analog_pfd_528; /* 0x4100 */
|
||||
u32 analog_pfd_528_set;
|
||||
u32 analog_pfd_528_clr;
|
||||
u32 analog_pfd_528_tog;
|
||||
};
|
||||
|
||||
/* Define the bits in register CCR */
|
||||
#define MXC_CCM_CCR_RBC_EN (1 << 27)
|
||||
#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
|
||||
#define MXC_CCM_CCR_WB_COUNT_MASK 0x7
|
||||
#define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
|
||||
#define MXC_CCM_CCR_COSC_EN (1 << 12)
|
||||
#define MXC_CCM_CCR_OSCNT_MASK 0xFF
|
||||
#define MXC_CCM_CCR_OSCNT_OFFSET 0
|
||||
|
||||
/* Define the bits in register CCDR */
|
||||
#define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
|
||||
#define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
|
||||
|
||||
/* Define the bits in register CSR */
|
||||
#define MXC_CCM_CSR_COSC_READY (1 << 5)
|
||||
#define MXC_CCM_CSR_REF_EN_B (1 << 0)
|
||||
|
||||
/* Define the bits in register CCSR */
|
||||
#define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
|
||||
#define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
|
||||
#define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
|
||||
#define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
|
||||
#define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
|
||||
#define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
|
||||
#define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
|
||||
#define MXC_CCM_CCSR_STEP_SEL (1 << 8)
|
||||
#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
|
||||
#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CACRR */
|
||||
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
|
||||
#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
|
||||
|
||||
/* Define the bits in register CBCDR */
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
|
||||
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
|
||||
#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
|
||||
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
|
||||
#define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
|
||||
#define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
|
||||
#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CBCMR */
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
|
||||
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
|
||||
#define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
|
||||
#define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
|
||||
#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
|
||||
#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
|
||||
|
||||
/* Define the bits in register CSCMR1 */
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
|
||||
#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
|
||||
#define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
|
||||
#define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
|
||||
#define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
|
||||
#define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
|
||||
#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
|
||||
|
||||
/* Define the bits in register CSCMR2 */
|
||||
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
|
||||
#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
|
||||
#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
|
||||
#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
|
||||
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
|
||||
#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
|
||||
|
||||
/* Define the bits in register CSCDR1 */
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
|
||||
#define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
|
||||
#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
|
||||
#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
|
||||
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
|
||||
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CS1CDR */
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
|
||||
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
|
||||
#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
|
||||
#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CS2CDR */
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
|
||||
#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
|
||||
|
||||
/* Define the bits in register CDCDR */
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
|
||||
#define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
|
||||
#define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
|
||||
#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
|
||||
|
||||
/* Define the bits in register CHSCCDR */
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
|
||||
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in register CSCDR2 */
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
|
||||
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
|
||||
#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in register CSCDR3 */
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
|
||||
|
||||
/* Define the bits in register CDHIPR */
|
||||
#define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
|
||||
#define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
|
||||
#define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
|
||||
#define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
|
||||
#define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
|
||||
#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
|
||||
|
||||
/* Define the bits in register CLPCR */
|
||||
#define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
|
||||
#define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
|
||||
#define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
|
||||
#define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
|
||||
#define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
|
||||
#define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
|
||||
#define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
|
||||
#define MXC_CCM_CLPCR_VSTBY (1 << 8)
|
||||
#define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
|
||||
#define MXC_CCM_CLPCR_SBYOS (1 << 6)
|
||||
#define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
|
||||
#define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
|
||||
#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
|
||||
#define MXC_CCM_CLPCR_LPM_MASK 0x3
|
||||
#define MXC_CCM_CLPCR_LPM_OFFSET 0
|
||||
|
||||
/* Define the bits in register CISR */
|
||||
#define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
|
||||
#define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CISR_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CISR_LRF_PLL 1
|
||||
|
||||
/* Define the bits in register CIMR */
|
||||
#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
|
||||
#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
|
||||
#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
|
||||
#define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
|
||||
#define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
|
||||
#define MXC_CCM_CIMR_MASK_LRF_PLL 1
|
||||
|
||||
/* Define the bits in register CCOSR */
|
||||
#define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
|
||||
#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
|
||||
#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
|
||||
#define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
|
||||
#define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
|
||||
#define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
|
||||
|
||||
/* Define the bits in registers CGPR */
|
||||
#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
|
||||
#define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
|
||||
#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
|
||||
|
||||
/* Define the bits in registers CCGRx */
|
||||
#define MXC_CCM_CCGR_CG_MASK 3
|
||||
|
||||
#define MXC_CCM_CCGR0_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
|
||||
#define MXC_CCM_CCGR0_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR0_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR0_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR0_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR0_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR0_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR0_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR0_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR0_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR0_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
|
||||
#define MXC_CCM_CCGR0_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
|
||||
#define MXC_CCM_CCGR0_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
|
||||
#define MXC_CCM_CCGR0_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR0_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
|
||||
#define MXC_CCM_CCGR0_CG0_OFFSET 0
|
||||
#define MXC_CCM_CCGR0_CG0_MASK 3
|
||||
|
||||
#define MXC_CCM_CCGR1_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR1_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR1_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR1_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR1_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR1_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR1_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR1_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR1_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR1_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR1_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR1_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR1_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR1_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR1_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR1_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR2_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR2_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR2_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR2_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR2_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR2_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR2_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR2_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR2_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR2_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR2_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR2_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR2_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR2_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR2_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR2_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR3_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR3_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR3_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR3_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR3_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR3_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR3_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR3_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR3_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR3_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR3_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR3_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR3_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR3_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR3_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR3_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR4_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR4_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR4_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR4_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR4_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR4_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR4_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR4_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR4_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR4_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR4_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR4_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR4_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR4_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR4_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR4_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR5_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR5_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR5_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR5_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR5_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR5_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR5_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR5_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR5_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR5_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR5_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR5_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR5_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR5_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR5_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR5_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR6_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR6_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR6_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR6_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR6_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR6_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR6_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR6_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR6_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR6_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR6_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR6_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR6_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR6_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR6_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR6_CG0_OFFSET 0
|
||||
|
||||
#define MXC_CCM_CCGR7_CG15_OFFSET 30
|
||||
#define MXC_CCM_CCGR7_CG14_OFFSET 28
|
||||
#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
|
||||
#define MXC_CCM_CCGR7_CG13_OFFSET 26
|
||||
#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
|
||||
#define MXC_CCM_CCGR7_CG12_OFFSET 24
|
||||
#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
|
||||
#define MXC_CCM_CCGR7_CG11_OFFSET 22
|
||||
#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
|
||||
#define MXC_CCM_CCGR7_CG10_OFFSET 20
|
||||
#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
|
||||
#define MXC_CCM_CCGR7_CG9_OFFSET 18
|
||||
#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
|
||||
#define MXC_CCM_CCGR7_CG8_OFFSET 16
|
||||
#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
|
||||
#define MXC_CCM_CCGR7_CG7_OFFSET 14
|
||||
#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
|
||||
#define MXC_CCM_CCGR7_CG6_OFFSET 12
|
||||
#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
|
||||
#define MXC_CCM_CCGR7_CG5_OFFSET 10
|
||||
#define MXC_CCM_CCGR7_CG4_OFFSET 8
|
||||
#define MXC_CCM_CCGR7_CG3_OFFSET 6
|
||||
#define MXC_CCM_CCGR7_CG2_OFFSET 4
|
||||
#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
|
||||
#define MXC_CCM_CCGR7_CG1_OFFSET 2
|
||||
#define MXC_CCM_CCGR7_CG0_OFFSET 0
|
||||
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_SYS_RSVD0 20
|
||||
#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
|
||||
#define BF_ANADIG_PLL_SYS_RSVD0(v) \
|
||||
(((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
|
||||
#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
|
||||
#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
|
||||
#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
|
||||
#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_SYS_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
|
||||
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
|
||||
(((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
|
||||
(((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
|
||||
#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
|
||||
#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
|
||||
|
||||
#define BM_ANADIG_PLL_528_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_528_RSVD1 19
|
||||
#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
|
||||
#define BF_ANADIG_PLL_528_RSVD1(v) \
|
||||
(((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
|
||||
#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_528_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_528_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_528_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_528_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_528_RSVD0 1
|
||||
#define BM_ANADIG_PLL_528_RSVD0 0x0000007E
|
||||
#define BF_ANADIG_PLL_528_RSVD0(v) \
|
||||
(((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
|
||||
#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
|
||||
|
||||
#define BP_ANADIG_PLL_528_SS_STOP 16
|
||||
#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
|
||||
#define BF_ANADIG_PLL_528_SS_STOP(v) \
|
||||
(((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
|
||||
#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
|
||||
#define BP_ANADIG_PLL_528_SS_STEP 0
|
||||
#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
|
||||
#define BF_ANADIG_PLL_528_SS_STEP(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
|
||||
|
||||
#define BP_ANADIG_PLL_528_NUM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
|
||||
#define BP_ANADIG_PLL_528_NUM_A 0
|
||||
#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_528_NUM_A(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
|
||||
|
||||
#define BP_ANADIG_PLL_528_DENOM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
|
||||
#define BP_ANADIG_PLL_528_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_528_DENOM_B(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
|
||||
|
||||
#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_AUDIO_RSVD0 22
|
||||
#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
|
||||
#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
|
||||
(((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
|
||||
#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
|
||||
#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
|
||||
#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
|
||||
#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
|
||||
(((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
|
||||
#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
|
||||
|
||||
#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
|
||||
#define BP_ANADIG_PLL_AUDIO_NUM_A 0
|
||||
#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
|
||||
|
||||
#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
|
||||
#define BP_ANADIG_PLL_AUDIO_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
|
||||
|
||||
#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_VIDEO_RSVD0 22
|
||||
#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
|
||||
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
|
||||
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
|
||||
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
|
||||
#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
|
||||
#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
|
||||
#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
|
||||
(((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
|
||||
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
|
||||
#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
|
||||
|
||||
#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
|
||||
#define BP_ANADIG_PLL_VIDEO_NUM_A 0
|
||||
#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
|
||||
|
||||
#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
|
||||
#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
|
||||
#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
|
||||
(((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
|
||||
#define BP_ANADIG_PLL_VIDEO_DENOM_B 0
|
||||
#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
|
||||
#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
|
||||
|
||||
#define BM_ANADIG_PLL_ENET_LOCK 0x80000000
|
||||
#define BP_ANADIG_PLL_ENET_RSVD1 21
|
||||
#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
|
||||
#define BF_ANADIG_PLL_ENET_RSVD1(v) \
|
||||
(((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
|
||||
#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
|
||||
#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
|
||||
#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
|
||||
#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
|
||||
#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
|
||||
#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
|
||||
(((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
|
||||
#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
|
||||
#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
|
||||
#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
|
||||
#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
|
||||
#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
|
||||
#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
|
||||
#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
|
||||
#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
|
||||
#define BP_ANADIG_PLL_ENET_RSVD0 2
|
||||
#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
|
||||
#define BF_ANADIG_PLL_ENET_RSVD0(v) \
|
||||
(((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
|
||||
#define BP_ANADIG_PLL_ENET_DIV_SELECT 0
|
||||
#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
|
||||
#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
|
||||
(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
|
||||
|
||||
#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
|
||||
#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
|
||||
#define BP_ANADIG_PFD_480_PFD3_FRAC 24
|
||||
#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
|
||||
#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
|
||||
(((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
|
||||
#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
|
||||
#define BP_ANADIG_PFD_480_PFD2_FRAC 16
|
||||
#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
|
||||
#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
|
||||
(((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
|
||||
#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
|
||||
#define BP_ANADIG_PFD_480_PFD1_FRAC 8
|
||||
#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
|
||||
#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
|
||||
(((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
|
||||
#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
|
||||
#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
|
||||
#define BP_ANADIG_PFD_480_PFD0_FRAC 0
|
||||
#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
|
||||
#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
|
||||
(((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
|
||||
|
||||
#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
|
||||
#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
|
||||
#define BP_ANADIG_PFD_528_PFD3_FRAC 24
|
||||
#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
|
||||
#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
|
||||
(((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
|
||||
#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
|
||||
#define BP_ANADIG_PFD_528_PFD2_FRAC 16
|
||||
#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
|
||||
#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
|
||||
(((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
|
||||
#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
|
||||
#define BP_ANADIG_PFD_528_PFD1_FRAC 8
|
||||
#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
|
||||
#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
|
||||
(((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
|
||||
#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
|
||||
#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
|
||||
#define BP_ANADIG_PFD_528_PFD0_FRAC 0
|
||||
#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
|
||||
#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
|
||||
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
|
||||
|
||||
#define PLL2_PFD0_FREQ 352000000
|
||||
#define PLL2_PFD1_FREQ 594000000
|
||||
#define PLL2_PFD2_FREQ 400000000
|
||||
#define PLL2_PFD2_DIV_FREQ 200000000
|
||||
#define PLL3_PFD0_FREQ 720000000
|
||||
#define PLL3_PFD1_FREQ 540000000
|
||||
#define PLL3_PFD2_FREQ 508200000
|
||||
#define PLL3_PFD3_FREQ 454700000
|
||||
#define PLL3_80M 80000000
|
||||
#define PLL3_60M 60000000
|
||||
|
||||
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_CLOCK_H
|
||||
#define __ASM_ARCH_CLOCK_H
|
||||
|
||||
enum mxc_clock {
|
||||
MXC_ARM_CLK = 0,
|
||||
MXC_PER_CLK,
|
||||
MXC_AHB_CLK,
|
||||
MXC_IPG_CLK,
|
||||
MXC_IPG_PERCLK,
|
||||
MXC_UART_CLK,
|
||||
MXC_CSPI_CLK,
|
||||
MXC_AXI_CLK,
|
||||
MXC_EMI_SLOW_CLK,
|
||||
MXC_DDR_CLK,
|
||||
MXC_ESDHC_CLK,
|
||||
MXC_ESDHC2_CLK,
|
||||
MXC_ESDHC3_CLK,
|
||||
MXC_ESDHC4_CLK,
|
||||
MXC_SATA_CLK,
|
||||
MXC_NFC_CLK,
|
||||
};
|
||||
|
||||
u32 imx_get_uartclk(void);
|
||||
u32 imx_get_fecclk(void);
|
||||
unsigned int mxc_get_clock(enum mxc_clock clk);
|
||||
|
||||
#endif /* __ASM_ARCH_CLOCK_H */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
* Copyright (C) 2011
|
||||
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -21,9 +21,15 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SERIAL_TEGRA_H_
|
||||
#define _SERIAL_TEGRA_H_
|
||||
|
||||
#include <asm/arch/uart.h>
|
||||
#ifndef __ASM_ARCH_MX6_GPIO_H
|
||||
#define __ASM_ARCH_MX6_GPIO_H
|
||||
|
||||
#endif /* _SERIAL_TEGRA_H_ */
|
||||
/* GPIO registers */
|
||||
struct gpio_regs {
|
||||
u32 gpio_dr;
|
||||
u32 gpio_dir;
|
||||
u32 gpio_psr;
|
||||
};
|
||||
|
||||
#endif /* __ASM_ARCH_MX6_GPIO_H */
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
|
||||
#define __ASM_ARCH_MX6_IMX_REGS_H__
|
||||
|
||||
#define ROMCP_ARB_BASE_ADDR 0x00000000
|
||||
#define ROMCP_ARB_END_ADDR 0x000FFFFF
|
||||
#define CAAM_ARB_BASE_ADDR 0x00100000
|
||||
#define CAAM_ARB_END_ADDR 0x00103FFF
|
||||
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
|
||||
#define APBH_DMA_ARB_END_ADDR 0x00117FFF
|
||||
#define HDMI_ARB_BASE_ADDR 0x00120000
|
||||
#define HDMI_ARB_END_ADDR 0x00128FFF
|
||||
#define GPU_3D_ARB_BASE_ADDR 0x00130000
|
||||
#define GPU_3D_ARB_END_ADDR 0x00133FFF
|
||||
#define GPU_2D_ARB_BASE_ADDR 0x00134000
|
||||
#define GPU_2D_ARB_END_ADDR 0x00137FFF
|
||||
#define DTCP_ARB_BASE_ADDR 0x00138000
|
||||
#define DTCP_ARB_END_ADDR 0x0013BFFF
|
||||
|
||||
/* GPV - PL301 configuration ports */
|
||||
#define GPV2_BASE_ADDR 0x00200000
|
||||
#define GPV3_BASE_ADDR 0x00300000
|
||||
#define GPV4_BASE_ADDR 0x00800000
|
||||
#define IRAM_BASE_ADDR 0x00900000
|
||||
#define SCU_BASE_ADDR 0x00A00000
|
||||
#define IC_INTERFACES_BASE_ADDR 0x00A00100
|
||||
#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
|
||||
#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
|
||||
#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
|
||||
#define GPV0_BASE_ADDR 0x00B00000
|
||||
#define GPV1_BASE_ADDR 0x00C00000
|
||||
#define PCIE_ARB_BASE_ADDR 0x01000000
|
||||
#define PCIE_ARB_END_ADDR 0x01FFFFFF
|
||||
|
||||
#define AIPS1_ARB_BASE_ADDR 0x02000000
|
||||
#define AIPS1_ARB_END_ADDR 0x020FFFFF
|
||||
#define AIPS2_ARB_BASE_ADDR 0x02100000
|
||||
#define AIPS2_ARB_END_ADDR 0x021FFFFF
|
||||
#define SATA_ARB_BASE_ADDR 0x02200000
|
||||
#define SATA_ARB_END_ADDR 0x02203FFF
|
||||
#define OPENVG_ARB_BASE_ADDR 0x02204000
|
||||
#define OPENVG_ARB_END_ADDR 0x02207FFF
|
||||
#define HSI_ARB_BASE_ADDR 0x02208000
|
||||
#define HSI_ARB_END_ADDR 0x0220BFFF
|
||||
#define IPU1_ARB_BASE_ADDR 0x02400000
|
||||
#define IPU1_ARB_END_ADDR 0x027FFFFF
|
||||
#define IPU2_ARB_BASE_ADDR 0x02800000
|
||||
#define IPU2_ARB_END_ADDR 0x02BFFFFF
|
||||
#define WEIM_ARB_BASE_ADDR 0x08000000
|
||||
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
|
||||
|
||||
#define MMDC0_ARB_BASE_ADDR 0x10000000
|
||||
#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
|
||||
#define MMDC1_ARB_BASE_ADDR 0x80000000
|
||||
#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
|
||||
|
||||
/* Defines for Blocks connected via AIPS (SkyBlue) */
|
||||
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
|
||||
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
|
||||
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
|
||||
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
|
||||
|
||||
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
|
||||
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
|
||||
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
|
||||
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
|
||||
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
|
||||
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
|
||||
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
|
||||
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
|
||||
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
|
||||
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
|
||||
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
|
||||
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
|
||||
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
|
||||
#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
|
||||
#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
|
||||
|
||||
#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
|
||||
#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
|
||||
#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
|
||||
#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
|
||||
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
|
||||
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
|
||||
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
|
||||
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
|
||||
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
|
||||
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
|
||||
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
|
||||
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
|
||||
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
|
||||
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
|
||||
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
|
||||
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
|
||||
#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
|
||||
#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
|
||||
#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
|
||||
#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
|
||||
#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
|
||||
#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
|
||||
#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
|
||||
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
|
||||
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
|
||||
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
|
||||
#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
|
||||
#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
|
||||
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
|
||||
|
||||
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
|
||||
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
|
||||
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
|
||||
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
|
||||
#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
|
||||
#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
|
||||
#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
|
||||
#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
|
||||
#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
|
||||
#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
|
||||
#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
|
||||
#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
|
||||
#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
|
||||
#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
|
||||
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
|
||||
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
|
||||
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
|
||||
#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
|
||||
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
|
||||
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
|
||||
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
|
||||
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
|
||||
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
|
||||
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
|
||||
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
|
||||
#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
|
||||
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
|
||||
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
|
||||
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
|
||||
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
|
||||
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
|
||||
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
|
||||
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
|
||||
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
|
||||
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
|
||||
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
|
||||
|
||||
#define CHIP_REV_1_0 0x10
|
||||
#define IRAM_SIZE 0x00040000
|
||||
#define IMX_IIM_BASE OCOTP_BASE_ADDR
|
||||
|
||||
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
|
||||
#include <asm/types.h>
|
||||
|
||||
extern void imx_get_mac_from_fuse(unsigned char *mac);
|
||||
|
||||
/* System Reset Controller (SRC) */
|
||||
struct src {
|
||||
u32 scr;
|
||||
u32 sbmr1;
|
||||
u32 srsr;
|
||||
u32 reserved1[2];
|
||||
u32 sisr;
|
||||
u32 simr;
|
||||
u32 sbmr2;
|
||||
u32 gpr1;
|
||||
u32 gpr2;
|
||||
u32 gpr3;
|
||||
u32 gpr4;
|
||||
u32 gpr5;
|
||||
u32 gpr6;
|
||||
u32 gpr7;
|
||||
u32 gpr8;
|
||||
u32 gpr9;
|
||||
u32 gpr10;
|
||||
};
|
||||
|
||||
struct iim_regs {
|
||||
u32 ctrl;
|
||||
u32 ctrl_set;
|
||||
u32 ctrl_clr;
|
||||
u32 ctrl_tog;
|
||||
u32 timing;
|
||||
u32 rsvd0[3];
|
||||
u32 data;
|
||||
u32 rsvd1[3];
|
||||
u32 read_ctrl;
|
||||
u32 rsvd2[3];
|
||||
u32 fuse_data;
|
||||
u32 rsvd3[3];
|
||||
u32 sticky;
|
||||
u32 rsvd4[3];
|
||||
u32 scs;
|
||||
u32 scs_set;
|
||||
u32 scs_clr;
|
||||
u32 scs_tog;
|
||||
u32 crc_addr;
|
||||
u32 rsvd5[3];
|
||||
u32 crc_value;
|
||||
u32 rsvd6[3];
|
||||
u32 version;
|
||||
u32 rsvd7[0xd8];
|
||||
|
||||
struct fuse_bank {
|
||||
u32 fuse_regs[0x20];
|
||||
} bank[15];
|
||||
};
|
||||
|
||||
struct fuse_bank4_regs {
|
||||
u32 sjc_resp_low;
|
||||
u32 rsvd0[3];
|
||||
u32 sjc_resp_high;
|
||||
u32 rsvd1[3];
|
||||
u32 mac_addr_low;
|
||||
u32 rsvd2[3];
|
||||
u32 mac_addr_high;
|
||||
u32 rsvd3[0x13];
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLER__*/
|
||||
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Based on Linux i.MX iomux-v3.h file:
|
||||
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
|
||||
* <armlinux@phytec.de>
|
||||
*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; either version 2
|
||||
* of the License, or (at your option) any later version.
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
||||
* MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
#ifndef __MACH_IOMUX_V3_H__
|
||||
#define __MACH_IOMUX_V3_H__
|
||||
|
||||
/*
|
||||
* build IOMUX_PAD structure
|
||||
*
|
||||
* This iomux scheme is based around pads, which are the physical balls
|
||||
* on the processor.
|
||||
*
|
||||
* - Each pad has a pad control register (IOMUXC_SW_PAD_CTRL_x) which controls
|
||||
* things like driving strength and pullup/pulldown.
|
||||
* - Each pad can have but not necessarily does have an output routing register
|
||||
* (IOMUXC_SW_MUX_CTL_PAD_x).
|
||||
* - Each pad can have but not necessarily does have an input routing register
|
||||
* (IOMUXC_x_SELECT_INPUT)
|
||||
*
|
||||
* The three register sets do not have a fixed offset to each other,
|
||||
* hence we order this table by pad control registers (which all pads
|
||||
* have) and put the optional i/o routing registers into additional
|
||||
* fields.
|
||||
*
|
||||
* The naming convention for the pad modes is SOC_PAD_<padname>__<padmode>
|
||||
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
|
||||
*
|
||||
* IOMUX/PAD Bit field definitions
|
||||
*
|
||||
* MUX_CTRL_OFS: 0..11 (12)
|
||||
* PAD_CTRL_OFS: 12..23 (12)
|
||||
* SEL_INPUT_OFS: 24..35 (12)
|
||||
* MUX_MODE + SION: 36..40 (5)
|
||||
* PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
|
||||
* SEL_INP: 59..62 (4)
|
||||
* reserved: 63 (1)
|
||||
*/
|
||||
|
||||
typedef u64 iomux_v3_cfg_t;
|
||||
|
||||
#define MUX_CTRL_OFS_SHIFT 0
|
||||
#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
|
||||
#define MUX_PAD_CTRL_OFS_SHIFT 12
|
||||
#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
|
||||
MUX_PAD_CTRL_OFS_SHIFT)
|
||||
#define MUX_SEL_INPUT_OFS_SHIFT 24
|
||||
#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << \
|
||||
MUX_SEL_INPUT_OFS_SHIFT)
|
||||
|
||||
#define MUX_MODE_SHIFT 36
|
||||
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
|
||||
#define MUX_PAD_CTRL_SHIFT 41
|
||||
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT)
|
||||
#define MUX_SEL_INPUT_SHIFT 59
|
||||
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
|
||||
|
||||
#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
|
||||
|
||||
#define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \
|
||||
sel_input, pad_ctrl) \
|
||||
(((iomux_v3_cfg_t)(mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
|
||||
((iomux_v3_cfg_t)(sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT)| \
|
||||
((iomux_v3_cfg_t)(sel_input) << MUX_SEL_INPUT_SHIFT))
|
||||
|
||||
#define NO_PAD_CTRL (1 << 17)
|
||||
#define GPIO_PIN_MASK 0x1f
|
||||
#define GPIO_PORT_SHIFT 5
|
||||
#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define MUX_CONFIG_SION (0x1 << 4)
|
||||
|
||||
int imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
|
||||
int imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
|
||||
|
||||
#endif /* __MACH_IOMUX_V3_H__*/
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* (C) Copyright 2009
|
||||
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PROTO_H_
|
||||
#define _SYS_PROTO_H_
|
||||
|
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
|
||||
|
||||
u32 get_cpu_rev(void);
|
||||
|
||||
/*
|
||||
* Initializes on-chip ethernet controllers.
|
||||
* to override, implement board_eth_init()
|
||||
*/
|
||||
|
||||
int fecmxc_initialize(bd_t *bis);
|
||||
|
||||
#endif
|
||||
|
|
@ -46,6 +46,9 @@ extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
|
|||
int cpu_init(void);
|
||||
int cleanup_before_linux(void);
|
||||
|
||||
/* Set up ARMv7 MMU, caches and TLBs */
|
||||
void cpu_init_cp15(void);
|
||||
|
||||
/* cpu/.../arch/cpu.c */
|
||||
int arch_cpu_init(void);
|
||||
int arch_misc_init(void);
|
||||
|
|
|
|||
|
|
@ -27,10 +27,8 @@ LIB = $(obj)lib$(BOARD).o
|
|||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
COBJS := m28evk.o
|
||||
endif
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
COBJS := mem_init.o mmc_boot.o power_init.o memsize.o
|
||||
else
|
||||
COBJS := spl_boot.o
|
||||
endif
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
|
|
@ -41,11 +39,6 @@ $(LIB): $(obj).depend $(OBJS)
|
|||
|
||||
all: $(ALL)
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
memsize.c:
|
||||
ln -sf $(TOPDIR)/common/memsize.c $@
|
||||
endif
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ static int m28_mmc_wp(int id)
|
|||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
/* Configure WP as output */
|
||||
/* Configure WP as input. */
|
||||
gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
|
||||
|
||||
return mxsmmc_initialize(bis, 0, m28_mmc_wp);
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Freescale i.MX28 Boot setup
|
||||
* DENX M28 Boot setup
|
||||
*
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
|
|
@ -27,23 +27,8 @@
|
|||
#include <config.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/iomux-mx28.h>
|
||||
|
||||
#include "m28_init.h"
|
||||
|
||||
/*
|
||||
* This delay function is intended to be used only in early stage of boot, where
|
||||
* clock are not set up yet. The timer used here is reset on every boot and
|
||||
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
|
||||
* code simple, it doesn't take rolling into consideration.
|
||||
*/
|
||||
#define HW_DIGCTRL_MICROSECONDS 0x8001c0c0
|
||||
void early_delay(int delay)
|
||||
{
|
||||
uint32_t st = readl(HW_DIGCTRL_MICROSECONDS);
|
||||
st += delay;
|
||||
while (st > readl(HW_DIGCTRL_MICROSECONDS))
|
||||
;
|
||||
}
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
|
||||
#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA)
|
||||
|
|
@ -109,10 +94,6 @@ const iomux_cfg_t iomux_setup[] = {
|
|||
MX28_PAD_GPMI_RDY2__CAN0_TX,
|
||||
MX28_PAD_GPMI_RDY3__CAN0_RX,
|
||||
|
||||
/* I2C */
|
||||
MX28_PAD_I2C0_SCL__I2C0_SCL,
|
||||
MX28_PAD_I2C0_SDA__I2C0_SDA,
|
||||
|
||||
/* TSC2007 */
|
||||
MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MUX_CONFIG_TSC,
|
||||
|
||||
|
|
@ -235,39 +216,5 @@ const iomux_cfg_t iomux_setup[] = {
|
|||
|
||||
void board_init_ll(void)
|
||||
{
|
||||
mxs_iomux_setup_multiple_pads(iomux_setup, ARRAY_SIZE(iomux_setup));
|
||||
mx28_power_init();
|
||||
mx28_mem_init();
|
||||
mx28_power_wait_pswitch();
|
||||
}
|
||||
|
||||
/* Support aparatus */
|
||||
inline void board_init_f(unsigned long bootflag)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
inline void board_init_r(gd_t *id, ulong dest_addr)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
}
|
||||
|
||||
inline int printf(const char *fmt, ...)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
inline void __coloured_LED_init(void) {}
|
||||
inline void __red_LED_on(void) {}
|
||||
void coloured_LED_init(void)
|
||||
__attribute__((weak, alias("__coloured_LED_init")));
|
||||
void red_LED_on(void)
|
||||
__attribute__((weak, alias("__red_LED_on")));
|
||||
void hang(void) __attribute__ ((noreturn));
|
||||
void hang(void)
|
||||
{
|
||||
for (;;)
|
||||
;
|
||||
mx28_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS := mx6qarm2.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
# Copyright (C) 2011 Freescale Semiconductor, Inc.
|
||||
# Jason Liu <r64343@freescale.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not write to the Free Software
|
||||
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
# Refer docs/README.imxmage for more details about how-to configure
|
||||
# and create imximage boot image
|
||||
#
|
||||
# The syntax is taken as close as possible with the kwbimage
|
||||
|
||||
# image version
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
# Boot Device : one of
|
||||
# spi, sd (the board has no nand neither onenand)
|
||||
|
||||
BOOT_FROM sd
|
||||
|
||||
# Device Configuration Data (DCD)
|
||||
#
|
||||
# Each entry must have the format:
|
||||
# Addr-type Address Value
|
||||
#
|
||||
# where:
|
||||
# Addr-type register length (1,2 or 4 bytes)
|
||||
# Address absolute address of the register
|
||||
# value value to be stored in the register
|
||||
DATA 4 0x020e05a8 0x00000030
|
||||
DATA 4 0x020e05b0 0x00000030
|
||||
DATA 4 0x020e0524 0x00000030
|
||||
DATA 4 0x020e051c 0x00000030
|
||||
|
||||
DATA 4 0x020e0518 0x00000030
|
||||
DATA 4 0x020e050c 0x00000030
|
||||
DATA 4 0x020e05b8 0x00000030
|
||||
DATA 4 0x020e05c0 0x00000030
|
||||
|
||||
DATA 4 0x020e05ac 0x00020030
|
||||
DATA 4 0x020e05b4 0x00020030
|
||||
DATA 4 0x020e0528 0x00020030
|
||||
DATA 4 0x020e0520 0x00020030
|
||||
|
||||
DATA 4 0x020e0514 0x00020030
|
||||
DATA 4 0x020e0510 0x00020030
|
||||
DATA 4 0x020e05bc 0x00020030
|
||||
DATA 4 0x020e05c4 0x00020030
|
||||
|
||||
DATA 4 0x020e056c 0x00020030
|
||||
DATA 4 0x020e0578 0x00020030
|
||||
DATA 4 0x020e0588 0x00020030
|
||||
DATA 4 0x020e0594 0x00020030
|
||||
|
||||
DATA 4 0x020e057c 0x00020030
|
||||
DATA 4 0x020e0590 0x00003000
|
||||
DATA 4 0x020e0598 0x00003000
|
||||
DATA 4 0x020e058c 0x00000000
|
||||
|
||||
DATA 4 0x020e059c 0x00003030
|
||||
DATA 4 0x020e05a0 0x00003030
|
||||
DATA 4 0x020e0784 0x00000030
|
||||
DATA 4 0x020e0788 0x00000030
|
||||
|
||||
DATA 4 0x020e0794 0x00000030
|
||||
DATA 4 0x020e079c 0x00000030
|
||||
DATA 4 0x020e07a0 0x00000030
|
||||
DATA 4 0x020e07a4 0x00000030
|
||||
|
||||
DATA 4 0x020e07a8 0x00000030
|
||||
DATA 4 0x020e0748 0x00000030
|
||||
DATA 4 0x020e074c 0x00000030
|
||||
DATA 4 0x020e0750 0x00020000
|
||||
|
||||
DATA 4 0x020e0758 0x00000000
|
||||
DATA 4 0x020e0774 0x00020000
|
||||
DATA 4 0x020e078c 0x00000030
|
||||
DATA 4 0x020e0798 0x000C0000
|
||||
|
||||
DATA 4 0x021b081c 0x33333333
|
||||
DATA 4 0x021b0820 0x33333333
|
||||
DATA 4 0x021b0824 0x33333333
|
||||
DATA 4 0x021b0828 0x33333333
|
||||
|
||||
DATA 4 0x021b481c 0x33333333
|
||||
DATA 4 0x021b4820 0x33333333
|
||||
DATA 4 0x021b4824 0x33333333
|
||||
DATA 4 0x021b4828 0x33333333
|
||||
|
||||
DATA 4 0x021b0018 0x00081740
|
||||
|
||||
DATA 4 0x021b001c 0x00008000
|
||||
DATA 4 0x021b000c 0x555A7975
|
||||
DATA 4 0x021b0010 0xFF538E64
|
||||
DATA 4 0x021b0014 0x01FF00DB
|
||||
DATA 4 0x021b002c 0x000026D2
|
||||
|
||||
DATA 4 0x021b0030 0x005B0E21
|
||||
DATA 4 0x021b0008 0x09444040
|
||||
DATA 4 0x021b0004 0x00025576
|
||||
DATA 4 0x021b0040 0x00000027
|
||||
DATA 4 0x021b0000 0xC31A0000
|
||||
|
||||
DATA 4 0x021b001c 0x04088032
|
||||
DATA 4 0x021b001c 0x0408803A
|
||||
DATA 4 0x021b001c 0x00008033
|
||||
DATA 4 0x021b001c 0x0000803B
|
||||
DATA 4 0x021b001c 0x00428031
|
||||
DATA 4 0x021b001c 0x00428039
|
||||
DATA 4 0x021b001c 0x09408030
|
||||
DATA 4 0x021b001c 0x09408038
|
||||
|
||||
DATA 4 0x021b001c 0x04008040
|
||||
DATA 4 0x021b001c 0x04008048
|
||||
DATA 4 0x021b0800 0xA1380003
|
||||
DATA 4 0x021b4800 0xA1380003
|
||||
DATA 4 0x021b0020 0x00005800
|
||||
DATA 4 0x021b0818 0x00022227
|
||||
DATA 4 0x021b4818 0x00022227
|
||||
|
||||
DATA 4 0x021b083c 0x434B0350
|
||||
DATA 4 0x021b0840 0x034C0359
|
||||
DATA 4 0x021b483c 0x434B0350
|
||||
DATA 4 0x021b4840 0x03650348
|
||||
DATA 4 0x021b0848 0x4436383B
|
||||
DATA 4 0x021b4848 0x39393341
|
||||
DATA 4 0x021b0850 0x35373933
|
||||
DATA 4 0x021b4850 0x48254A36
|
||||
|
||||
DATA 4 0x021b080c 0x001F001F
|
||||
DATA 4 0x021b0810 0x001F001F
|
||||
|
||||
DATA 4 0x021b480c 0x00440044
|
||||
DATA 4 0x021b4810 0x00440044
|
||||
|
||||
DATA 4 0x021b08b8 0x00000800
|
||||
DATA 4 0x021b48b8 0x00000800
|
||||
|
||||
DATA 4 0x021b001c 0x00000000
|
||||
DATA 4 0x021b0404 0x00011006
|
||||
|
||||
DATA 4 0x020e0010 0xF00000FF
|
||||
DATA 4 0x020e0018 0x00070007
|
||||
DATA 4 0x020e001c 0x00070007
|
||||
|
||||
DATA 4 0x020c4068 0x00C03F3F
|
||||
DATA 4 0x020c406c 0x0030FC00
|
||||
DATA 4 0x020c4070 0x0FFFC000
|
||||
DATA 4 0x020c4074 0x3FF00000
|
||||
DATA 4 0x020c4078 0x00FFF300
|
||||
DATA 4 0x020c407c 0x0F0000C3
|
||||
DATA 4 0x020c4080 0x000003FC
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx6x_pins.h>
|
||||
#include <asm/arch/iomux-v3.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t uart4_pads[] = {
|
||||
MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t usdhc3_pads[] = {
|
||||
MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t usdhc4_pads[] = {
|
||||
MX6Q_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
struct fsl_esdhc_cfg usdhc_cfg[2] = {
|
||||
{USDHC3_BASE_ADDR, 1},
|
||||
{USDHC4_BASE_ADDR, 1},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
|
||||
gpio_direction_input(171); /*GPIO6_11*/
|
||||
*cd = gpio_get_value(171);
|
||||
} else /* Don't have the CD GPIO pin on board */
|
||||
*cd = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
s32 status = 0;
|
||||
u32 index = 0;
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) then supported by the board (%d)\n",
|
||||
index + 1, CONFIG_SYS_FSL_USDHC_NUM);
|
||||
return status;
|
||||
}
|
||||
|
||||
status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX6Q-Armadillo2\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -33,10 +33,6 @@
|
|||
#include <asm/arch/uart.h>
|
||||
#include "board.h"
|
||||
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
#include <mmc.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
const struct tegra2_sysinfo sysinfo = {
|
||||
|
|
@ -100,33 +96,6 @@ static void pin_mux_uart(void)
|
|||
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
/*
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
static void pin_mux_mmc(void)
|
||||
{
|
||||
/* SDMMC4: config 3, x8 on 2nd set of pins */
|
||||
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
|
||||
|
||||
pinmux_tristate_disable(PINGRP_ATB);
|
||||
pinmux_tristate_disable(PINGRP_GMA);
|
||||
pinmux_tristate_disable(PINGRP_GME);
|
||||
|
||||
/* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
|
||||
pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
|
||||
pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
|
||||
pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
|
||||
|
||||
pinmux_tristate_disable(PINGRP_SDC);
|
||||
pinmux_tristate_disable(PINGRP_SDD);
|
||||
pinmux_tristate_disable(PINGRP_SDB);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Routine: board_init
|
||||
* Description: Early hardware init.
|
||||
|
|
@ -142,30 +111,12 @@ int board_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
/* this is a weak define that we are overriding */
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
debug("board_mmc_init called\n");
|
||||
/* Enable muxes, etc. for SDMMC controllers */
|
||||
pin_mux_mmc();
|
||||
gpio_config_mmc();
|
||||
|
||||
debug("board_mmc_init: init eMMC\n");
|
||||
/* init dev 0, eMMC chip, with 4-bit bus */
|
||||
tegra2_mmc_init(0, 4);
|
||||
|
||||
debug("board_mmc_init: init SD slot\n");
|
||||
/* init dev 1, SD slot, with 4-bit bus */
|
||||
tegra2_mmc_init(1, 4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* We didn't do this init in start.S, so do it now */
|
||||
cpu_init_cp15();
|
||||
|
||||
/* Initialize essential common plls */
|
||||
clock_early_init();
|
||||
|
||||
|
|
@ -177,9 +128,6 @@ int board_early_init_f(void)
|
|||
|
||||
/* Initialize periph GPIOs */
|
||||
gpio_config_uart();
|
||||
|
||||
/* Init UART, scratch regs, and start CPU */
|
||||
tegra2_start();
|
||||
return 0;
|
||||
}
|
||||
#endif /* EARLY_INIT */
|
||||
|
|
|
|||
|
|
@ -24,9 +24,7 @@
|
|||
#ifndef _BOARD_H_
|
||||
#define _BOARD_H_
|
||||
|
||||
void tegra2_start(void);
|
||||
void gpio_config_uart(void);
|
||||
void gpio_config_mmc(void);
|
||||
int tegra2_mmc_init(int dev_index, int bus_width);
|
||||
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
|
||||
|
||||
#endif /* BOARD_H */
|
||||
|
|
|
|||
|
|
@ -24,9 +24,12 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/tegra2.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/gpio.h>
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
#include <mmc.h>
|
||||
#endif
|
||||
#include "../common/board.h"
|
||||
|
||||
/*
|
||||
* Routine: gpio_config_uart
|
||||
|
|
@ -38,23 +41,55 @@ void gpio_config_uart(void)
|
|||
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
/*
|
||||
* Routine: gpio_config_mmc
|
||||
* Description: Set GPIOs for SD card
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
void gpio_config_mmc(void)
|
||||
static void pin_mux_mmc(void)
|
||||
{
|
||||
/* Not implemented for now */
|
||||
/* SDMMC4: config 3, x8 on 2nd set of pins */
|
||||
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
|
||||
|
||||
pinmux_tristate_disable(PINGRP_ATB);
|
||||
pinmux_tristate_disable(PINGRP_GMA);
|
||||
pinmux_tristate_disable(PINGRP_GME);
|
||||
|
||||
/* For power GPIO PI6 */
|
||||
pinmux_tristate_disable(PINGRP_ATA);
|
||||
/* For CD GPIO PH2 */
|
||||
pinmux_tristate_disable(PINGRP_ATD);
|
||||
|
||||
/* SDMMC2: SDIO2_CLK, SDIO2_CMD, SDIO2_DAT[7:0] */
|
||||
pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
|
||||
pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
|
||||
|
||||
pinmux_tristate_disable(PINGRP_DTA);
|
||||
pinmux_tristate_disable(PINGRP_DTD);
|
||||
|
||||
/* For power GPIO PT3 */
|
||||
pinmux_tristate_disable(PINGRP_DTB);
|
||||
/* For CD GPIO PI5 */
|
||||
pinmux_tristate_disable(PINGRP_ATC);
|
||||
}
|
||||
|
||||
/* this is a weak define that we are overriding */
|
||||
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
debug("board_mmc_getcd called\n");
|
||||
/*
|
||||
* Hard-code CD presence for now. Need to add GPIO inputs
|
||||
* for Harmony
|
||||
*/
|
||||
*cd = 1;
|
||||
debug("board_mmc_init called\n");
|
||||
|
||||
/* Enable muxes, etc. for SDMMC controllers */
|
||||
pin_mux_mmc();
|
||||
|
||||
debug("board_mmc_init: init SD slot J26\n");
|
||||
/* init dev 0, SD slot J26, with 4-bit bus */
|
||||
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
|
||||
tegra2_mmc_init(0, 4, GPIO_PI6, GPIO_PH2);
|
||||
|
||||
debug("board_mmc_init: init SD slot J5\n");
|
||||
/* init dev 2, SD slot J5, with 4-bit bus */
|
||||
tegra2_mmc_init(2, 4, GPIO_PT3, GPIO_PI5);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,61 +24,78 @@
|
|||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/tegra2.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/gpio.h>
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
#include <mmc.h>
|
||||
#endif
|
||||
#include "../common/board.h"
|
||||
|
||||
/*
|
||||
* Routine: gpio_config_uart
|
||||
* Routine: gpio_config_uart_seaboard
|
||||
* Description: Force GPIO_PI3 low on Seaboard so UART4 works.
|
||||
*/
|
||||
static void gpio_config_uart_seaboard(void)
|
||||
{
|
||||
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
|
||||
gpio_request(GPIO_PI3, NULL);
|
||||
gpio_direction_output(GPIO_PI3, 0);
|
||||
}
|
||||
|
||||
void gpio_config_uart(void)
|
||||
{
|
||||
int gp = GPIO_PI3;
|
||||
struct gpio_ctlr *gpio = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
|
||||
struct gpio_ctlr_bank *bank = &gpio->gpio_bank[GPIO_BANK(gp)];
|
||||
u32 val;
|
||||
|
||||
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
|
||||
val = readl(&bank->gpio_config[GPIO_PORT(gp)]);
|
||||
val |= 1 << GPIO_BIT(gp);
|
||||
writel(val, &bank->gpio_config[GPIO_PORT(gp)]);
|
||||
|
||||
val = readl(&bank->gpio_out[GPIO_PORT(gp)]);
|
||||
val &= ~(1 << GPIO_BIT(gp));
|
||||
writel(val, &bank->gpio_out[GPIO_PORT(gp)]);
|
||||
|
||||
val = readl(&bank->gpio_dir_out[GPIO_PORT(gp)]);
|
||||
val |= 1 << GPIO_BIT(gp);
|
||||
writel(val, &bank->gpio_dir_out[GPIO_PORT(gp)]);
|
||||
if (machine_is_ventana())
|
||||
return;
|
||||
gpio_config_uart_seaboard();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_TEGRA2_MMC
|
||||
/*
|
||||
* Routine: gpio_config_mmc
|
||||
* Description: Set GPIOs for SDMMC3 SDIO slot.
|
||||
* Routine: pin_mux_mmc
|
||||
* Description: setup the pin muxes/tristate values for the SDMMC(s)
|
||||
*/
|
||||
void gpio_config_mmc(void)
|
||||
static void pin_mux_mmc(void)
|
||||
{
|
||||
/* Set EN_VDDIO_SD (GPIO I6) */
|
||||
gpio_direction_output(GPIO_PI6, 1);
|
||||
/* SDMMC4: config 3, x8 on 2nd set of pins */
|
||||
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
|
||||
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
|
||||
|
||||
/* Config pin as GPI for Card Detect (GPIO I5) */
|
||||
gpio_direction_input(GPIO_PI5);
|
||||
pinmux_tristate_disable(PINGRP_ATB);
|
||||
pinmux_tristate_disable(PINGRP_GMA);
|
||||
pinmux_tristate_disable(PINGRP_GME);
|
||||
|
||||
/* SDMMC3: SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
|
||||
pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
|
||||
pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
|
||||
pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
|
||||
|
||||
pinmux_tristate_disable(PINGRP_SDC);
|
||||
pinmux_tristate_disable(PINGRP_SDD);
|
||||
pinmux_tristate_disable(PINGRP_SDB);
|
||||
|
||||
/* For power GPIO PI6 */
|
||||
pinmux_tristate_disable(PINGRP_ATA);
|
||||
/* For CD GPIO PI5 */
|
||||
pinmux_tristate_disable(PINGRP_ATC);
|
||||
}
|
||||
|
||||
/* this is a weak define that we are overriding */
|
||||
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
int board_mmc_init(bd_t *bd)
|
||||
{
|
||||
debug("board_mmc_getcd called\n");
|
||||
*cd = 1; /* Assume card is inserted, or eMMC */
|
||||
debug("board_mmc_init called\n");
|
||||
|
||||
if (IS_SD(mmc)) {
|
||||
/* Seaboard SDMMC3 = SDIO3_CD = GPIO_PI5 */
|
||||
if (gpio_get_value(GPIO_PI5))
|
||||
*cd = 0;
|
||||
}
|
||||
/* Enable muxes, etc. for SDMMC controllers */
|
||||
pin_mux_mmc();
|
||||
|
||||
debug("board_mmc_init: init eMMC\n");
|
||||
/* init dev 0, eMMC chip, with 4-bit bus */
|
||||
/* The board has an 8-bit bus, but 8-bit doesn't work yet */
|
||||
tegra2_mmc_init(0, 4, -1, -1);
|
||||
|
||||
debug("board_mmc_init: init SD slot\n");
|
||||
/* init dev 1, SD slot, with 4-bit bus */
|
||||
tegra2_mmc_init(1, 4, GPIO_PI6, GPIO_PI5);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2010,2011
|
||||
# NVIDIA Corporation <www.nvidia.com>
|
||||
#
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS += ../seaboard/seaboard.o
|
||||
COBJS += ../common/board.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Lowlevel setup for ORIGEN board based on S5PV310
|
||||
* Lowlevel setup for ORIGEN board based on EXYNOS4210
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
*
|
||||
|
|
@ -43,11 +43,11 @@ lowlevel_init:
|
|||
|
||||
/* r5 has always zero */
|
||||
mov r5, #0
|
||||
ldr r7, =S5PC210_GPIO_PART1_BASE
|
||||
ldr r6, =S5PC210_GPIO_PART2_BASE
|
||||
ldr r7, =EXYNOS4_GPIO_PART1_BASE
|
||||
ldr r6, =EXYNOS4_GPIO_PART2_BASE
|
||||
|
||||
/* check reset status */
|
||||
ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
|
||||
ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
|
||||
ldr r1, [r0]
|
||||
|
||||
/* AFTR wakeup reset */
|
||||
|
|
@ -97,9 +97,9 @@ wakeup_reset:
|
|||
|
||||
exit_wakeup:
|
||||
/* Load return address and jump to kernel */
|
||||
ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
|
||||
ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
|
||||
|
||||
/* r1 = physical address of s5pc210_cpu_resume function */
|
||||
/* r1 = physical address of exynos4210_cpu_resume function */
|
||||
ldr r1, [r0]
|
||||
|
||||
/* Jump to kernel*/
|
||||
|
|
@ -113,7 +113,7 @@ exit_wakeup:
|
|||
*/
|
||||
system_clock_init:
|
||||
push {lr}
|
||||
ldr r0, =S5PC210_CLOCK_BASE
|
||||
ldr r0, =EXYNOS4_CLOCK_BASE
|
||||
|
||||
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
|
||||
ldr r1, =CLK_SRC_CPU_VAL
|
||||
|
|
@ -290,13 +290,13 @@ uart_asm_init:
|
|||
|
||||
/* setup UART0-UART3 GPIOs (part1) */
|
||||
mov r0, r7
|
||||
ldr r1, =S5PC210_GPIO_A0_CON_VAL
|
||||
str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
|
||||
ldr r1, =S5PC210_GPIO_A1_CON_VAL
|
||||
str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
|
||||
ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
|
||||
str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
|
||||
ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
|
||||
str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
|
||||
|
||||
ldr r0, =S5PC210_UART_BASE
|
||||
add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
|
||||
ldr r0, =EXYNOS4_UART_BASE
|
||||
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
|
||||
|
||||
ldr r1, =ULCON_VAL
|
||||
str r1, [r0, #ULCON_OFFSET]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Memory setup for ORIGEN board based on S5PV310
|
||||
* Memory setup for ORIGEN board based on EXYNOS4210
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
*
|
||||
|
|
@ -38,7 +38,7 @@ mem_ctrl_asm_init:
|
|||
str r1, [r0]
|
||||
|
||||
#ifdef SET_MIU
|
||||
ldr r0, =S5PC210_MIU_BASE
|
||||
ldr r0, =EXYNOS4_MIU_BASE
|
||||
/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
|
||||
ldr r1, =0x20001507
|
||||
str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
|
||||
|
|
@ -48,7 +48,7 @@ mem_ctrl_asm_init:
|
|||
str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
|
||||
#endif
|
||||
/* DREX0 */
|
||||
ldr r0, =S5PC210_DMC0_BASE
|
||||
ldr r0, =EXYNOS4_DMC0_BASE
|
||||
|
||||
/*
|
||||
* DLL Parameter Setting:
|
||||
|
|
@ -229,7 +229,7 @@ mem_ctrl_asm_init:
|
|||
bne 8b
|
||||
|
||||
/* DREX1 */
|
||||
ldr r0, =S5PC210_DMC1_BASE @0x10410000
|
||||
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
|
||||
|
||||
/*
|
||||
* DLL Parameter Setting:
|
||||
|
|
@ -410,11 +410,11 @@ mem_ctrl_asm_init:
|
|||
bne 8b
|
||||
|
||||
/* turn on DREX0, DREX1 */
|
||||
ldr r0, =S5PC210_DMC0_BASE
|
||||
ldr r0, =EXYNOS4_DMC0_BASE
|
||||
ldr r1, =0x0FFF303a
|
||||
str r1, [r0, #DMC_CONCONTROL]
|
||||
|
||||
ldr r0, =S5PC210_DMC1_BASE
|
||||
ldr r0, =EXYNOS4_DMC1_BASE
|
||||
ldr r1, =0x0FFF303a
|
||||
str r1, [r0, #DMC_CONCONTROL]
|
||||
|
||||
|
|
|
|||
|
|
@ -27,13 +27,13 @@
|
|||
#include <asm/arch/mmc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
struct s5pc210_gpio_part1 *gpio1;
|
||||
struct s5pc210_gpio_part2 *gpio2;
|
||||
struct exynos4_gpio_part1 *gpio1;
|
||||
struct exynos4_gpio_part2 *gpio2;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
|
||||
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
|
||||
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
|
||||
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
|
||||
|
||||
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -98,8 +98,8 @@
|
|||
#define INFORM1_OFFSET 0x804
|
||||
|
||||
/* GPIO Offsets for UART: GPIO Contol Register */
|
||||
#define S5PC210_GPIO_A0_CON_OFFSET 0x00
|
||||
#define S5PC210_GPIO_A1_CON_OFFSET 0x20
|
||||
#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
|
||||
#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
|
||||
|
||||
/* UART Register offsets */
|
||||
#define ULCON_OFFSET 0x00
|
||||
|
|
@ -416,8 +416,8 @@
|
|||
* UART GPIO_A0/GPIO_A1 Control Register Value
|
||||
* 0x2: UART Function
|
||||
*/
|
||||
#define S5PC210_GPIO_A0_CON_VAL 0x22222222
|
||||
#define S5PC210_GPIO_A1_CON_VAL 0x222222
|
||||
#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
|
||||
#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
|
||||
|
||||
/* ULCON: UART Line Control Value 8N1 */
|
||||
#define WORD_LEN_5_BIT 0x00
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Lowlevel setup for SMDKV310 board based on S5PC210
|
||||
* Lowlevel setup for SMDKV310 board based on EXYNOS4210
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
*
|
||||
|
|
@ -45,11 +45,11 @@ lowlevel_init:
|
|||
|
||||
/* r5 has always zero */
|
||||
mov r5, #0
|
||||
ldr r7, =S5PC210_GPIO_PART1_BASE
|
||||
ldr r6, =S5PC210_GPIO_PART2_BASE
|
||||
ldr r7, =EXYNOS4_GPIO_PART1_BASE
|
||||
ldr r6, =EXYNOS4_GPIO_PART2_BASE
|
||||
|
||||
/* check reset status */
|
||||
ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
|
||||
ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
|
||||
ldr r1, [r0]
|
||||
|
||||
/* AFTR wakeup reset */
|
||||
|
|
@ -95,9 +95,9 @@ wakeup_reset:
|
|||
|
||||
exit_wakeup:
|
||||
/* Load return address and jump to kernel */
|
||||
ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
|
||||
ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
|
||||
|
||||
/* r1 = physical address of s5pc210_cpu_resume function */
|
||||
/* r1 = physical address of exynos4210_cpu_resume function */
|
||||
ldr r1, [r0]
|
||||
|
||||
/* Jump to kernel*/
|
||||
|
|
@ -111,7 +111,7 @@ exit_wakeup:
|
|||
*/
|
||||
system_clock_init:
|
||||
push {lr}
|
||||
ldr r0, =S5PC210_CLOCK_BASE
|
||||
ldr r0, =EXYNOS4_CLOCK_BASE
|
||||
|
||||
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
|
||||
ldr r1, =0x0101
|
||||
|
|
@ -388,12 +388,12 @@ uart_asm_init:
|
|||
/* setup UART0-UART3 GPIOs (part1) */
|
||||
mov r0, r7
|
||||
ldr r1, =0x22222222
|
||||
str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
|
||||
str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
|
||||
ldr r1, =0x00222222
|
||||
str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
|
||||
str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
|
||||
|
||||
ldr r0, =S5PC210_UART_BASE
|
||||
add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
|
||||
ldr r0, =EXYNOS4_UART_BASE
|
||||
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
|
||||
|
||||
ldr r1, =0x3C5
|
||||
str r1, [r0, #0x4]
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Memory setup for SMDKV310 board based on S5PC210
|
||||
* Memory setup for SMDKV310 board based on EXYNOS4210
|
||||
*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
*
|
||||
|
|
@ -54,7 +54,7 @@ mem_ctrl_asm_init:
|
|||
str r1, [r0]
|
||||
|
||||
#ifdef SET_MIU
|
||||
ldr r0, =S5PC210_MIU_BASE @0x10600000
|
||||
ldr r0, =EXYNOS4_MIU_BASE @0x10600000
|
||||
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
|
||||
ldr r1, =0x0000000c
|
||||
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
|
||||
|
|
@ -89,7 +89,7 @@ mem_ctrl_asm_init:
|
|||
#endif
|
||||
#endif
|
||||
/* DREX0 */
|
||||
ldr r0, =S5PC210_DMC0_BASE @0x10400000
|
||||
ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
|
||||
|
||||
ldr r1, =0xe0000086
|
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
|
@ -221,7 +221,7 @@ mem_ctrl_asm_init:
|
|||
bne 8b
|
||||
|
||||
/* DREX1 */
|
||||
ldr r0, =S5PC210_DMC1_BASE @0x10410000
|
||||
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
|
||||
|
||||
ldr r1, =0xe0000086
|
||||
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
|
||||
|
|
|
|||
|
|
@ -29,8 +29,8 @@
|
|||
#include <asm/arch/sromc.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
struct s5pc210_gpio_part1 *gpio1;
|
||||
struct s5pc210_gpio_part2 *gpio2;
|
||||
struct exynos4_gpio_part1 *gpio1;
|
||||
struct exynos4_gpio_part2 *gpio2;
|
||||
|
||||
static void smc9115_pre_init(void)
|
||||
{
|
||||
|
|
@ -52,8 +52,8 @@ static void smc9115_pre_init(void)
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
|
||||
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
|
||||
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
|
||||
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
|
||||
|
||||
smc9115_pre_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Lowlevel setup for universal board based on S5PC210
|
||||
* Lowlevel setup for universal board based on EXYNOS4210
|
||||
*
|
||||
* Copyright (C) 2010 Samsung Electronics
|
||||
* Kyungmin Park <kyungmin.park@samsung.com>
|
||||
|
|
@ -43,11 +43,11 @@ lowlevel_init:
|
|||
/* r5 has always zero */
|
||||
mov r5, #0
|
||||
|
||||
ldr r7, =S5PC210_GPIO_PART1_BASE
|
||||
ldr r6, =S5PC210_GPIO_PART2_BASE
|
||||
ldr r7, =EXYNOS4_GPIO_PART1_BASE
|
||||
ldr r6, =EXYNOS4_GPIO_PART2_BASE
|
||||
|
||||
/* System Timer */
|
||||
ldr r0, =S5PC210_SYSTIMER_BASE
|
||||
ldr r0, =EXYNOS4_SYSTIMER_BASE
|
||||
ldr r1, =0x5000
|
||||
str r1, [r0, #0x0]
|
||||
ldr r1, =0xffffffff
|
||||
|
|
@ -57,7 +57,7 @@ lowlevel_init:
|
|||
|
||||
/* PMIC manual reset */
|
||||
/* nPOWER: XEINT_23: GPX2[7] */
|
||||
add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
|
||||
add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
|
||||
ldr r1, [r0, #0x0]
|
||||
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
|
||||
orr r1, r1, #(0x1 << 28) @ Output
|
||||
|
|
@ -71,7 +71,7 @@ lowlevel_init:
|
|||
bl system_clock_init
|
||||
|
||||
/* Disable Watchdog */
|
||||
ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
|
||||
ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
|
||||
str r5, [r0]
|
||||
|
||||
/* UART */
|
||||
|
|
@ -99,12 +99,12 @@ uart_asm_init:
|
|||
*/
|
||||
mov r0, r7
|
||||
ldr r1, =0x22222222
|
||||
str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
|
||||
str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
|
||||
ldr r1, =0x00223322
|
||||
str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
|
||||
str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
|
||||
|
||||
/* UART_SEL GPY4[7] (part2) at S5PC210 */
|
||||
add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
|
||||
/* UART_SEL GPY4[7] (part2) at EXYNOS4 */
|
||||
add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
|
||||
ldr r1, [r0, #0x0]
|
||||
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
|
||||
orr r1, r1, #(0x1 << 28)
|
||||
|
|
@ -125,7 +125,7 @@ uart_asm_init:
|
|||
nop
|
||||
|
||||
system_clock_init:
|
||||
ldr r0, =S5PC210_CLOCK_BASE
|
||||
ldr r0, =EXYNOS4_CLOCK_BASE
|
||||
|
||||
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
|
||||
ldr r1, =0x0101
|
||||
|
|
@ -326,7 +326,7 @@ system_clock_init:
|
|||
nop
|
||||
|
||||
system_power_init:
|
||||
ldr r0, =S5PC210_POWER_BASE @ 0x10020000
|
||||
ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
|
||||
|
||||
ldr r2, =0x330C @ PS_HOLD_CONTROL
|
||||
ldr r1, [r0, r2]
|
||||
|
|
|
|||
|
|
@ -31,8 +31,8 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct s5pc210_gpio_part1 *gpio1;
|
||||
struct s5pc210_gpio_part2 *gpio2;
|
||||
struct exynos4_gpio_part1 *gpio1;
|
||||
struct exynos4_gpio_part2 *gpio2;
|
||||
unsigned int board_rev;
|
||||
|
||||
u32 get_board_rev(void)
|
||||
|
|
@ -49,8 +49,8 @@ static void check_hw_revision(void);
|
|||
|
||||
int board_init(void)
|
||||
{
|
||||
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
|
||||
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
|
||||
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
|
||||
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
|
||||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
|
|
|||
|
|
@ -180,6 +180,7 @@ mx53evk arm armv7 mx53evk freesca
|
|||
mx53loco arm armv7 mx53loco freescale mx5 mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
|
||||
mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
|
||||
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
|
||||
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
|
||||
cm_t35 arm armv7 cm_t35 - omap3
|
||||
omap3_overo arm armv7 overo - omap3
|
||||
omap3_pandora arm armv7 pandora - omap3
|
||||
|
|
@ -202,11 +203,12 @@ omap4_sdp4430 arm armv7 sdp4430 ti
|
|||
omap5_evm arm armv7 omap5_evm ti omap5
|
||||
s5p_goni arm armv7 goni samsung s5pc1xx
|
||||
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
|
||||
origen arm armv7 origen samsung s5pc2xx
|
||||
s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
|
||||
smdkv310 arm armv7 smdkv310 samsung s5pc2xx
|
||||
origen arm armv7 origen samsung exynos
|
||||
s5pc210_universal arm armv7 universal_c210 samsung exynos
|
||||
smdkv310 arm armv7 smdkv310 samsung exynos
|
||||
harmony arm armv7 harmony nvidia tegra2
|
||||
seaboard arm armv7 seaboard nvidia tegra2
|
||||
ventana arm armv7 ventana nvidia tegra2
|
||||
u8500_href arm armv7 u8500 st-ericsson u8500
|
||||
actux1_4_16 arm ixp actux1 - - actux1:FLASH2X2
|
||||
actux1_8_16 arm ixp actux1 - - actux1:FLASH1X8
|
||||
|
|
|
|||
|
|
@ -113,7 +113,8 @@ must have the following parameters:
|
|||
* Partition size ........ at least 1024 kb
|
||||
* Partition type ........ 0x53 (sometimes "OnTrack DM6 Aux3")
|
||||
|
||||
For example in Linux fdisk, the sequence for a clear card is the following:
|
||||
For example in Linux fdisk, the sequence for a clear card follows. Be sure to
|
||||
run fdisk with the option "-u=sectors" to set units to sectors:
|
||||
|
||||
* o ..................... create a clear partition table
|
||||
* n ..................... create new partition
|
||||
|
|
|
|||
|
|
@ -40,10 +40,10 @@ static unsigned long gpio_ports[] = {
|
|||
[0] = GPIO1_BASE_ADDR,
|
||||
[1] = GPIO2_BASE_ADDR,
|
||||
[2] = GPIO3_BASE_ADDR,
|
||||
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
|
||||
#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
|
||||
[3] = GPIO4_BASE_ADDR,
|
||||
#endif
|
||||
#if defined(CONFIG_MX53)
|
||||
#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
|
||||
[4] = GPIO5_BASE_ADDR,
|
||||
[5] = GPIO6_BASE_ADDR,
|
||||
[6] = GPIO7_BASE_ADDR,
|
||||
|
|
|
|||
|
|
@ -146,8 +146,10 @@ int gpio_request(int gp, const char *label)
|
|||
if (gp >= MAX_NUM_GPIOS)
|
||||
return -1;
|
||||
|
||||
strncpy(gpio_names[gp].name, label, GPIO_NAME_SIZE);
|
||||
gpio_names[gp].name[GPIO_NAME_SIZE - 1] = '\0';
|
||||
if (label != NULL) {
|
||||
strncpy(gpio_names[gp].name, label, GPIO_NAME_SIZE);
|
||||
gpio_names[gp].name[GPIO_NAME_SIZE - 1] = '\0';
|
||||
}
|
||||
|
||||
/* Configure as a GPIO */
|
||||
set_config(gp, 1);
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clk_rst.h>
|
||||
#include <asm/arch/clock.h>
|
||||
|
|
@ -473,20 +474,37 @@ static int mmc_core_init(struct mmc *mmc)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int tegra2_mmc_initialize(int dev_index, int bus_width)
|
||||
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
|
||||
{
|
||||
struct mmc_host *host;
|
||||
char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
|
||||
struct mmc *mmc;
|
||||
|
||||
debug(" mmc_initialize called\n");
|
||||
debug(" tegra2_mmc_init: index %d, bus width %d "
|
||||
"pwr_gpio %d cd_gpio %d\n",
|
||||
dev_index, bus_width, pwr_gpio, cd_gpio);
|
||||
|
||||
host = &mmc_host[dev_index];
|
||||
|
||||
host->clock = 0;
|
||||
host->pwr_gpio = pwr_gpio;
|
||||
host->cd_gpio = cd_gpio;
|
||||
tegra2_get_setup(host, dev_index);
|
||||
|
||||
clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
|
||||
|
||||
if (host->pwr_gpio >= 0) {
|
||||
sprintf(gpusage, "SD/MMC%d PWR", dev_index);
|
||||
gpio_request(host->pwr_gpio, gpusage);
|
||||
gpio_direction_output(host->pwr_gpio, 1);
|
||||
}
|
||||
|
||||
if (host->cd_gpio >= 0) {
|
||||
sprintf(gpusage, "SD/MMC%d CD", dev_index);
|
||||
gpio_request(host->cd_gpio, gpusage);
|
||||
gpio_direction_input(host->cd_gpio);
|
||||
}
|
||||
|
||||
mmc = &mmc_dev[dev_index];
|
||||
|
||||
sprintf(mmc->name, "Tegra2 SD/MMC");
|
||||
|
|
@ -518,9 +536,21 @@ static int tegra2_mmc_initialize(int dev_index, int bus_width)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int tegra2_mmc_init(int dev_index, int bus_width)
|
||||
/* this is a weak define that we are overriding */
|
||||
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
{
|
||||
debug(" tegra2_mmc_init: index %d, bus width %d\n",
|
||||
dev_index, bus_width);
|
||||
return tegra2_mmc_initialize(dev_index, bus_width);
|
||||
struct mmc_host *host = (struct mmc_host *)mmc->priv;
|
||||
|
||||
debug("board_mmc_getcd called\n");
|
||||
|
||||
*cd = 1; /* Assume card is inserted, or eMMC */
|
||||
|
||||
if (IS_SD(mmc)) {
|
||||
if (host->cd_gpio >= 0) {
|
||||
if (gpio_get_value(host->cd_gpio))
|
||||
*cd = 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -123,9 +123,11 @@ struct mmc_host {
|
|||
unsigned int clock; /* Current clock (MHz) */
|
||||
unsigned int base; /* Base address, SDMMC1/2/3/4 */
|
||||
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
|
||||
int pwr_gpio; /* Power GPIO */
|
||||
int cd_gpio; /* Change Detect GPIO */
|
||||
};
|
||||
|
||||
int tegra2_mmc_init(int dev_index, int bus_width);
|
||||
int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __TEGRA2_MMC_H_ */
|
||||
|
|
|
|||
|
|
@ -55,7 +55,6 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
|
|||
COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
|
||||
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
|
||||
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
|
||||
COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
COBJS-$(CONFIG_USB_TTY) += usbtty.o
|
||||
|
|
|
|||
|
|
@ -1,77 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/tegra2.h>
|
||||
#include "serial_tegra2.h"
|
||||
|
||||
static void setup_uart(struct uart_ctlr *u)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
/* Prepare the divisor value */
|
||||
reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
|
||||
|
||||
/* Set up UART parameters */
|
||||
writel(UART_LCR_DLAB, &u->uart_lcr);
|
||||
writel(reg, &u->uart_thr_dlab_0);
|
||||
writel(0, &u->uart_ier_dlab_0);
|
||||
writel(0, &u->uart_lcr); /* clear DLAB */
|
||||
writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
|
||||
UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
|
||||
writel(0, &u->uart_ier_dlab_0);
|
||||
writel(UART_LCR_WLS_8, &u->uart_lcr); /* 8N1 */
|
||||
writel(UART_MCR_RTS, &u->uart_mcr);
|
||||
writel(0, &u->uart_msr);
|
||||
writel(0, &u->uart_spr);
|
||||
writel(0, &u->uart_irda_csr);
|
||||
writel(0, &u->uart_asr);
|
||||
writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
|
||||
|
||||
/* Flush any old characters out of the RX FIFO */
|
||||
reg = readl(&u->uart_lsr);
|
||||
|
||||
while (reg & UART_LSR_DR) {
|
||||
reg = readl(&u->uart_thr_dlab_0);
|
||||
reg = readl(&u->uart_lsr);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Routine: uart_init
|
||||
* Description: init the UART clocks, muxes, and baudrate/parity/etc.
|
||||
*/
|
||||
void uart_init(void)
|
||||
{
|
||||
struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE;
|
||||
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
|
||||
setup_uart(uart);
|
||||
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
|
||||
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
|
||||
uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE;
|
||||
|
||||
setup_uart(uart);
|
||||
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
|
||||
}
|
||||
|
|
@ -48,8 +48,10 @@
|
|||
*/
|
||||
#define CONFIG_SPL
|
||||
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
|
||||
#define CONFIG_SPL_START_S_PATH "board/denx/m28evk"
|
||||
#define CONFIG_SPL_LDSCRIPT "board/denx/m28evk/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mx28"
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mx28/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||
|
||||
/*
|
||||
* U-Boot Commands
|
||||
|
|
|
|||
|
|
@ -0,0 +1,162 @@
|
|||
/*
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX6Q Armadillo2 board.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MX6Q
|
||||
#define CONFIG_SYS_MX6_HCLK 24000000
|
||||
#define CONFIG_SYS_MX6_CLK32 32768
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART4_BASE
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/* Command definition */
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#undef CONFIG_CMD_NET
|
||||
#undef CONFIG_CMD_NFS
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_LOADADDR 0x10800000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x17800000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console=ttymxc3\0" \
|
||||
"mmcdev=1\0" \
|
||||
"mmcpart=2\0" \
|
||||
"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"bootm\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"dhcp ${uimage}; bootm\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev};" \
|
||||
"if mmc rescan ${mmcdev}; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT "MX6QARM2 U-Boot > "
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x10000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10010000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_STACKSIZE (128 * 1024)
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (8 * 1024)
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
*
|
||||
* Configuration settings for the SAMSUNG ORIGEN (S5PV310) board.
|
||||
* Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
|
||||
#define CONFIG_S5P 1 /* S5P Family */
|
||||
#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */
|
||||
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
|
||||
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
|
|
@ -68,7 +68,7 @@
|
|||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define S5PC210_DEFAULT_UART_OFFSET 0x020000
|
||||
#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
|
||||
|
||||
/* SD/MMC configuration */
|
||||
#define CONFIG_GENERIC_MMC 1
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* Copyright (C) 2010 Samsung Electronics
|
||||
* Minkyu Kang <mk7.kang@samsung.com>
|
||||
*
|
||||
* Configuation settings for the SAMSUNG Universal (s5pc100) board.
|
||||
* Configuation settings for the SAMSUNG Universal (EXYNOS4210) board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -32,7 +32,7 @@
|
|||
*/
|
||||
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P 1 /* which is in a S5P Family */
|
||||
#define CONFIG_S5PC210 1 /* which is in a S5PC210 */
|
||||
#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
|
||||
#define CONFIG_UNIVERSAL 1 /* working with Universal */
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
|
|
@ -47,7 +47,7 @@
|
|||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x44800000
|
||||
|
||||
/* input clock of PLL: Universal has 24MHz input clock at S5PC210 */
|
||||
/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
|
||||
#define CONFIG_SYS_CLK_FREQ_C210 24000000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
|
|
@ -249,8 +249,8 @@
|
|||
/*
|
||||
* I2C Settings
|
||||
*/
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL s5pc210_gpio_part1_get_nr(b, 7)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA s5pc210_gpio_part1_get_nr(b, 6)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
|
||||
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
|
||||
|
||||
#define CONFIG_SOFT_I2C
|
||||
#define CONFIG_SOFT_I2C_READ_REPEATED_START
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics
|
||||
*
|
||||
* Configuration settings for the SAMSUNG SMDKV310 (S5PC210) board.
|
||||
* Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -28,7 +28,7 @@
|
|||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P 1 /* S5P Family */
|
||||
#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */
|
||||
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
|
||||
#define CONFIG_SMDKV310 1 /* working with SMDKV310*/
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
|
|
@ -65,7 +65,7 @@
|
|||
#define CONFIG_SERIAL_MULTI 1
|
||||
#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define S5PC210_DEFAULT_UART_OFFSET 0x010000
|
||||
#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
|
||||
|
||||
/* SD/MMC configuration */
|
||||
#define CONFIG_GENERIC_MMC 1
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@
|
|||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32
|
||||
|
||||
#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
|
||||
#define CONFIG_ARCH_CPU_INIT /* Fire up the A9 core */
|
||||
|
||||
#include <asm/arch/tegra2.h> /* get chip and board defs */
|
||||
|
||||
|
|
@ -45,7 +45,6 @@
|
|||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <asm/sizes.h>
|
||||
#include "tegra2-common.h"
|
||||
|
||||
/* High-level configuration options */
|
||||
#define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M"
|
||||
#define V_PROMPT "Tegra2 (Ventana) # "
|
||||
#define CONFIG_TEGRA2_BOARD_STRING "NVIDIA Ventana"
|
||||
|
||||
/* Board-specific serial config */
|
||||
#define CONFIG_SERIAL_MULTI
|
||||
#define CONFIG_TEGRA2_ENABLE_UARTD
|
||||
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA
|
||||
#define CONFIG_SYS_BOARD_ODMDATA 0x300d8011 /* lp1, 1GB */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* SD/MMC */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_TEGRA2_MMC
|
||||
#define CONFIG_CMD_MMC
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue