* Header file cleanup for ARM

* Patch by Murray Jensen, 24 Jun 2003:
  - make sure to use only U-boot provided header files
  - fix problems with ".rodata.str1.4" section as used by GCC-3.x
This commit is contained in:
wdenk 2003-06-25 22:26:29 +00:00
parent a300d83cb8
commit b783edaee8
112 changed files with 1472 additions and 299 deletions

View File

@ -2,6 +2,12 @@
Changes since U-Boot 0.3.1:
======================================================================
* Header file cleanup for ARM
* Patch by Murray Jensen, 24 Jun 2003:
- make sure to use only U-boot provided header files
- fix problems with ".rodata.str1.4" section as used by GCC-3.x
* Patch by Stefan Roese, 24 Jun 2003:
- Update esd ASH405 board files.
- Update esd DASA_SIM config file.

View File

@ -802,7 +802,7 @@ clobber: clean
rm -f u-boot u-boot.bin u-boot.srec u-boot.map System.map
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
rm -f tools/inca-swap-bytes cpu/mpc824x/bedbug_603e.c
rm -f include/asm/arch include/asm
rm -f include/asm/proc include/asm/arch include/asm
mrproper \
distclean: clobber unconfig

View File

@ -90,6 +90,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -75,6 +75,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -77,6 +77,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -77,6 +77,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -79,6 +79,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -61,6 +61,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -70,6 +70,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -88,6 +88,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -68,6 +68,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -70,6 +70,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -61,6 +61,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -88,6 +88,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -70,6 +70,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -93,6 +93,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -73,6 +73,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -73,6 +73,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -66,6 +66,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -62,6 +62,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -88,6 +88,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -74,6 +74,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -96,6 +96,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -98,6 +98,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -93,6 +93,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -100,6 +100,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -86,6 +86,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

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@ -78,6 +78,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -73,6 +73,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -79,6 +79,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -67,6 +67,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -66,6 +66,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -75,6 +75,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -78,6 +78,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -79,6 +79,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -79,6 +79,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -83,6 +83,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -92,6 +92,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -88,6 +88,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -70,6 +70,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -82,6 +82,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -66,6 +66,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -67,6 +67,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -61,6 +61,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -70,6 +70,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -61,6 +61,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -74,6 +74,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -77,6 +77,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -67,6 +67,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -60,6 +60,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -74,6 +74,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -61,6 +61,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -65,6 +65,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -79,6 +79,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -61,6 +61,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -79,6 +79,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -75,6 +75,7 @@ SECTIONS
. = ALIGN(16);
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -81,6 +81,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -70,6 +70,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -88,6 +88,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

View File

@ -76,6 +76,7 @@ SECTIONS
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }

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@ -107,10 +107,12 @@ LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds
endif
OBJCFLAGS += --gap-fill=0xff
gccincdir := $(shell $(CC) -print-file-name=include)
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
-D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \
-I$(TOPDIR)/include \
-fno-builtin \
-fno-builtin -nostdinc -isystem $(gccincdir) \
-pipe $(PLATFORM_CPPFLAGS)
ifdef BUILD_TAG

View File

@ -33,6 +33,7 @@
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
/* read co-processor 15, register #1 (control register) */
static unsigned long read_p15_c1(void)

View File

@ -32,7 +32,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/proc-armv/ptrace.h>
#include <asm/arch/hardware.h>
#include <asm/proc/ptrace.h>
extern void reset_cpu(ulong addr);

View File

@ -31,6 +31,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
/* ggi thunder */
AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU;

View File

@ -0,0 +1,162 @@
/*
* linux/include/asm-arm/arch-s3c2400/memory.h by gj@denx.de
* based on
* linux/include/asm-arm/arch-sa1100/memory.h
*
* Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com>
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Task size: 3GB
*/
#define TASK_SIZE (0xc0000000UL)
#define TASK_SIZE_26 (0x04000000UL)
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
/*
* Page offset: 3GB
*/
#define PAGE_OFFSET (0xc0000000UL)
/*
* Physical DRAM offset is 0x0c000000 on the S3C2400
*/
#define PHYS_OFFSET (0x0c000000UL)
#include <linux/config.h>
/* Modified for S3C2400, by chc, 20010509 */
#define RAM_IN_BANK_0 32*1024*1024
#define RAM_IN_BANK_1 0
#define RAM_IN_BANK_2 0
#define RAM_IN_BANK_3 0
#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3)
/* translation macros */
#define __virt_to_phys__is_a_macro
#define __phys_to_virt__is_a_macro
#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 )
#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET )
#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \
(RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0)
/* Two identical banks */
#define __virt_to_phys(x) \
( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \
((x) - PAGE_OFFSET + _DRAMBnk0) : \
((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) )
#define __phys_to_virt(x) \
( ((x)&0x07ffffff) + \
(((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) )
#else
/* It's more efficient for all other cases to use the function call */
#undef __virt_to_phys__is_a_macro
#undef __phys_to_virt__is_a_macro
extern unsigned long __virt_to_phys(unsigned long vpage);
extern unsigned long __phys_to_virt(unsigned long ppage);
#endif
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*
* On the SA1100, bus addresses are equivalent to physical addresses.
*/
#define __virt_to_bus__is_a_macro
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
#ifdef CONFIG_DISCONTIGMEM
#error "CONFIG_DISCONTIGMEM will not work on S3C2400"
/*
* Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much more convenient to use Linux's NUMA support to implement
* our memory map representation. Assuming all memory nodes have equal access
* characteristics, we then have generic discontiguous memory support.
*
* Of course, all this isn't mandatory for SA1100 implementations with only
* one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM.
*
* The nodes are matched with the physical memory bank addresses which are
* incidentally the same as virtual addresses.
*
* node 0: 0xc0000000 - 0xc7ffffff
* node 1: 0xc8000000 - 0xcfffffff
* node 2: 0xd0000000 - 0xd7ffffff
* node 3: 0xd8000000 - 0xdfffffff
*/
#define NR_NODES 4
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) \
(((unsigned long)(addr) - 0xc0000000) >> 27)
/*
* Given a physical address, convert it to a node id.
*/
#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr))
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and returns the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) \
NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(kvaddr) \
(((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT)
/*
* Given a kaddr, virt_to_page returns a pointer to the corresponding
* mem_map entry.
*/
#define virt_to_page(kaddr) \
(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
/*
* VALID_PAGE returns a non-zero value if given page pointer is valid.
* This assumes all node's mem_maps are stored within the node they refer to.
*/
#define VALID_PAGE(page) \
({ unsigned int node = KVADDR_TO_NID(page); \
( (node < NR_NODES) && \
((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \
})
#else
#define PHYS_TO_NID(addr) (0)
#endif
#endif /* __ASM_ARCH_MEMORY_H */

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/*
* FILE bitfield.h
*
* Version 1.1
* Author Copyright (c) Marc A. Viredaz, 1998
* DEC Western Research Laboratory, Palo Alto, CA
* Date April 1998 (April 1997)
* System Advanced RISC Machine (ARM)
* Language C or ARM Assembly
* Purpose Definition of macros to operate on bit fields.
*/
#ifndef __BITFIELD_H
#define __BITFIELD_H
#ifndef __ASSEMBLY__
#define UData(Data) ((unsigned long) (Data))
#else
#define UData(Data) (Data)
#endif
/*
* MACRO: Fld
*
* Purpose
* The macro "Fld" encodes a bit field, given its size and its shift value
* with respect to bit 0.
*
* Note
* A more intuitive way to encode bit fields would have been to use their
* mask. However, extracting size and shift value information from a bit
* field's mask is cumbersome and might break the assembler (255-character
* line-size limit).
*
* Input
* Size Size of the bit field, in number of bits.
* Shft Shift value of the bit field with respect to bit 0.
*
* Output
* Fld Encoded bit field.
*/
#define Fld(Size, Shft) (((Size) << 16) + (Shft))
/*
* MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
*
* Purpose
* The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
* the size, shift value, mask, aligned mask, and first bit of a
* bit field.
*
* Input
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FSize Size of the bit field, in number of bits.
* FShft Shift value of the bit field with respect to bit 0.
* FMsk Mask for the bit field.
* FAlnMsk Mask for the bit field, aligned on bit 0.
* F1stBit First bit of the bit field.
*/
#define FSize(Field) ((Field) >> 16)
#define FShft(Field) ((Field) & 0x0000FFFF)
#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
#define F1stBit(Field) (UData (1) << FShft (Field))
/*
* MACRO: FInsrt
*
* Purpose
* The macro "FInsrt" inserts a value into a bit field by shifting the
* former appropriately.
*
* Input
* Value Bit-field value.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FInsrt Bit-field value positioned appropriately.
*/
#define FInsrt(Value, Field) \
(UData (Value) << FShft (Field))
/*
* MACRO: FExtr
*
* Purpose
* The macro "FExtr" extracts the value of a bit field by masking and
* shifting it appropriately.
*
* Input
* Data Data containing the bit-field to be extracted.
* Field Encoded bit field (using the macro "Fld").
*
* Output
* FExtr Bit-field value.
*/
#define FExtr(Data, Field) \
((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
#endif /* __BITFIELD_H */

113
include/asm-arm/atomic.h Normal file
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/*
* linux/include/asm-arm/atomic.h
*
* Copyright (c) 1996 Russell King.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Changelog:
* 27-06-1996 RMK Created
* 13-04-1997 RMK Made functions atomic!
* 07-12-1997 RMK Upgraded for v2.1.
* 26-08-1998 PJB Added #ifdef __KERNEL__
*/
#ifndef __ASM_ARM_ATOMIC_H
#define __ASM_ARM_ATOMIC_H
#include <linux/config.h>
#ifdef CONFIG_SMP
#error SMP not supported
#endif
typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_INIT(i) { (i) }
#ifdef __KERNEL__
#include <asm/proc/system.h>
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) (((v)->counter) = (i))
static inline void atomic_add(int i, volatile atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
v->counter += i;
local_irq_restore(flags);
}
static inline void atomic_sub(int i, volatile atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
v->counter -= i;
local_irq_restore(flags);
}
static inline void atomic_inc(volatile atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
v->counter += 1;
local_irq_restore(flags);
}
static inline void atomic_dec(volatile atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
v->counter -= 1;
local_irq_restore(flags);
}
static inline int atomic_dec_and_test(volatile atomic_t *v)
{
unsigned long flags;
int val;
local_irq_save(flags);
val = v->counter;
v->counter = val -= 1;
local_irq_restore(flags);
return val == 0;
}
static inline int atomic_add_negative(int i, volatile atomic_t *v)
{
unsigned long flags;
int val;
local_irq_save(flags);
val = v->counter;
v->counter = val += i;
local_irq_restore(flags);
return val < 0;
}
static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
{
unsigned long flags;
local_irq_save(flags);
*addr &= ~mask;
local_irq_restore(flags);
}
/* Atomic operations are already serializing on ARM */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#endif
#endif

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/*
* linux/include/asm-arm/hardware.h
*
* Copyright (C) 1996 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Common hardware definitions
*/
#ifndef __ASM_HARDWARE_H
#define __ASM_HARDWARE_H
#include <asm/arch/hardware.h>
#endif

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