powerpc/mpc8548cds: Add 36-bit support
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
chenhui zhao
Kumar Gala
parent
fff80975ae
commit
b76aef60df
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@ -562,6 +562,7 @@ MPC8541CDS powerpc mpc85xx mpc8541cds freesca
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MPC8541CDS_legacy powerpc mpc85xx mpc8541cds freescale - MPC8541CDS:LEGACY
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MPC8544DS powerpc mpc85xx mpc8544ds freescale
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MPC8548CDS powerpc mpc85xx mpc8548cds freescale - MPC8548CDS
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MPC8548CDS_36BIT powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:36BIT
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MPC8548CDS_legacy powerpc mpc85xx mpc8548cds freescale - MPC8548CDS:LEGACY
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MPC8555CDS powerpc mpc85xx mpc8555cds freescale - MPC8555CDS
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MPC8555CDS_legacy powerpc mpc85xx mpc8555cds freescale - MPC8555CDS:LEGACY
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@ -29,6 +29,10 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_36BIT
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#define CONFIG_PHYS_64BIT
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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@ -74,6 +78,11 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_ADDR_MAP
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00400000
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@ -122,6 +131,19 @@ extern unsigned long get_clock_freq(void);
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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* 36bit:
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* 0x00000_0000 0x07fff_ffff DDR 2G cacheable
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* 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
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* 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
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* 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
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* 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
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* 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
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* 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
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* 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
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* 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
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* 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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*/
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@ -160,7 +182,11 @@ extern unsigned long get_clock_freq(void);
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*/
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#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
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#else
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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#endif
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#define CONFIG_SYS_BR0_PRELIM \
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(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
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@ -191,7 +217,11 @@ extern unsigned long get_clock_freq(void);
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* SDRAM on the Local Bus
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*/
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#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
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#else
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#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
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#endif
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#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
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/*
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@ -285,7 +315,11 @@ extern unsigned long get_clock_freq(void);
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#define CONFIG_FSL_CADMUS
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#define CADMUS_BASE_ADDR 0xf8000000
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#ifdef CONFIG_PHYS_64BIT
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#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
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#else
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#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
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#endif
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#define CONFIG_SYS_BR3_PRELIM \
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(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
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#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
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@ -347,23 +381,41 @@ extern unsigned long get_clock_freq(void);
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
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#else
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#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
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#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
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#endif
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
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#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
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#else
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#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
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#endif
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#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
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#ifdef CONFIG_PCIE1
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#define CONFIG_SYS_PCIE1_NAME "Slot"
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
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#else
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
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#endif
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
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#else
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
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#endif
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
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#endif
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@ -371,7 +423,11 @@ extern unsigned long get_clock_freq(void);
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* RapidIO MMU
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*/
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#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
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#else
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#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
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#endif
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#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
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#ifdef CONFIG_LEGACY
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