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ARM: OMAP5: DRA7xx: Add workaround for ARM errata 798870 

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Praveen Rao <prao@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Praveen Rao 2013-11-26 10:35:50 +05:30 committed by Tom Rini
parent c3a7f32060
commit a59443f753
4 changed files with 38 additions and 0 deletions
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1
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View File

@ -129,6 +129,7 @@ void s_init(void)
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
arm_errata_798870();
#endif
init_omap_revision();
hw_data_init();

13
arch/arm/cpu/armv7/omap-common/lowlevel_init.S
View File

@ -30,3 +30,16 @@ ENTRY(set_pl310_ctrl_reg)
@ call ROM Code API to set control register
POP {r4-r11, pc}
ENDPROC(set_pl310_ctrl_reg)
ENTRY(get_l2_aux_ctrl_reg)
MRC p15, 1, r0, c15, c0, 0
ENDPROC(get_l2_aux_ctrl_reg)
ENTRY(set_l2_aux_ctrl_reg)
PUSH {r4-r11, lr} @ save registers - ROM code may pollute
@ our registers
LDR r12, =0x104 @ Set L2 Cache Aux ctrl register - value in R0
.word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
@ call ROM Code API to set control register
POP {r4-r11, pc}
ENDPROC(set_l2_aux_ctrl_reg)

22
arch/arm/cpu/armv7/omap5/hwinit.c
View File

@ -381,3 +381,25 @@ void setup_warmreset_time(void)
rst_val |= rst_time;
writel(rst_val, (*prcm)->prm_rsttime);
}
void arm_errata_798870(void)
{
u32 val;
val = cortex_rev();
val = (val >> 4);
val &= 0xf;
/*
* L2ACTLR[7]: Enable hazard detect timeout for A15.
*/
if (val == 0xf) {
val = get_l2_aux_ctrl_reg();
/*
* Set L2ACTLR[7] to reissue any memory transaction in the L2
* that has been stalled for 1024 cycles to verify that its
* hazard condition still exists.
*/
val |= (1 << 7);
set_l2_aux_ctrl_reg(val);
}
}

2
arch/arm/include/asm/arch-omap5/sys_proto.h
View File

@ -56,6 +56,8 @@ void force_emif_self_refresh(void);
void get_ioregs(const struct ctrl_ioregs **regs);
void srcomp_enable(void);
void setup_warmreset_time(void);
u32 get_l2_aux_ctrl_reg(void);
void set_l2_aux_ctrl_reg(u32 val);
static inline u32 running_from_sdram(void)
{