rockchip: rk3188: Add core devicetree files
The rk3188 shares a lot of peripherals with the rk3066 and thus has a common include called rk3xxx.dtsi. Add both this one and the specialized rk3188 on top of it. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Heiko Stübner
Simon Glass
parent
dcdd32788a
commit
a57f2b86b7
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@ -0,0 +1,601 @@
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/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* SPDX-License-Identifier: GPL-2.0+ or X11
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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operating-points = <
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/* kHz uV */
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1608000 1350000
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1416000 1250000
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1200000 1150000
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1008000 1075000
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816000 975000
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600000 950000
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504000 925000
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312000 875000
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>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x3>;
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};
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x8000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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i2s0: i2s@1011a000 {
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compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
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reg = <0x1011a000 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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dmas = <&dmac1_s 6>, <&dmac1_s 7>;
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dma-names = "tx", "rx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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rockchip,playback-channels = <2>;
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rockchip,capture-channels = <2>;
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status = "disabled";
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};
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spdif: sound@1011e000 {
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compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
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reg = <0x1011e000 0x2000>;
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#sound-dai-cells = <0>;
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clock-names = "hclk", "mclk";
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clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
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dmas = <&dmac1_s 8>;
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dma-names = "tx";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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status = "disabled";
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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u-boot,dm-spl;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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efuse: efuse@20010000 {
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compatible = "rockchip,rockchip-efuse";
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reg = <0x20010000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru PCLK_EFUSE>;
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clock-names = "pclk_efuse";
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cpu_leakage: cpu_leakage@17 {
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reg = <0x17 0x1>;
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};
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};
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usbphy: phy {
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compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy@10c {
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#phy-cells = <0>;
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reg = <0x10c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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};
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usbphy1: usb-phy@11c {
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#phy-cells = <0>;
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reg = <0x11c>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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u-boot,dm-spl;
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gpio0: gpio0@2000a000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg_pull_up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg_pull_down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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emmc {
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emmc_clk: emmc-clk {
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rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
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};
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emmc_rst: emmc-rst {
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rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
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};
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/*
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* The data pins are shared between nandc and emmc and
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* not accessible through pinctrl. Also they should've
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* been already set correctly by firmware, as
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* flash/emmc is the boot-device.
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*/
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};
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emac {
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emac_xfer: emac-xfer {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
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<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
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<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
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<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
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<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
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<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
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<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
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<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
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};
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emac_mdio: emac-mdio {
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rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
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<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
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<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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i2c4 {
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i2c4_xfer: i2c4-xfer {
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rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_out: pwm0-out {
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rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_out: pwm1-out {
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rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm2 {
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pwm2_out: pwm2-out {
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rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm3 {
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pwm3_out: pwm3-out {
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rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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spi0 {
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spi0_clk: spi0-clk {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_cs0: spi0-cs0 {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_tx: spi0-tx {
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rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_rx: spi0-rx {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_cs1: spi0-cs1 {
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rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
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};
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};
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spi1 {
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spi1_clk: spi1-clk {
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rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_cs0: spi1-cs0 {
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rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_rx: spi1-rx {
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rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_tx: spi1-tx {
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rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_cs1: spi1-cs1 {
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rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
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};
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd0 {
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sd0_clk: sd0-clk {
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rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cmd: sd0-cmd {
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rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cd: sd0-cd {
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rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_wp: sd0-wp {
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rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_pwr: sd0-pwr {
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rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_bus1: sd0-bus-width1 {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_bus4: sd0-bus-width4 {
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rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd1 {
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sd1_clk: sd1-clk {
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rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_cmd: sd1-cmd {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_cd: sd1-cd {
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rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd1_wp: sd1-wp {
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rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_bus1: sd1-bus-width1 {
|
||||
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sd1_bus4: sd1-bus-width4 {
|
||||
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
i2s0_bus: i2s0-bus {
|
||||
rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
spdif {
|
||||
spdif_tx: spdif-tx {
|
||||
rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&emac {
|
||||
compatible = "rockchip,rk3188-emac";
|
||||
};
|
||||
|
||||
&global_timer {
|
||||
interrupts = <GIC_PPI 11 0xf04>;
|
||||
};
|
||||
|
||||
&grf {
|
||||
compatible = "rockchip,rk3188-grf", "syscon";
|
||||
};
|
||||
|
||||
&local_timer {
|
||||
interrupts = <GIC_PPI 13 0xf04>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_xfer>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_xfer>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_xfer>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_xfer>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
compatible = "rockchip,rk3188-i2c";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_xfer>;
|
||||
};
|
||||
|
||||
&pmu {
|
||||
compatible = "rockchip,rk3188-pmu", "syscon";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_out>;
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_out>;
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_out>;
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_out>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_xfer>;
|
||||
};
|
||||
|
||||
&wdt {
|
||||
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
|
||||
};
|
||||
|
|
@ -0,0 +1,417 @@
|
|||
/*
|
||||
* Copyright (c) 2013 MundoReader S.L.
|
||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+ or X11
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &emac;
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
mshc0 = &emmc;
|
||||
mshc1 = &mmc0;
|
||||
mshc2 = &mmc1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dmac1_s: dma-controller@20018000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x20018000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
clocks = <&cru ACLK_DMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
dmac1_ns: dma-controller@2001c000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x2001c000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
clocks = <&cru ACLK_DMA1>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmac2: dma-controller@20078000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x20078000 0x4000>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
arm,pl330-broken-no-flushp;
|
||||
clocks = <&cru ACLK_DMA2>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
xin24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "xin24m";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@10138000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x10138000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu@1013c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0x1013c000 0x100>;
|
||||
};
|
||||
|
||||
global_timer: global-timer@1013c200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x1013c200 0x20>;
|
||||
interrupts = <GIC_PPI 11 0x304>;
|
||||
clocks = <&cru CORE_PERI>;
|
||||
};
|
||||
|
||||
local_timer: local-timer@1013c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0x1013c600 0x20>;
|
||||
interrupts = <GIC_PPI 13 0x304>;
|
||||
clocks = <&cru CORE_PERI>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1013d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x1013d000 0x1000>,
|
||||
<0x1013c100 0x0100>;
|
||||
};
|
||||
|
||||
uart0: serial@10124000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10124000 0x400>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10126000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x10126000 0x400>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
noc: syscon@10128000 {
|
||||
u-boot,dm-spl;
|
||||
compatible = "rockchip,rk3188-noc", "syscon";
|
||||
reg = <0x10128000 0x2000>;
|
||||
};
|
||||
|
||||
usb_otg: usb@10180000 {
|
||||
compatible = "rockchip,rk3066-usb", "snps,dwc2";
|
||||
reg = <0x10180000 0x40000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG0>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "otg";
|
||||
g-np-tx-fifo-size = <16>;
|
||||
g-rx-fifo-size = <275>;
|
||||
g-tx-fifo-size = <256 128 128 64 64 32>;
|
||||
g-use-dma;
|
||||
phys = <&usbphy0>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_host: usb@101c0000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x101c0000 0x40000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_OTG1>;
|
||||
clock-names = "otg";
|
||||
dr_mode = "host";
|
||||
phys = <&usbphy1>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emac: ethernet@10204000 {
|
||||
compatible = "snps,arc-emac";
|
||||
reg = <0x10204000 0x3c>;
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
|
||||
clock-names = "hclk", "macref";
|
||||
max-speed = <100>;
|
||||
phy-mode = "rmii";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: dwmmc@10214000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x10214000 0x1000>;
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: dwmmc@10218000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x10218000 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: dwmmc@1021c000 {
|
||||
compatible = "rockchip,rk2928-dw-mshc";
|
||||
reg = <0x1021c000 0x1000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pmu: pmu@20004000 {
|
||||
compatible = "rockchip,rk3066-pmu", "syscon";
|
||||
reg = <0x20004000 0x100>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
grf: grf@20008000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x20008000 0x200>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
dmc: dmc@20020000 {
|
||||
/* unreviewed u-boot-specific binding */
|
||||
compatible = "rockchip,rk3188-dmc", "syscon";
|
||||
rockchip,cru = <&cru>;
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,pmu = <&pmu>;
|
||||
rockchip,noc = <&noc>;
|
||||
reg = <0x20020000 0x3fc
|
||||
0x20040000 0x294>;
|
||||
clocks = <&cru PCLK_DDRUPCTL>, <&cru PCLK_PUBL>;
|
||||
clock-names = "pclk_ddrupctl", "pclk_publ";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
i2c0: i2c@2002d000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2002d000 0x1000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clock-names = "i2c";
|
||||
clocks = <&cru PCLK_I2C0>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2002f000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2002f000 0x1000>;
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C1>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@20030000 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20030000 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@20030010 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20030010 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM01>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: watchdog@2004c000 {
|
||||
compatible = "snps,dw-wdt";
|
||||
reg = <0x2004c000 0x100>;
|
||||
clocks = <&cru PCLK_WDT>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@20050020 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050020 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@20050030 {
|
||||
compatible = "rockchip,rk2928-pwm";
|
||||
reg = <0x20050030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM23>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@20056000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x20056000 0x1000>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C2>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@2005a000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2005a000 0x1000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C3>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c4: i2c@2005e000 {
|
||||
compatible = "rockchip,rk3066-i2c";
|
||||
reg = <0x2005e000 0x1000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
clocks = <&cru PCLK_I2C4>;
|
||||
clock-names = "i2c";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@20064000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20064000 0x400>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@20068000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x20068000 0x400>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
saradc: saradc@2006c000 {
|
||||
compatible = "rockchip,saradc";
|
||||
reg = <0x2006c000 0x100>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#io-channel-cells = <1>;
|
||||
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
||||
clock-names = "saradc", "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@20070000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x20070000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&dmac2 10>, <&dmac2 11>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@20074000 {
|
||||
compatible = "rockchip,rk3066-spi";
|
||||
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
|
||||
clock-names = "spiclk", "apb_pclk";
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg = <0x20074000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&dmac2 12>, <&dmac2 13>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue