drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers and dividers capable of supplying clock to various controllers on or off-chip. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Purna Chandra Mandal
Daniel Schwierzeck
parent
32c1a6eef8
commit
a0e7908326
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@ -0,0 +1,33 @@
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* Microchip PIC32 Clock and Oscillator
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Microchip PIC32 clock tree consists of few oscillators, PLLs,
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multiplexers and few divider modules capable of supplying clocks
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to various controllers within SoC and also to off-chip.
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PIC32 clock controller output is defined by indices as defined
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in [0]
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[0] include/dt-bindings/clock/microchip,clock.h
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Required Properties:
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- compatible: should be "microchip,pic32mzda_clk"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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Example: Clock controller node:
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clock: clk@1f801200 {
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compatible = "microchip,pic32mzda-clk";
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reg = <0x1f801200 0x1000>;
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};
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Example: UART controller node that consumes the clock generated by the clock
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controller:
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uart1: serial@1f822000 {
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compatible = "microchip,pic32mzda-uart";
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reg = <0xbf822000 0x50>;
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interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clock PB2CLK>;
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};
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@ -9,3 +9,4 @@ obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o
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obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
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obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
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obj-$(CONFIG_SANDBOX) += clk_sandbox.o
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obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
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@ -0,0 +1,433 @@
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/*
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* Copyright (C) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <div64.h>
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#include <wait_bit.h>
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#include <dm/lists.h>
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#include <asm/io.h>
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#include <mach/pic32.h>
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#include <dt-bindings/clock/microchip,clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Primary oscillator */
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#define SYS_POSC_CLK_HZ 24000000
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/* FRC clk rate */
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#define SYS_FRC_CLK_HZ 8000000
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/* Clock Registers */
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#define OSCCON 0x0000
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#define OSCTUNE 0x0010
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#define SPLLCON 0x0020
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#define REFO1CON 0x0080
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#define REFO1TRIM 0x0090
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#define PB1DIV 0x0140
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/* SPLL */
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#define ICLK_MASK 0x00000080
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#define PLLIDIV_MASK 0x00000007
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#define PLLODIV_MASK 0x00000007
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#define CUROSC_MASK 0x00000007
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#define PLLMUL_MASK 0x0000007F
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#define FRCDIV_MASK 0x00000007
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/* PBCLK */
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#define PBDIV_MASK 0x00000007
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/* SYSCLK MUX */
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#define SCLK_SRC_FRC1 0
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#define SCLK_SRC_SPLL 1
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#define SCLK_SRC_POSC 2
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#define SCLK_SRC_FRC2 7
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/* Reference Oscillator Control Reg fields */
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#define REFO_SEL_MASK 0x0f
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#define REFO_SEL_SHIFT 0
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#define REFO_ACTIVE BIT(8)
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#define REFO_DIVSW_EN BIT(9)
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#define REFO_OE BIT(12)
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#define REFO_ON BIT(15)
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#define REFO_DIV_SHIFT 16
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#define REFO_DIV_MASK 0x7fff
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/* Reference Oscillator Trim Register Fields */
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#define REFO_TRIM_REG 0x10
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#define REFO_TRIM_MASK 0x1ff
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#define REFO_TRIM_SHIFT 23
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#define REFO_TRIM_MAX 511
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#define ROCLK_SRC_SCLK 0x0
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#define ROCLK_SRC_SPLL 0x7
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#define ROCLK_SRC_ROCLKI 0x8
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/* Memory PLL */
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#define MPLL_IDIV 0x3f
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#define MPLL_MULT 0xff
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#define MPLL_ODIV1 0x7
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#define MPLL_ODIV2 0x7
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#define MPLL_VREG_RDY BIT(23)
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#define MPLL_RDY BIT(31)
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#define MPLL_IDIV_SHIFT 0
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#define MPLL_MULT_SHIFT 8
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#define MPLL_ODIV1_SHIFT 24
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#define MPLL_ODIV2_SHIFT 27
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#define MPLL_IDIV_INIT 0x03
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#define MPLL_MULT_INIT 0x32
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#define MPLL_ODIV1_INIT 0x02
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#define MPLL_ODIV2_INIT 0x01
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struct pic32_clk_priv {
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void __iomem *iobase;
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void __iomem *syscfg_base;
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};
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static ulong pic32_get_pll_rate(struct pic32_clk_priv *priv)
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{
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u32 iclk, idiv, odiv, mult;
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ulong plliclk, v;
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v = readl(priv->iobase + SPLLCON);
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iclk = (v & ICLK_MASK);
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idiv = ((v >> 8) & PLLIDIV_MASK) + 1;
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odiv = ((v >> 24) & PLLODIV_MASK);
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mult = ((v >> 16) & PLLMUL_MASK) + 1;
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plliclk = iclk ? SYS_FRC_CLK_HZ : SYS_POSC_CLK_HZ;
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if (odiv < 2)
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odiv = 2;
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else if (odiv < 5)
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odiv = (1 << odiv);
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else
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odiv = 32;
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return ((plliclk / idiv) * mult) / odiv;
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}
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static ulong pic32_get_sysclk(struct pic32_clk_priv *priv)
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{
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ulong v;
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ulong hz;
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ulong div, frcdiv;
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ulong curr_osc;
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/* get clk source */
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v = readl(priv->iobase + OSCCON);
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curr_osc = (v >> 12) & CUROSC_MASK;
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switch (curr_osc) {
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case SCLK_SRC_FRC1:
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case SCLK_SRC_FRC2:
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frcdiv = ((v >> 24) & FRCDIV_MASK);
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div = ((1 << frcdiv) + 1) + (128 * (frcdiv == 7));
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hz = SYS_FRC_CLK_HZ / div;
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break;
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case SCLK_SRC_SPLL:
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hz = pic32_get_pll_rate(priv);
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break;
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case SCLK_SRC_POSC:
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hz = SYS_POSC_CLK_HZ;
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break;
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default:
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hz = 0;
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printf("clk: unknown sclk_src.\n");
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break;
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}
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return hz;
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}
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static ulong pic32_get_pbclk(struct pic32_clk_priv *priv, int periph)
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{
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void __iomem *reg;
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ulong div, clk_freq;
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WARN_ON((periph < PB1CLK) || (periph > PB7CLK));
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clk_freq = pic32_get_sysclk(priv);
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reg = priv->iobase + PB1DIV + (periph - PB1CLK) * 0x10;
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div = (readl(reg) & PBDIV_MASK) + 1;
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return clk_freq / div;
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}
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static ulong pic32_get_cpuclk(struct pic32_clk_priv *priv)
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{
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return pic32_get_pbclk(priv, PB7CLK);
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}
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static ulong pic32_set_refclk(struct pic32_clk_priv *priv, int periph,
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int parent_rate, int rate, int parent_id)
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{
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void __iomem *reg;
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u32 div, trim, v;
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u64 frac;
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WARN_ON((periph < REF1CLK) || (periph > REF5CLK));
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/* calculate dividers,
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* rate = parent_rate / [2 * (div + (trim / 512))]
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*/
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if (parent_rate <= rate) {
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div = 0;
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trim = 0;
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} else {
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div = parent_rate / (rate << 1);
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frac = parent_rate;
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frac <<= 8;
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do_div(frac, rate);
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frac -= (u64)(div << 9);
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trim = (frac >= REFO_TRIM_MAX) ? REFO_TRIM_MAX : (u32)frac;
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}
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reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
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/* disable clk */
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writel(REFO_ON | REFO_OE, reg + _CLR_OFFSET);
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/* wait till previous src change is active */
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wait_for_bit(__func__, reg, REFO_DIVSW_EN | REFO_ACTIVE,
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false, CONFIG_SYS_HZ, false);
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/* parent_id */
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v = readl(reg);
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v &= ~(REFO_SEL_MASK << REFO_SEL_SHIFT);
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v |= (parent_id << REFO_SEL_SHIFT);
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/* apply rodiv */
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v &= ~(REFO_DIV_MASK << REFO_DIV_SHIFT);
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v |= (div << REFO_DIV_SHIFT);
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writel(v, reg);
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/* apply trim */
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v = readl(reg + REFO_TRIM_REG);
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v &= ~(REFO_TRIM_MASK << REFO_TRIM_SHIFT);
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v |= (trim << REFO_TRIM_SHIFT);
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writel(v, reg + REFO_TRIM_REG);
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/* enable clk */
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writel(REFO_ON | REFO_OE, reg + _SET_OFFSET);
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/* switch divider */
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writel(REFO_DIVSW_EN, reg + _SET_OFFSET);
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/* wait for divider switching to complete */
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return wait_for_bit(__func__, reg, REFO_DIVSW_EN, false,
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CONFIG_SYS_HZ, false);
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}
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static ulong pic32_get_refclk(struct pic32_clk_priv *priv, int periph)
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{
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u32 rodiv, rotrim, rosel, v, parent_rate;
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void __iomem *reg;
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u64 rate64;
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WARN_ON((periph < REF1CLK) || (periph > REF5CLK));
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reg = priv->iobase + REFO1CON + (periph - REF1CLK) * 0x20;
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v = readl(reg);
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/* get rosel */
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rosel = (v >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
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/* get div */
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rodiv = (v >> REFO_DIV_SHIFT) & REFO_DIV_MASK;
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/* get trim */
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v = readl(reg + REFO_TRIM_REG);
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rotrim = (v >> REFO_TRIM_SHIFT) & REFO_TRIM_MASK;
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if (!rodiv)
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return 0;
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/* get parent rate */
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switch (rosel) {
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case ROCLK_SRC_SCLK:
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parent_rate = pic32_get_cpuclk(priv);
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break;
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case ROCLK_SRC_SPLL:
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parent_rate = pic32_get_pll_rate(priv);
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break;
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default:
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parent_rate = 0;
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break;
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}
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/* Calculation
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* rate = parent_rate / [2 * (div + (trim / 512))]
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*/
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if (rotrim) {
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rodiv <<= 9;
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rodiv += rotrim;
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rate64 = parent_rate;
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rate64 <<= 8;
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do_div(rate64, rodiv);
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v = (u32)rate64;
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} else {
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v = parent_rate / (rodiv << 1);
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}
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return v;
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}
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static ulong pic32_get_mpll_rate(struct pic32_clk_priv *priv)
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{
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u32 v, idiv, mul;
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u32 odiv1, odiv2;
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u64 rate;
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v = readl(priv->syscfg_base + CFGMPLL);
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idiv = v & MPLL_IDIV;
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mul = (v >> MPLL_MULT_SHIFT) & MPLL_MULT;
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odiv1 = (v >> MPLL_ODIV1_SHIFT) & MPLL_ODIV1;
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odiv2 = (v >> MPLL_ODIV2_SHIFT) & MPLL_ODIV2;
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rate = (SYS_POSC_CLK_HZ / idiv) * mul;
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do_div(rate, odiv1);
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do_div(rate, odiv2);
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return (ulong)rate;
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}
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static int pic32_mpll_init(struct pic32_clk_priv *priv)
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{
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u32 v, mask;
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/* initialize */
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v = (MPLL_IDIV_INIT << MPLL_IDIV_SHIFT) |
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(MPLL_MULT_INIT << MPLL_MULT_SHIFT) |
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(MPLL_ODIV1_INIT << MPLL_ODIV1_SHIFT) |
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(MPLL_ODIV2_INIT << MPLL_ODIV2_SHIFT);
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writel(v, priv->syscfg_base + CFGMPLL);
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/* Wait for ready */
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mask = MPLL_RDY | MPLL_VREG_RDY;
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return wait_for_bit(__func__, priv->syscfg_base + CFGMPLL, mask,
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true, get_tbclk(), false);
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}
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static void pic32_clk_init(struct udevice *dev)
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{
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const void *blob = gd->fdt_blob;
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struct pic32_clk_priv *priv;
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ulong rate, pll_hz;
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char propname[50];
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int i;
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priv = dev_get_priv(dev);
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pll_hz = pic32_get_pll_rate(priv);
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/* Initialize REFOs as not initialized and enabled on reset. */
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for (i = REF1CLK; i <= REF5CLK; i++) {
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snprintf(propname, sizeof(propname),
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"microchip,refo%d-frequency", i - REF1CLK + 1);
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rate = fdtdec_get_int(blob, dev->of_offset, propname, 0);
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if (rate)
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pic32_set_refclk(priv, i, pll_hz, rate, ROCLK_SRC_SPLL);
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}
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/* Memory PLL */
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pic32_mpll_init(priv);
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}
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static ulong pic32_clk_get_rate(struct udevice *dev)
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{
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struct pic32_clk_priv *priv = dev_get_priv(dev);
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return pic32_get_cpuclk(priv);
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}
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static ulong pic32_get_periph_rate(struct udevice *dev, int periph)
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{
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struct pic32_clk_priv *priv = dev_get_priv(dev);
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ulong rate;
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switch (periph) {
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case PB1CLK ... PB7CLK:
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rate = pic32_get_pbclk(priv, periph);
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break;
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case REF1CLK ... REF5CLK:
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rate = pic32_get_refclk(priv, periph);
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break;
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case PLLCLK:
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rate = pic32_get_pll_rate(priv);
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break;
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case MPLL:
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rate = pic32_get_mpll_rate(priv);
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break;
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default:
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rate = 0;
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break;
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}
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return rate;
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}
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static ulong pic32_set_periph_rate(struct udevice *dev, int periph, ulong rate)
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{
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struct pic32_clk_priv *priv = dev_get_priv(dev);
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ulong pll_hz;
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switch (periph) {
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case REF1CLK ... REF5CLK:
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pll_hz = pic32_get_pll_rate(priv);
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pic32_set_refclk(priv, periph, pll_hz, rate, ROCLK_SRC_SPLL);
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break;
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default:
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break;
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}
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return rate;
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}
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static struct clk_ops pic32_pic32_clk_ops = {
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.get_rate = pic32_clk_get_rate,
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.set_periph_rate = pic32_set_periph_rate,
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.get_periph_rate = pic32_get_periph_rate,
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};
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static int pic32_clk_probe(struct udevice *dev)
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{
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struct pic32_clk_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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fdt_size_t size;
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addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->iobase = ioremap(addr, size);
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if (!priv->iobase)
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return -EINVAL;
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priv->syscfg_base = pic32_get_syscfg_base();
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/* initialize clocks */
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pic32_clk_init(dev);
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return 0;
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}
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static const struct udevice_id pic32_clk_ids[] = {
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{ .compatible = "microchip,pic32mzda-clk"},
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{}
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};
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U_BOOT_DRIVER(pic32_clk) = {
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.name = "pic32_clk",
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.id = UCLASS_CLK,
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.of_match = pic32_clk_ids,
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.flags = DM_FLAG_PRE_RELOC,
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.ops = &pic32_pic32_clk_ops,
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.probe = pic32_clk_probe,
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||||
.priv_auto_alloc_size = sizeof(struct pic32_clk_priv),
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __CLK_MICROCHIP_PIC32
|
||||
#define __CLK_MICROCHIP_PIC32
|
||||
|
||||
/* clock output indices */
|
||||
#define BASECLK 0
|
||||
#define PLLCLK 1
|
||||
#define MPLL 2
|
||||
#define SYSCLK 3
|
||||
#define PB1CLK 4
|
||||
#define PB2CLK 5
|
||||
#define PB3CLK 6
|
||||
#define PB4CLK 7
|
||||
#define PB5CLK 8
|
||||
#define PB6CLK 9
|
||||
#define PB7CLK 10
|
||||
#define REF1CLK 11
|
||||
#define REF2CLK 12
|
||||
#define REF3CLK 13
|
||||
#define REF4CLK 14
|
||||
#define REF5CLK 15
|
||||
|
||||
#endif /* __CLK_MICROCHIP_PIC32 */
|
||||
Loading…
Reference in New Issue