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armv8: layerscape: Fix the sequence of changing MMU table 

This patch follows the break-before-make process when making changes
to MMU table. MMU is disabled before changing TTBR to avoid any
potential race condition.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2017-03-06 09:02:31 -08:00
parent 24f55496a4
commit a045a0c333
1 changed files with 4 additions and 11 deletions
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15
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
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@ -181,21 +181,14 @@ static inline void final_mmu_setup(void)
setup_pgtables();
gd->arch.tlb_addr = tlb_addr_save;
/* flush new MMU table */
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
/* Disable cache and MMU */
dcache_disable(); /* TLBs are invalidated */
invalidate_icache_all();
/* point TTBR to the new table */
set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
MEMORY_ATTRIBUTES);
/*
* EL3 MMU is already enabled, just need to invalidate TLB to load the
* new table. The new table is compatible with the current table, if
* MMU somehow walks through the new table before invalidation TLB,
* it still works. So we don't need to turn off MMU here.
* When EL2 MMU table is created by calling this function, MMU needs
* to be enabled.
*/
set_sctlr(get_sctlr() | CR_M);
}