ARM: ts4800: add basic board support
This commit adds basic support including: MMC, Serial console, TS4800 watchdog The config use CONFIG_SKIP_LOWLEVEL_INIT as U-boot is used as a second stage bootloader. Signed-off-by: Lucile Quirion <lucile.quirion@savoirfairelinux.com> signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Lucile Quirion
Stefano Babic
parent
0d8c32dd28
commit
9ee16897a2
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@ -667,6 +667,10 @@ config TARGET_SNOWBALL
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bool "Support snowball"
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select CPU_V7
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config TARGET_TS4800
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bool "Support TS4800"
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select CPU_V7
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config TARGET_U8500_HREF
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bool "Support u8500_href"
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select CPU_V7
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@ -991,6 +995,7 @@ source "board/timll/devkit3250/Kconfig"
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source "board/toradex/colibri_pxa270/Kconfig"
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source "board/toradex/colibri_vf/Kconfig"
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source "board/trizepsiv/Kconfig"
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source "board/technologic/ts4800/Kconfig"
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source "board/ttcontrol/vision2/Kconfig"
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source "board/udoo/Kconfig"
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source "board/vpac270/Kconfig"
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@ -0,0 +1,15 @@
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if TARGET_TS4800
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config SYS_BOARD
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default "ts4800"
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config SYS_VENDOR
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default "technologic"
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config SYS_SOC
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default "mx5"
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config SYS_CONFIG_NAME
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default "ts4800"
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endif
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@ -0,0 +1,6 @@
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TS4800 BOARD
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M: Lucile Quirion <lucile.quirion@savoirfairelinux.com>
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S: Maintained
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F: board/ts/ts4800/
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F: include/configs/ts4800.h
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F: configs/ts4800_defconfig
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@ -0,0 +1,7 @@
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#
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# (C) Copyright 2015 Savoir-faire Linux
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += ts4800.o
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@ -0,0 +1,154 @@
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/*
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* (C) Copyright 2015 Savoir-faire Linux Inc.
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*
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* Derived from MX51EVK code by
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* Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx51.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/imx-common/mx5_video.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <mc13892.h>
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#include "ts4800.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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u32 get_board_rev(void)
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{
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u32 rev = get_cpu_rev();
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if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
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rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
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return rev;
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}
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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MX51_PAD_UART1_RXD__UART1_RXD,
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MX51_PAD_UART1_TXD__UART1_TXD,
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NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 0));
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 6));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
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};
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
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return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int checkboard(void)
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{
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puts("Board: TS4800\n");
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return 0;
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}
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void hw_watchdog_reset(void)
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{
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struct ts4800_wtd_regs *wtd = (struct ts4800_wtd_regs *) (TS4800_SYSCON_BASE + 0xE);
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/* feed the watchdog for another 10s */
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writew(0x2, &wtd->feed);
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}
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void hw_watchdog_init(void)
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{
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return;
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}
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@ -0,0 +1,16 @@
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/*
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* (C) Copyright 2015 Savoir-faire Linux Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TS4800_H
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#define _TS4800_H
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#define TS4800_SYSCON_BASE 0xb0010000
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struct ts4800_wtd_regs {
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u16 feed;
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};
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#endif
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@ -0,0 +1,4 @@
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CONFIG_ARM=y
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CONFIG_TARGET_TS4800=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_SETEXPR is not set
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@ -0,0 +1,169 @@
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/*
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* Copyright (C) 2015, Savoir-faire Linux Inc.
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*
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* Derived from MX51EVK code by
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* Guennadi Liakhovetski <lg@denx.de>
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* Freescale Semiconductor, Inc.
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*
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* Configuration settings for the TS4800 Board
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_MX51
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_NO_FLASH /* No NOR Flash */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* U-boot is a 2nd stage bootloader */
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX
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/* text base address used when linking */
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#define CONFIG_SYS_TEXT_BASE 0x90008000
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#include <asm/arch/imx-regs.h>
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/* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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/* use common/board_f.c instead of arch/<arch>/lib/<board>.c */
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
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/*
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* Hardware drivers
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*/
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART1_BASE
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#define CONFIG_MXC_GPIO
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/*
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* SPI Configs
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* */
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#define CONFIG_HARD_SPI /* puts SPI: ready */
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#define CONFIG_MXC_SPI /* driver for the SPI controllers*/
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#define CONFIG_CMD_SPI /* SPI serial bus support */
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/*
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* MMC Configs
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* */
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#define CONFIG_FSL_ESDHC
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#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */
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#define CONFIG_CONS_INDEX 1 /* use UART0 : used by serial driver */
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#define CONFIG_BAUDRATE 115200
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/***********************************************************
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* Command definition
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***********************************************************/
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#define CONFIG_CMD_BOOTZ
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#undef CONFIG_CMD_IMLS
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/* Environment variables */
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=uImage\0" \
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"mmcdev=0\0" \
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"mmcpart=1\0" \
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"mmcargs=setenv bootargs root=/dev/mmcblk0p2 rootwait rw\0" \
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"addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs addtty; " \
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"bootm; "
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"fi; " \
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"fi; " \
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"fi; "
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_CMDLINE_EDITING
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
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#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
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#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* Low level init */
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#define CONFIG_SYS_DDR_CLKSEL 0
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#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
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#define CONFIG_SYS_MAIN_PWR_ON
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/*-----------------------------------------------------------------------
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* Environment organization
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*/
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#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
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#define CONFIG_ENV_SIZE (8 * 1024)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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