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fsl_esdhc: Fix DMA transfer completion waiting loop 

Rework the waiting for transfer completion loop condition
to continue waiting until both Transfer Complete and DMA End
interrupts occur. Checking of DLA bit in Present State register
looks not needed in addition to interrupts status checking,
so it can be removed from the condition. Also, DMA Error
condition is added to the list of data errors, checked in the loop.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
This commit is contained in:
Andrew Gabbasov 2013-04-07 23:06:08 +00:00 committed by Stefano Babic
parent 54899fc8fe
commit 9b74dc56fb
2 changed files with 4 additions and 3 deletions
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3
drivers/mmc/fsl_esdhc.c
View File

@ -397,8 +397,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
if (irqstat & DATA_ERR)
return COMM_ERR;
} while (!(irqstat & IRQSTAT_TC) &&
(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
} while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
#endif
if (data->flags & MMC_DATA_READ)
check_and_invalidate_dcache_range(cmd, data);

4
include/fsl_esdhc.h
View File

@ -63,7 +63,9 @@
#define IRQSTAT_CC (0x00000001)
#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
IRQSTAT_DMAE)
#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
#define IRQSTATEN 0x0002e034
#define IRQSTATEN_DMAE (0x10000000)