ARM: DRA7xx: clocks: Update PLL values
Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sricharan R <r.sricharan@ti.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
7f36c88f64
commit
97405d843e
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@ -50,13 +50,12 @@
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const u32 sys_clk_array[8] = {
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12000000, /* 12 MHz */
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13000000, /* 13 MHz */
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20000000, /* 20 MHz */
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16800000, /* 16.8 MHz */
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19200000, /* 19.2 MHz */
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26000000, /* 26 MHz */
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27000000, /* 27 MHz */
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38400000, /* 38.4 MHz */
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20000000, /* 20 MHz */
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};
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static inline u32 __get_sys_clk_index(void)
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@ -75,13 +74,6 @@ static inline u32 __get_sys_clk_index(void)
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/* SYS_CLKSEL - 1 to match the dpll param array indices */
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ind = (readl((*prcm)->cm_sys_clksel) &
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CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
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/*
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* SYS_CLKSEL value for 20MHz is 0. This is introduced newly
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* in DRA7XX socs. SYS_CLKSEL -1 will be greater than
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* NUM_SYS_CLK. So considering the last 3 bits as the index
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* for the dpll param array.
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*/
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ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
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}
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return ind;
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}
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@ -441,6 +433,12 @@ static void setup_non_essential_dplls(void)
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params = get_abe_dpll_params(*dplls_data);
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#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
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if (omap_revision() == DRA752_ES1_0)
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/* Select the sys clk for dpll_abe */
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clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
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CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
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CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
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#else
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abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
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/*
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@ -100,14 +100,13 @@ static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
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};
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static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
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{250, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{119, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{500, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{625, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
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{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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static const struct dpll_params
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@ -133,15 +132,14 @@ static const struct dpll_params
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};
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static const struct dpll_params
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core_dpll_params_2128mhz_ddr532_dra7xx[NUM_SYS_CLKS] = {
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{266, 2, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{443, 6, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 16.8 MHz */
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{277, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 19.2 MHz */
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{368, 8, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 26 MHz */
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core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
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{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
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{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
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{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
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{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
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{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{277, 9, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6}, /* 38.4 MHz */
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{266, 4, 2, -1, -1, 4, 62, 5, -1, 5, 7, 6} /* 20 MHz */
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{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
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};
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static const struct dpll_params
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@ -187,14 +185,13 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
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};
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static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
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{32, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{160, 6, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
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{20, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
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{192, 12, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
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{32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
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{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */
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{160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
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{20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
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{192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{10, 0, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
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{96, 4, 4, -1, 3, 4, 10, 2, -1, -1, -1, -1} /* 20 MHz */
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{10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
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@ -207,6 +204,16 @@ static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
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{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
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};
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static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
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{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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/* ABE M & N values with sys_clk as source */
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static const struct dpll_params
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abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
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@ -224,26 +231,36 @@ static const struct dpll_params abe_dpll_params_32k_196608khz = {
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750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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/* ABE M & N values with sysclk2(22.5792 MHz) as input */
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static const struct dpll_params
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abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
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{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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{48, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
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};
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static const struct dpll_params ddr_dpll_params_1066mhz[NUM_SYS_CLKS] = {
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{533, 11, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
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{222, 6, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{111, 3, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{41, 1, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
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{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
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{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
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{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
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{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
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{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
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{347, 24, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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{533, 19, 1, 1, 4, -1, -1, -1, -1, -1, -1, -1} /* 20 MHz */
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{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
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};
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struct dplls omap5_dplls_es1 = {
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@ -276,10 +293,12 @@ struct dplls omap5_dplls_es2 = {
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struct dplls dra7xx_dplls = {
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.mpu = mpu_dpll_params_1ghz,
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.core = core_dpll_params_2128mhz_ddr532_dra7xx,
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.core = core_dpll_params_2128mhz_dra7xx,
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.per = per_dpll_params_768mhz_dra7xx,
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.abe = abe_dpll_params_sysclk2_361267khz,
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.iva = iva_dpll_params_2330mhz_dra7xx,
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.usb = usb_dpll_params_1920mhz,
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.ddr = ddr_dpll_params_1066mhz,
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.ddr = ddr_dpll_params_2128mhz,
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};
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struct pmic_data palmas = {
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@ -951,6 +951,7 @@ struct prcm_regs const dra7xx_prcm = {
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/* l4 wkup regs */
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.cm_abe_pll_ref_clksel = 0x4ae0610c,
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.cm_sys_clksel = 0x4ae06110,
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.cm_abe_pll_sys_clksel = 0x4ae06118,
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.cm_wkup_clkstctrl = 0x4ae07800,
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.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
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.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
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@ -76,7 +76,7 @@
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#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
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/* CM_SYS_CLKSEL */
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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/* CM_CLKSEL_CORE */
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#define CLKSEL_CORE_SHIFT 0
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@ -81,7 +81,7 @@
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#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
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/* CM_SYS_CLKSEL */
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
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/* CM_CLKSEL_CORE */
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#define CLKSEL_CORE_SHIFT 0
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@ -98,6 +98,12 @@
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
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#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
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/* CM_CLKSEL_ABE_PLL_SYS */
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#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
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#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
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#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
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#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
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/* CM_BYPCLK_DPLL_IVA */
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#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
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#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
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@ -29,7 +29,7 @@
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#include <common.h>
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#define NUM_SYS_CLKS 8
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#define NUM_SYS_CLKS 7
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struct prcm_regs {
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/* cm1.ckgen */
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@ -303,6 +303,7 @@ struct prcm_regs {
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/* l4 wkup regs */
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u32 cm_abe_pll_ref_clksel;
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u32 cm_sys_clksel;
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u32 cm_abe_pll_sys_clksel;
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u32 cm_wkup_clkstctrl;
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u32 cm_wkup_l4wkup_clkctrl;
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u32 cm_wkup_wdtimer1_clkctrl;
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@ -39,4 +39,6 @@
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 UART1_BASE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_OMAP_ABE_SYSCK
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#endif /* __CONFIG_DRA7XX_EVM_H */
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