add support for skylab
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@ -276,6 +276,11 @@ carambola2_config: unconfig hornet_common_config
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@echo "#define CARABOOT_RELEASE \"$(CARABOOT_RELEASE)\"" >>include/config.h
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@./mkconfig -a carambola2 mips mips carambola2 ar7240 ar7240
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skylab_config: unconfig hornet_common_config
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@echo "#define FLASH_SIZE $(FLASH_SIZE)" >>include/config.h
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@echo "#define CARABOOT_RELEASE \"$(CARABOOT_RELEASE)\"" >>include/config.h
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@./mkconfig -a skylab mips mips carambola2 ar7240 ar7240
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hornet_common_config :
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@ >include/config.h
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@ -0,0 +1,294 @@
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/*
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* This file contains the configuration parameters for the dbau1x00 board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/ar7240.h>
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#include <config.h>
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*-----------------------------------------------------------------------
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*/
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 128
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#define CFG_FLASH_SECTOR_SIZE (64*1024)
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#define CFG_FLASH_SIZE 0x00800000
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#if (CFG_MAX_FLASH_SECT * CFG_FLASH_SECTOR_SIZE) != CFG_FLASH_SIZE
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# error "Invalid flash configuration"
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#endif
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#define CFG_FLASH_WORD_SIZE unsigned short
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/*
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* We boot from this flash
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*/
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#define CFG_FLASH_BASE 0x9f000000
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#ifdef COMPRESSED_UBOOT
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#define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
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#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
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#endif
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/*
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* The following #defines are needed to get flash environment right
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*/
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 << 10)
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#undef CONFIG_BOOTARGS
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/* XXX - putting rootfs in last partition results in jffs errors */
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/* default mtd partition table */
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#undef MTDPARTS_DEFAULT
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#define CONFIG_BOOTARGS ""
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#define MTDPARTS_DEFAULT ""
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#undef CFG_PLL_FREQ
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#define CFG_PLL_FREQ CFG_PLL_400_400_200
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#undef CFG_HZ
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/*
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* MIPS32 24K Processor Core Family Software User's Manual
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*
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* 6.2.9 Count Register (CP0 Register 9, Select 0)
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* The Count register acts as a timer, incrementing at a constant
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* rate, whether or not an instruction is executed, retired, or
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* any forward progress is made through the pipeline. The counter
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* increments every other clock, if the DC bit in the Cause register
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* is 0.
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*/
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/* Since the count is incremented every other tick, divide by 2 */
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/* XXX derive this from CFG_PLL_FREQ */
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#define CPU_PLL_DITHER_FRAC_VAL 0x001003e8
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#define CPU_CLK_CONTROL_VAL2 0x00008000
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#if (CFG_PLL_FREQ == CFG_PLL_200_200_100)
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# define CFG_HZ (200000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_300_300_150)
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# define CFG_HZ (300000000/2)
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CPU_PLL_CONFIG_VAL1 0x40813C00
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#define CPU_PLL_CONFIG_VAL2 0x00813C00
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#else
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#define CPU_PLL_CONFIG_VAL1 0x40816000
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#define CPU_PLL_CONFIG_VAL2 0x00816000
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#endif
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#elif (CFG_PLL_FREQ == CFG_PLL_350_350_175)
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# define CFG_HZ (350000000/2)
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#undef CPU_PLL_DITHER_FRAC_VAL
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#define CPU_PLL_DITHER_FRAC_VAL 0x001803E8
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#define CPU_PLL_CONFIG_VAL1 0x40814600
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#define CPU_PLL_CONFIG_VAL2 0x00814600
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#else
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#define CPU_PLL_CONFIG_VAL1 0x40817000
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#define CPU_PLL_CONFIG_VAL2 0x00817000
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#endif
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#elif (CFG_PLL_FREQ == CFG_PLL_333_333_166)
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# define CFG_HZ (333000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_266_266_133)
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# define CFG_HZ (266000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_266_266_66)
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# define CFG_HZ (266000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_400_400_200) || (CFG_PLL_FREQ == CFG_PLL_400_400_100)
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# define CFG_HZ (400000000/2)
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CPU_PLL_CONFIG_VAL1 0x40815000
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#define CPU_PLL_CONFIG_VAL2 0x00815000
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#else
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#define CPU_PLL_CONFIG_VAL1 0x40818000
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#define CPU_PLL_CONFIG_VAL2 0x00818000
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#endif
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#elif (CFG_PLL_FREQ == CFG_PLL_320_320_80) || (CFG_PLL_FREQ == CFG_PLL_320_320_160)
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# define CFG_HZ (320000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_410_400_200)
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# define CFG_HZ (410000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_420_400_200)
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# define CFG_HZ (420000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_362_362_181)
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# define CFG_HZ (326500000/2)
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#define CPU_PLL_CONFIG_VAL1 0x40817400
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#define CPU_PLL_CONFIG_VAL2 0x00817400
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#elif (CFG_PLL_FREQ == CFG_PLL_80_80_40)
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# define CFG_HZ (80000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_64_64_32)
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# define CFG_HZ (64000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_48_48_24)
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# define CFG_HZ (48000000/2)
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#elif (CFG_PLL_FREQ == CFG_PLL_32_32_16)
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# define CFG_HZ (32000000/2)
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#endif
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CPU_PLL_SETTLE_TIME_VAL 0x00000550
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#else
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#define CPU_PLL_SETTLE_TIME_VAL 0x00000352
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#endif
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/*
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* timeout values are in ticks
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*/
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#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
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#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
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/*
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* Cache lock for stack
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*/
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#define CFG_INIT_SP_OFFSET 0x1000
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#ifndef COMPRESSED_UBOOT
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#define CFG_ENV_IS_IN_FLASH 1
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#undef CFG_ENV_IS_NOWHERE
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#else
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#undef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_IS_NOWHERE 1
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#endif /* #ifndef COMPRESSED_UBOOT */
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/* Address and size of Primary Environment Sector */
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#define CFG_ENV_ADDR 0x9f040000
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#define CFG_ENV_SIZE 0x10000
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#define CONFIG_BOOTCOMMAND "bootm 0x9f050000"
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/* DDR init values */
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#define CONFIG_NR_DRAM_BANKS 2
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#if CONFIG_40MHZ_XTAL_SUPPORT
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#define CFG_DDR_REFRESH_VAL 0x4270
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#else
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#define CFG_DDR_REFRESH_VAL 0x4186
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#endif
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#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0
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#define CFG_DDR_MODE_VAL_INIT 0x133
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#ifdef LOW_DRIVE_STRENGTH
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# define CFG_DDR_EXT_MODE_VAL 0x2
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#else
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# define CFG_DDR_EXT_MODE_VAL 0x0
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#endif
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#define CFG_DDR_MODE_VAL 0x33
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#define CFG_DDR_TRTW_VAL 0x1f
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#define CFG_DDR_TWTR_VAL 0x1e
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//#define CFG_DDR_CONFIG2_VAL 0x99d0e6a8 // HORNET 1.0
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#define CFG_DDR_CONFIG2_VAL 0x9dd0e6a8 // HORNET 1.1
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#define CFG_DDR_RD_DATA_THIS_CYCLE_VAL 0x00ff
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#define CFG_DDR_TAP0_VAL 0x8
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#define CFG_DDR_TAP1_VAL 0x9
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/* DDR2 Init values */
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#define CFG_DDR2_EXT_MODE_VAL 0x402
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#define CONFIG_NET_MULTI
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#define CONFIG_MEMSIZE_IN_BYTES
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#ifdef COMPRESSED_UBOOT
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#define ATH_NO_PCI_INIT
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#ifndef COMPRESSED_UBOOT
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#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_PCI | \
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CFG_CMD_MII | CFG_CMD_PING | CFG_CMD_NET | CFG_CMD_ENV | CFG_CMD_USB | \
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CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | CFG_CMD_ETHREG | CFG_CMD_FAT ))
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#elif defined(VXWORKS_UBOOT)
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#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET | CFG_CMD_MII | CFG_CMD_ELF))
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#else
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#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET | CFG_CMD_MII))
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#endif /* #ifndef COMPRESSED_UBOOT */
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#define CFG_ATHRS26_PHY 1
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#define CONFIG_IPADDR 192.168.2.100
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#define CONFIG_SERVERIP 192.168.2.254
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#define CONFIG_ETHADDR 0x00:0xaa:0xbb:0xcc:0xdd:0xee
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#define CFG_FAULT_ECHO_LINK_DOWN 1
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#define CFG_PHY_ADDR 0
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#define CFG_AG7240_NMACS 2
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#define CFG_GMII 0
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#define CFG_MII0_RMII 1
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#define CFG_AG7100_GE0_RMII 1
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#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
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#undef DEBUG
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#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup*/
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#define CONFIG_SHOW_BOOT_PROGRESS /* use LEDs to show boot status*/
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#define CONFIG_SHOW_ACTIVITY
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "hush>"
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#define CONFIG_CARAMBOLA_FACTORY_MODE
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#define CFG_C2_IMG_LOAD_ADDR "0x80F00000"
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#define CFG_C2_IMG_FILENAME "carambola2.bin"
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_STORAGE
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#define ARCH_DMA_MINALIGN 4*1024 // 4kb in datasheet
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_EHCI_DESC_BIG_ENDIAN
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#define CONFIG_EHCI_IS_TDI
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#define HAVE_BLOCK_DEVICE
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#define CONFIG_PARTITIONS
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#define CONFIG_DOS_PARTITION
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#define CONFIG_FS_FAT
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#define CONFIG_SUPPORT_VFAT
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#define CONFIG_SYS_LOAD_ADDR 0x82000000
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#define CONFIG_CMD_USB
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#define CONFIG_NEEDS_MANUAL_RELOC
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#define CONFIG_USB_BOOT
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#define CFG_USB_BOOT_MAX_PARTITIONS_SCAN 16
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#define CFG_USB_BOOT_LOAD_ADDR 0x82000000 /* starts at upper half of RAM */
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#define CFG_MAX_USB_BOOT_FILE_SIZE 30*1024*1024 /* 30MB */
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#define CFG_MAX_USB_RECOVERY_FILE_SIZE 0xFA0000 /* 15.625MB */
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#define CFG_USB_BOOT_FILENAME "8dev_uimage.bin"
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#define CFG_USB_RECOVERY_FILENAME "8dev_recovery.bin"
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#define CFG_USB_RECOVERY_FW_START_IN_FLASH "0x9f050000"
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#define CFG_USB_BOOT_BUTTON_ID 0
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#define CONFIG_AUTOBOOT_KEYED
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#define CONFIG_AUTOBOOT_PROMPT "Hit '%s' key(s) to stop autoboot: %2d "
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#define CONFIG_AUTOBOOT_STOP_STR "\x1B"
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#undef CFG_BAUDRATE_TABLE
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#define CFG_BAUDRATE_TABLE { 300, 1200, 2400, 4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, \
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115200, 128000, 230400, 250000, 256000, 460800, 500000, 576000, 921600, \
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1000000, 1152000, 1500000, 2000000, 3000000}
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/*
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** Parameters defining the location of the calibration/initialization
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** information for the two Merlin devices.
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** NOTE: **This will change with different flash configurations**
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*/
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#define WLANCAL 0x9fff1000
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#define BOARDCAL 0x9fff0000
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#define ATHEROS_PRODUCT_ID 138
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#define CAL_SECTOR (CFG_MAX_FLASH_SECT - 1)
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/* For Kite, only PCI-e interface is valid */
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#define AR7240_ART_PCICFG_OFFSET 3
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#include <cmd_confdefs.h>
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#endif /* __CONFIG_H */
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