sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

am33xx: NAND support 

TI AM33XX has the same GPMC controller as OMAP3 so we could just use the
existing omap_gpmc driver. This patch adds adds required
definitions/intialization.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This commit is contained in:
Ilya Yanok 2012-11-06 13:06:30 +00:00 committed by Tom Rini
parent 70fb65b093
commit 8eb16b7f73
9 changed files with 370 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/cpu/armv7/am33xx/Makefile
View File

@ -18,6 +18,7 @@ LIB = $(obj)lib$(SOC).o
COBJS += clock.o
COBJS += sys_info.o
COBJS += mem.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o

1
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -25,6 +25,7 @@
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>

5
arch/arm/cpu/armv7/am33xx/clock.c
View File

@ -150,6 +150,11 @@ static void enable_per_clocks(void)
;
#endif /* CONFIG_SERIAL6 */
/* GPMC */
writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
;
/* MMC0*/
writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)

101
arch/arm/cpu/armv7/am33xx/mem.c Normal file
View File

@ -0,0 +1,101 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
*
* Author :
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Manikandan Pillai <mani.pillai@ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <command.h>
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
M_NAND_GPMC_CONFIG4,
M_NAND_GPMC_CONFIG5,
M_NAND_GPMC_CONFIG6, 0
};
#endif
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
(1 << 6)), &cs->config7);
sdelay(2000);
}
/*****************************************************
* gpmc_init(): init gpmc bus
* Init GPMC for x16, MuxMode (SDRAM in x32).
* This code can only be executed from SRAM or SDRAM.
*****************************************************/
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
gpmc_cfg = (struct gpmc *)GPMC_BASE;
#ifdef CONFIG_CMD_NAND
const u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
#endif
/* global settings */
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000100, &gpmc_cfg->irqstatus);
writel(0x00000200, &gpmc_cfg->irqenable);
writel(0x00000012, &gpmc_cfg->config);
/*
* Disable the GPMC0 config set by ROM code
*/
writel(0, &gpmc_cfg->cs[0].config7);
sdelay(1000);
#ifdef CONFIG_CMD_NAND
gpmc_config = gpmc_m_nand;
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#endif
}

53
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -60,6 +60,59 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
struct gpmc_cs {
u32 config1; /* 0x00 */
u32 config2; /* 0x04 */
u32 config3; /* 0x08 */
u32 config4; /* 0x0C */
u32 config5; /* 0x10 */
u32 config6; /* 0x14 */
u32 config7; /* 0x18 */
u32 nand_cmd; /* 0x1C */
u32 nand_adr; /* 0x20 */
u32 nand_dat; /* 0x24 */
u8 res[8]; /* blow up to 0x30 byte */
};
struct bch_res_0_3 {
u32 bch_result_x[4];
};
struct gpmc {
u8 res1[0x10];
u32 sysconfig; /* 0x10 */
u8 res2[0x4];
u32 irqstatus; /* 0x18 */
u32 irqenable; /* 0x1C */
u8 res3[0x20];
u32 timeout_control; /* 0x40 */
u8 res4[0xC];
u32 config; /* 0x50 */
u32 status; /* 0x54 */
u8 res5[0x8]; /* 0x58 */
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
u8 res6[0x14]; /* 0x1E0 */
u32 ecc_config; /* 0x1F4 */
u32 ecc_control; /* 0x1F8 */
u32 ecc_size_config; /* 0x1FC */
u32 ecc1_result; /* 0x200 */
u32 ecc2_result; /* 0x204 */
u32 ecc3_result; /* 0x208 */
u32 ecc4_result; /* 0x20C */
u32 ecc5_result; /* 0x210 */
u32 ecc6_result; /* 0x214 */
u32 ecc7_result; /* 0x218 */
u32 ecc8_result; /* 0x21C */
u32 ecc9_result; /* 0x220 */
u8 res7[12]; /* 0x224 */
u32 testmomde_ctrl; /* 0x230 */
u8 res8[12]; /* 0x234 */
struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
};
/* Used for board specific gpmc initialization */
extern struct gpmc *gpmc_cfg;
/* Encapsulating core pll registers */
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */

3
arch/arm/include/asm/arch-am33xx/hardware.h
View File

@ -80,6 +80,9 @@
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
/* GPMC Base address */
#define GPMC_BASE 0x50000000
/* CPSW Config space */
#define AM335X_CPSW_BASE 0x4A100000
#define AM335X_CPSW_MDIO_BASE 0x4A101000

83
arch/arm/include/asm/arch-am33xx/mem.h Normal file
View File

@ -0,0 +1,83 @@
/*
* (C) Copyright 2006-2008
* Texas Instruments, <www.ti.com>
*
* Author
* Mansoor Ahamed <mansoor.ahamed@ti.com>
*
* Initial Code from:
* Richard Woodruff <r-woodruff2@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MEM_H_
#define _MEM_H_
/*
* GPMC settings -
* Definitions is as per the following format
* #define <PART>_GPMC_CONFIG<x> <value>
* Where:
* PART is the part name e.g. STNOR - Intel Strata Flash
* x is GPMC config registers from 1 to 6 (there will be 6 macros)
* Value is corresponding value
*
* For every valid PRCM configuration there should be only one definition of
* the same. if values are independent of the board, this definition will be
* present in this file if values are dependent on the board, then this should
* go into corresponding mem-boardName.h file
*
* Currently valid part Names are (PART):
* M_NAND - Micron NAND
*/
#define GPMC_SIZE_256M 0x0
#define GPMC_SIZE_128M 0x8
#define GPMC_SIZE_64M 0xC
#define GPMC_SIZE_32M 0xE
#define GPMC_SIZE_16M 0xF
#define M_NAND_GPMC_CONFIG1 0x00000800
#define M_NAND_GPMC_CONFIG2 0x001e1e00
#define M_NAND_GPMC_CONFIG3 0x001e1e00
#define M_NAND_GPMC_CONFIG4 0x16051807
#define M_NAND_GPMC_CONFIG5 0x00151e1e
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */
#define GPMC_MAX_REG 7
#define PISMO1_NOR 1
#define PISMO1_NAND 2
#define PISMO2_CS0 3
#define PISMO2_CS1 4
#define PISMO1_ONENAND 5
#define DBG_MPDB 6
#define PISMO2_NAND_CS0 7
#define PISMO2_NAND_CS1 8
/* make it readable for the gpmc_init */
#define PISMO1_NOR_BASE FLASH_BASE
#define PISMO1_NAND_BASE CONFIG_SYS_NAND_BASE
#define PISMO1_NAND_SIZE GPMC_SIZE_256M
#endif /* endif _MEM_H_ */

120
arch/arm/include/asm/arch-am33xx/omap_gpmc.h Normal file
View File

@ -0,0 +1,120 @@
/*
* (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
* Rohit Choraria <rohitkc@ti.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_OMAP_GPMC_H
#define __ASM_ARCH_OMAP_GPMC_H
#define GPMC_BUF_EMPTY 0
#define GPMC_BUF_FULL 1
#define ECCCLEAR (0x1 << 8)
#define ECCRESULTREG1 (0x1 << 0)
#define ECCSIZE512BYTE 0xFF
#define ECCSIZE1 (ECCSIZE512BYTE << 22)
#define ECCSIZE0 (ECCSIZE512BYTE << 12)
#define ECCSIZE0SEL (0x000 << 0)
/* Generic ECC Layouts */
/* Large Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\
9, 10, 11, 12},\
.oobfree = {\
{.offset = 13,\
.length = 51 } } \
}
#endif
/* Large Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 12,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13},\
.oobfree = {\
{.offset = 14,\
.length = 50 } } \
}
#endif
/* Small Page x8 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {1, 2, 3},\
.oobfree = {\
{.offset = 4,\
.length = 12 } } \
}
#endif
/* Small Page x16 NAND device Layout */
#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT
#define GPMC_NAND_HW_ECC_LAYOUT {\
.eccbytes = 3,\
.eccpos = {2, 3, 4},\
.oobfree = {\
{.offset = 5,\
.length = 11 } } \
}
#endif
#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\
.eccbytes = 32,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
28, 29, 30, 31, 32, 33},\
.oobfree = {\
{.offset = 34,\
.length = 30 } } \
}
#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\
.eccbytes = 56,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
52, 53, 54, 55, 56, 57},\
.oobfree = {\
{.offset = 58,\
.length = 6 } } \
}
#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\
.eccbytes = 104,\
.eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\
28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\
52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\
64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\
76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\
88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\
100, 101, 102, 103, 104, 105},\
.oobfree = {\
{.offset = 106,\
.length = 8 } } \
}
#endif /* __ASM_ARCH_OMAP_GPMC_H */

3
arch/arm/include/asm/arch-am33xx/sys_proto.h
View File

@ -33,4 +33,7 @@ u32 get_device_type(void);
void setup_clocks_for_console(void);
void ddr_pll_config(unsigned int ddrpll_M);
void sdelay(unsigned long);
void gpmc_init(void);
void omap_nand_switch_ecc(int);
#endif