sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

powerpc/85xx: Fix e6500 L2 cache stash IDs 

The value written to L2CSR1 didn't match the value written to the
device tree.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Scott Wood 2014-03-26 20:30:56 -05:00 committed by York Sun
parent 44afbbc0f0
commit 8d451a7129
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -275,12 +275,16 @@ static inline void ft_fixup_l2cache(void *blob)
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
/* Only initialize every eighth thread */
if (reg && !((*reg) % 8))
#else
if (reg)
#endif
if (reg && !((*reg) % 8)) {
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
(*reg / 4) + 32 + 1);
}
#else
if (reg) {
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
(*reg * 2) + 32 + 1);
}
#endif
#endif
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);