Initial revision
This commit is contained in:
wdenk
parent
ef94f5da1d
commit
858b1a643f
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@ -0,0 +1,760 @@
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/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Note: Parts of these software are imported from
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* - UBL, The Universal Talkware Boot Loader
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* Copyright (C) 2000 Universal Talkware Inc.
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* - Linux
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*
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*
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*/
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#include <common.h>
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#ifdef CONFIG_VIDEO
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#include <command.h>
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#include <asm/processor.h>
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#include <devices.h>
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#include "video.h"
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#include <pci.h>
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#include "vga_table.h"
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#ifdef CONFIG_VIDEO_CT69000
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#define VIDEO_VEND_ID 0x102C
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#define VIDEO_DEV_ID 0x00C0
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#else
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#error CONFIG_VIDEO_CT69000 must be defined
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#endif
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/*
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* Routine for resent board info to video
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* resides in pip405.c
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*/
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extern void video_write_board_info(void);
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#undef VGA_DEBUG
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#ifdef VGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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#define VGA_MAXROWS 25
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#define VGA_MAXCOLS 80
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#define CRTC_CURSH 14 /* cursor high pos */
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#define CRTC_CURSL 15 /* cursor low pos */
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/* description of the hardware layout */
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#define ATTRI_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3c0 /* Index and Data write port of the attribute Registers */
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#define ATTRI_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3c1 /* Data port of the attribute Registers */
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#define STATUS_REG0 CFG_ISA_IO_BASE_ADDRESS | 0x3c2 /* Status Register 0 (read only) */
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#define MSR_REG_W CFG_ISA_IO_BASE_ADDRESS | 0x3c2 /* Misc. Output Register (write only) */
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#define SEQ_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3c4 /* Index port of the Sequencer Controller */
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#define SEQ_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3c5 /* Data port of the Sequencer Controller */
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#define COL_PAL_MASK CFG_ISA_IO_BASE_ADDRESS | 0x3c6 /* Color Palette Mask */
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#define COL_PAL_STAT CFG_ISA_IO_BASE_ADDRESS | 0x3c7 /* Color Palette Status (read only) */
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#define COL_PAL_IND_R CFG_ISA_IO_BASE_ADDRESS | 0x3c7 /* Color Palette Read Mode Index (write only) */
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#define COL_PAL_IND_W CFG_ISA_IO_BASE_ADDRESS | 0x3c8 /* Color Palette Write Mode Index */
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#define COL_PAL_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3c9 /* Color Palette Data Port */
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#define FCR_REG_R CFG_ISA_IO_BASE_ADDRESS | 0x3ca /* Feature Control Register (read only) */
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#define MSR_REG_R CFG_ISA_IO_BASE_ADDRESS | 0x3cc /* Misc. Output Register (read only) */
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#define GR_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3ce /* Index port of the Graphic Controller Registers */
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#define GR_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3cf /* Data port of the Graphic Controller Registers */
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#define FP_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d0 /* Index port of the Flat panel Registers */
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#define FP_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d1 /* Data port of the Flat panel Registers */
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#define MR_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d2 /* Index Port of the Multimedia Extension */
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#define MR_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d3 /* Data Port of the Multimedia Extension */
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#define CRT_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d4 /* Index port of the CRT Controller */
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#define CRT_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d5 /* Data port of the CRT Controller */
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#define XREG_INDEX CFG_ISA_IO_BASE_ADDRESS | 0x3d6 /* Extended Register index */
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#define XREG_DATA CFG_ISA_IO_BASE_ADDRESS | 0x3d7 /* Extended Register data */
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#define STATUS_REG1 CFG_ISA_IO_BASE_ADDRESS | 0x3da /* Input Status Register 1 (read only) */
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#define FCR_REG_W CFG_ISA_IO_BASE_ADDRESS | 0x3da /* Feature Control Register (write only) */
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static unsigned char * video_fb; /* Frame buffer */
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/* current hardware state */
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static int video_row;
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static int video_col;
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static unsigned char video_attr;
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static unsigned int font_base_addr;
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/**********************************************************************
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* some forward declerations...
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*/
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int video_init(int busdevfunc);
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void vga_set_attrib(void);
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void vga_set_crt(void);
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void vga_set_dac(void);
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void vga_set_gr(void);
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void vga_set_seq(void);
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void vga_set_xreg(void);
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void vga_write_sr(unsigned char reg,unsigned char val);
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void vga_write_gr(unsigned char reg,unsigned char val);
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void vga_write_cr(unsigned char reg,unsigned char val);
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void vga_set_font(void);
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/***************************************************************************
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* Init VGA Device
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*/
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int drv_video_init (void)
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{
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int error, devices = 1 ;
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device_t vgadev ;
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int busdevfunc;
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busdevfunc=pci_find_device(VIDEO_VEND_ID,VIDEO_DEV_ID,0); /* get PCI Device ID */
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if(busdevfunc==-1) {
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#ifdef CONFIG_VIDEO_ONBOARD
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printf("Error VGA Controller (%04X,%04X) not found\n",VIDEO_VEND_ID,VIDEO_DEV_ID);
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#endif
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return -1;
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}
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video_init(busdevfunc);
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video_write_board_info();
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memset (&vgadev, 0, sizeof(vgadev));
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strcpy(vgadev.name, "vga");
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vgadev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
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vgadev.putc = video_putc;
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vgadev.puts = video_puts;
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vgadev.getc = NULL;
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vgadev.tstc = NULL;
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error = device_register (&vgadev);
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return (error == 0) ? devices : error ;
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}
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/***********************************************************
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* VGA Initializing
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*/
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int video_init(int busdevfunc)
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{
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pci_read_config_dword(busdevfunc, PCI_BASE_ADDRESS_0, &font_base_addr);
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video_fb = (char*)font_base_addr; /* we look into the big linaer memory area */
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/* set the extended Registers */
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vga_set_xreg();
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/* set IO Addresses to 0x3Dx (color mode ) */
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out8(MSR_REG_W,0x01);
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/* Feature Control Register:
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Bits 7-4 Reserved = 0
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Bit 3 Vertical Sync select = 1 = Enabled
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Bits 2-0 Reserved = 010 = as read from memory.
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*/
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out8(FCR_REG_W,0x02);
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/* Miscelaneous output Register:
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Bits 7-6 (num lines) = 01 = VGA 400 lines,
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Bit 5 (Odd/Even Page) = 1 = Sleect high page of memory,
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Bit 4 reserved = 0,
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Bits 3-2 (Clocl Select) = 01 = 28.322Mhz
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Bit 1 = Display Ram Enable = 1 = Enable processor access.
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Bit 0 = Io Address Select = 1 = Color Graphics Enulation.
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*/
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out8(MSR_REG_W,0x67);
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/* set the palette */
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vga_set_dac();
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/* set the attributes (before we bring up the engine
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then we dont have to wait for refresh).
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*/
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vga_set_attrib();
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/* set the crontroller register. */
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vga_set_crt();
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vga_write_sr(0x00,0x01); /* synchronous reset */
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vga_write_sr(0x01,0x00); /* clocking mode */
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vga_write_sr(0x02,0x03); /* write to map 0, 1 */
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vga_write_sr(0x03,0x00); /* select character map 0 */
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vga_write_sr(0x04,0x03); /* even-odd addressing */
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vga_write_sr(0x00,0x03); /* clear synchronous reset */
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vga_set_seq(); /* Set the extended sr's. */
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vga_set_gr(); /* Set the graphic registers. */
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/* load the font */
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vga_set_font();
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/* initialize the rol/col counts and the text attribute. */
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video_row=0;
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video_col=0;
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video_attr = VGA_ATTR_CLR_WHT;
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/* Clear the video ram */
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video_clear();
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return 1;
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}
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void vga_set_font(void)
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{
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int i,j;
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char *fontmap;
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fontmap = (char *)font_base_addr;
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vga_write_sr(0x00,0x01); /* synchronous reset */
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vga_write_sr(0x04,0x06); /* sequential addressing */
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vga_write_sr(0x02,0x04); /* write to map 2 */
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vga_write_sr(0x00,0x03); /* clear synchronous reset */
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vga_write_gr(0x04,0x02); /* select map 2 */
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vga_write_gr(0x05,0x00); /* disable odd-even addressing */
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vga_write_gr(0x06,0x00); /* map start at 0xa0000 */
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for(i=0;i<0x100;i++) {
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for(j=0;j<0x10;j++) {
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*((char *)fontmap+i*32+j)=(char)fontdata_8x16[i*16+j];
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}
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}
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vga_write_sr(0x00,0x01); /* synchronous reset */
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vga_write_sr(0x02,0x03); /* write to map 0 and 1 */
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vga_write_sr(0x04,0x03); /* odd-even addressing */
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vga_write_sr(0x03,0x00); /* Character map 0 & 1 */
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vga_write_sr(0x00,0x03); /* clear synchronous reset */
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vga_write_gr(0x04,0x00); /* select map 0 for CPU */
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vga_write_gr(0x05,0x10); /* enable odd-even addressing */
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vga_write_gr(0x06,0x0E); /* map start at 0xb8000 */
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}
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/* since we are BIG endian, swap attributes and char */
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unsigned short vga_swap_short(unsigned short val)
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{
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unsigned short swapped;
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swapped = ((val & 0xff)<<8) | ((val & 0xff00)>>8);
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return swapped;
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}
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/****************************************************
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* Routines usable Outside world
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*/
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/* scolls the text up row rows */
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void video_scroll(int row)
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{
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unsigned short clear = ((unsigned short)video_attr << 8) | (' ');
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unsigned short* addr16 = &((unsigned short *)video_fb)[(VGA_MAXROWS-row)*VGA_MAXCOLS];
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int i;
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clear=vga_swap_short(clear);
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memcpy(video_fb, video_fb+row*(VGA_MAXCOLS*2), (VGA_MAXROWS-row)*(VGA_MAXCOLS*2));
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for (i = 0 ; i < row * VGA_MAXCOLS ; i++)
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addr16[i] = clear;
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video_row-=row;
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video_col=0;
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}
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unsigned long video_cursor(int col, int row)
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{
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unsigned short off = row * VGA_MAXCOLS + col ;
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unsigned long saved = (video_col << 16) | (video_row & 0xFFFF);
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video_col = col;
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video_row = row;
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vga_write_cr(CRTC_CURSH,(unsigned char)((off & 0xff00)>>8)); /* Cursor pos. high */
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vga_write_cr(CRTC_CURSL,(unsigned char)(off & 0xff)); /* Cursor pos. low */
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return saved;
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}
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void video_set_lxy(unsigned long lxy)
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{
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int col = (lxy >> 16) & 0xFFFF;
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int row = lxy & 0xFFFF;
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video_cursor(col,row);
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}
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unsigned long video_get_lxy(void)
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{
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return (video_col << 16) | (video_row & 0xFFFF);
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}
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void video_clear(void)
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{
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int i;
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unsigned short clear = ((unsigned short)video_attr << 8) | (' ');
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unsigned short * addr16 = (unsigned short * )video_fb;
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clear=vga_swap_short(clear);
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video_row = video_col = 0;
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for (i = 0 ; i < 2000 ; i++) {
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addr16[i] = clear;
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}
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}
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void video_copy(unsigned short *buffer)
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{
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int i;
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unsigned short * addr16 = (unsigned short * )video_fb;
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for (i = 0 ; i < 2000 ; i++) {
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buffer[i] = addr16[i];
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}
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}
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void video_write(unsigned short *buffer)
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{
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int i;
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unsigned short * addr16 = (unsigned short *)video_fb;
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for (i = 0 ; i < 2000 ; i++) {
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addr16[i] = buffer[i];
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}
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}
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void video_putc(char ch)
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{
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char* addr;
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#if 0
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char buf[48];
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char buf1[16];
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static int i=0;
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sprintf(buf1,"%02X ",ch);
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serial_puts(buf1);
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buf[i++]=((ch>=0x20)&&(ch<=0x7f)) ? ch : '.';
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if(i>=16) {
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buf[i++]='\n';
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buf[i]='\0';
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i=0;
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serial_puts(" ");
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serial_puts(buf);
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}
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#endif
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switch (ch) {
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case '\n':
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video_col=0;
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video_row++;
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break;
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case '\r':
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video_col=0;
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break;
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case '\t':
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video_col += 8 - video_col % 8;
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break;
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case '\a':
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/* beep(); */
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break;
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case '\b':
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if(video_col)
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video_col--;
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else
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return;
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break;
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default:
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addr = video_fb + 2 * video_row * 80 + 2 * video_col;
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*((char *)addr+1) = (char) video_attr;
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*((char *)addr) = (char) ch;
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video_col++;
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if (video_col > (VGA_MAXCOLS-1)) {
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video_row++;
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video_col=0;
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}
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}
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/* If we're on the bottom of the secreen, wrap one row */
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if (video_row > (VGA_MAXROWS-1))
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video_scroll(1);
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video_cursor(video_col, video_row);
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}
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unsigned char video_set_attr(unsigned char attr)
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{
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unsigned char saved_attr = video_attr;
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video_attr = attr;
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return saved_attr;
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}
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unsigned char video_set_attr_xy(unsigned char attr, int x, int y)
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{
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unsigned char *addr = video_fb + (x * 80 + y) * 2 + 1;
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unsigned char saved_attr = *addr;
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*addr = attr;
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return saved_attr;
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}
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/* put char at xy */
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void video_putc_xy(char ch, int x, int y)
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{
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video_col = x;
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video_row = y;
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video_putc(ch);
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}
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/* put char at xy relative to the position */
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void video_putc_rxy(char ch, int x, int y)
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{
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video_col += x;
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video_row += y;
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video_putc(ch);
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}
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/* put char with attribute at xy */
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void video_putc_axy(char ch, char attr, int x, int y)
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{
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unsigned char saved_attr = video_set_attr(attr);
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video_col = x;
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video_row = y;
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video_putc(ch);
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video_set_attr(saved_attr);
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}
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void video_puts(const char *s)
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{
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while(*s) {
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video_putc(*s);
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s++;
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}
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}
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void video_puts_a(const char *s, char attr)
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{
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unsigned char saved_attr = video_set_attr(attr);
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video_puts(s);
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video_set_attr(saved_attr);
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}
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void video_puts_xy(const char *s, int x, int y)
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{
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video_cursor(x,y);
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video_puts(s);
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}
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void video_puts_axy(const char *s, char attr, int x, int y)
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{
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unsigned char saved_attr = video_set_attr(attr);
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video_puts_xy(s, x, y);
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video_set_attr(saved_attr);
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}
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|
||||
void video_wipe_ca_area(unsigned char ch, char attr, int x, int y, int w, int h)
|
||||
{
|
||||
int r, c;
|
||||
/* better to do this as word writes */
|
||||
unsigned short * addr16 = (unsigned short *)video_fb + (y * 80 + x);
|
||||
unsigned short charattr = (unsigned short)ch << 8 | attr;
|
||||
charattr=vga_swap_short(charattr);
|
||||
for (r = 0 ; r < h ; r++, addr16 += 80) {
|
||||
for (c = 0 ; c < w ; c++) {
|
||||
addr16[c] = charattr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void video_wipe_a_area(unsigned char attr, int x, int y, int w, int h)
|
||||
{
|
||||
int r, c;
|
||||
/* better to do this as word writes */
|
||||
unsigned short * addr16 = (unsigned short *)video_fb + (y * 80 + x);
|
||||
for (r = 0 ; r < h ; r++, addr16 += 80) {
|
||||
for (c = 0 ; c < w ; c++) {
|
||||
((char*)addr16)[c*2+1] = attr;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void video_wipe_c_area(unsigned char ch, int x, int y, int w, int h)
|
||||
{
|
||||
int r, c;
|
||||
/* better to do this as word writes */
|
||||
unsigned short * addr16 = (unsigned short *)video_fb + (y * 80 + x);
|
||||
for (r = 0 ; r < h ; r++, addr16 += 80) {
|
||||
for (c = 0 ; c < w ; c++) {
|
||||
((char*)addr16)[c*2] = ch;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
tl t tr
|
||||
l l
|
||||
bl b br
|
||||
*/
|
||||
typedef struct {
|
||||
unsigned char tl; /* top left corner */
|
||||
unsigned char t; /* top edge */
|
||||
unsigned char tr; /* top right corner */
|
||||
unsigned char l; /* left edge */
|
||||
unsigned char r; /* right edge */
|
||||
unsigned char bl; /* bottom left corner */
|
||||
unsigned char b; /* bottom edge */
|
||||
unsigned char br; /* bottom right corner */
|
||||
} box_chars_t;
|
||||
|
||||
box_chars_t sbox_chars = {
|
||||
0xDA, 0xC4, 0xBF,
|
||||
0xB3, 0xB3,
|
||||
0xC0, 0xC4, 0xD9
|
||||
};
|
||||
|
||||
box_chars_t dbox_chars = {
|
||||
0xC9, 0xCD, 0xBB,
|
||||
0xBA, 0xBA,
|
||||
0xC8, 0xCD, 0xBC
|
||||
};
|
||||
|
||||
static char cmap[] = "0123456789ABCDEF";
|
||||
void video_putchex(char c)
|
||||
{
|
||||
video_putc(cmap[(c >> 4 ) & 0xF]);
|
||||
video_putc(cmap[c & 0xF]);
|
||||
}
|
||||
|
||||
void video_putchexl(char c)
|
||||
{
|
||||
video_putc(cmap[c & 0xF]);
|
||||
}
|
||||
|
||||
void video_putchexh(char c)
|
||||
{
|
||||
video_putc(cmap[(c >> 4) & 0xF]);
|
||||
}
|
||||
|
||||
#define VGA_CELL_CA(a,c) (((unsigned short)c<<8)|a) /* for BIG endians */
|
||||
|
||||
void video_gbox_area(box_chars_t *box_chars_p, int x, int y, int w, int h)
|
||||
{
|
||||
int r, c;
|
||||
/* better to do this as word writes */
|
||||
unsigned short* addr16 = (unsigned short *)video_fb + (y * VGA_MAXCOLS + x);
|
||||
for (r = 0 ; r < h ; r++, addr16 += VGA_MAXCOLS) {
|
||||
if (r == 0) {
|
||||
addr16[0] = VGA_CELL_CA(video_attr, box_chars_p->tl);
|
||||
addr16[w-1] = VGA_CELL_CA(video_attr, box_chars_p->tr);
|
||||
for (c = 1 ; c < w - 1 ; c++)
|
||||
addr16[c] = VGA_CELL_CA(video_attr, box_chars_p->t);
|
||||
} else if (r == h - 1) {
|
||||
addr16[0] = VGA_CELL_CA(video_attr, box_chars_p->bl);
|
||||
addr16[w-1] = VGA_CELL_CA(video_attr, box_chars_p->br);
|
||||
for (c = 1 ; c < w - 1 ; c++)
|
||||
addr16[c] = VGA_CELL_CA(video_attr, box_chars_p->b);
|
||||
} else {
|
||||
addr16[0] = VGA_CELL_CA(video_attr, box_chars_p->l);
|
||||
addr16[w-1] = VGA_CELL_CA(video_attr, box_chars_p->r);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Writes a box on the screen */
|
||||
void video_box_area(int x, int y, int w, int h) {
|
||||
video_gbox_area(&sbox_chars, x, y, w, h);
|
||||
}
|
||||
/*writes a box with double lines on the screen */
|
||||
void video_dbox_area(int x, int y, int w, int h) {
|
||||
video_gbox_area(&dbox_chars, x, y, w, h);
|
||||
}
|
||||
|
||||
/* routines to set the VGA registers */
|
||||
|
||||
/* set attributes */
|
||||
void vga_set_attrib(void)
|
||||
{
|
||||
int i;
|
||||
unsigned char status;
|
||||
|
||||
status=in8(STATUS_REG1);
|
||||
i=0;
|
||||
|
||||
while(attr[i].reg!=0xFF) {
|
||||
out8(ATTRI_INDEX,attr[i].reg);
|
||||
out8(ATTRI_INDEX,attr[i].val); /* Attribute uses index for index and data */
|
||||
i++;
|
||||
}
|
||||
out8(ATTRI_INDEX,0x20); /* unblank the screen */
|
||||
}
|
||||
|
||||
/* set CRT Controller Registers */
|
||||
void vga_set_crt(void)
|
||||
{
|
||||
int i;
|
||||
i=0;
|
||||
while(crtc[i].reg!=0xFF) {
|
||||
out8(CRT_INDEX,crtc[i].reg);
|
||||
out8(CRT_DATA,crtc[i].val);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
/* Set Palette Registers (DAC) */
|
||||
void vga_set_dac(void)
|
||||
{
|
||||
int i;
|
||||
for(i=0;i<256;i++) {
|
||||
out8(COL_PAL_IND_W,(unsigned char)i);
|
||||
out8(COL_PAL_DATA,dac[i][0]); /* red */
|
||||
out8(COL_PAL_DATA,dac[i][1]); /* green */
|
||||
out8(COL_PAL_DATA,dac[i][2]); /* blue */
|
||||
}
|
||||
out8(COL_PAL_MASK,0xff); /* set mask */
|
||||
}
|
||||
/* set Graphic Controller Register */
|
||||
void vga_set_gr(void)
|
||||
{
|
||||
int i;
|
||||
i=0;
|
||||
while(grmr[i].reg!=0xFF) {
|
||||
out8(GR_INDEX,grmr[i].reg);
|
||||
out8(GR_DATA,grmr[i].val);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Set Sequencer Registers */
|
||||
void vga_set_seq(void)
|
||||
{
|
||||
int i;
|
||||
i=0;
|
||||
while(seq[i].reg!=0xFF) {
|
||||
out8(SEQ_INDEX,seq[i].reg);
|
||||
out8(SEQ_DATA,seq[i].val);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Set Extension Registers */
|
||||
void vga_set_xreg(void)
|
||||
{
|
||||
int i;
|
||||
i=0;
|
||||
while(xreg[i].reg!=0xFF) {
|
||||
out8(XREG_INDEX,xreg[i].reg);
|
||||
out8(XREG_DATA,xreg[i].val);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************
|
||||
* some helping routines
|
||||
*/
|
||||
|
||||
void vga_write_sr(unsigned char reg,unsigned char val)
|
||||
{
|
||||
out8(SEQ_INDEX,reg);
|
||||
out8(SEQ_DATA,val);
|
||||
}
|
||||
|
||||
|
||||
void vga_write_gr(unsigned char reg,unsigned char val)
|
||||
{
|
||||
out8(GR_INDEX,reg);
|
||||
out8(GR_DATA,val);
|
||||
}
|
||||
|
||||
void vga_write_cr(unsigned char reg,unsigned char val)
|
||||
{
|
||||
out8(CRT_INDEX,reg);
|
||||
out8(CRT_DATA,val);
|
||||
}
|
||||
|
||||
|
||||
#if 0
|
||||
void video_dump_reg(void)
|
||||
{
|
||||
/* first dump attributes */
|
||||
int i;
|
||||
unsigned char status;
|
||||
|
||||
|
||||
printf("Extended Regs:\n");
|
||||
i=0;
|
||||
while(xreg[i].reg!=0xFF) {
|
||||
out8(XREG_INDEX,xreg[i].reg);
|
||||
status=in8(XREG_DATA);
|
||||
printf("XR%02X is %02X, should be %02X\n",xreg[i].reg,status,xreg[i].val);
|
||||
i++;
|
||||
}
|
||||
printf("Sequencer Regs:\n");
|
||||
i=0;
|
||||
while(seq[i].reg!=0xFF) {
|
||||
out8(SEQ_INDEX,seq[i].reg);
|
||||
status=in8(SEQ_DATA);
|
||||
printf("SR%02X is %02X, should be %02X\n",seq[i].reg,status,seq[i].val);
|
||||
i++;
|
||||
}
|
||||
printf("Graphic Regs:\n");
|
||||
i=0;
|
||||
while(grmr[i].reg!=0xFF) {
|
||||
out8(GR_INDEX,grmr[i].reg);
|
||||
status=in8(GR_DATA);
|
||||
printf("GR%02X is %02X, should be %02X\n",grmr[i].reg,status,grmr[i].val);
|
||||
i++;
|
||||
}
|
||||
printf("CRT Regs:\n");
|
||||
i=0;
|
||||
while(crtc[i].reg!=0xFF) {
|
||||
out8(CRT_INDEX,crtc[i].reg);
|
||||
status=in8(CRT_DATA);
|
||||
printf("CR%02X is %02X, should be %02X\n",crtc[i].reg,status,crtc[i].val);
|
||||
i++;
|
||||
}
|
||||
printf("Attributes:\n");
|
||||
status=in8(STATUS_REG1);
|
||||
i=0;
|
||||
while(attr[i].reg!=0xFF) {
|
||||
out8(ATTRI_INDEX,attr[i].reg);
|
||||
status=in8(ATTRI_DATA);
|
||||
out8(ATTRI_INDEX,attr[i].val); /* Attribute uses index for index and data */
|
||||
printf("AR%02X is %02X, should be %02X\n",attr[i].reg,status,attr[i].val);
|
||||
i++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_VIDEO */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_VIDEO
|
||||
#ifndef _VIDEO_H
|
||||
#define _VIDEO_H
|
||||
|
||||
int video_init(int busdevfunc);
|
||||
void video_clear(void);
|
||||
void video_putc(char ch);
|
||||
void video_puts(const char *s);
|
||||
void video_puts_a(const char *s, char attr);
|
||||
unsigned char video_set_attr(unsigned char attr);
|
||||
|
||||
void video_box_area(int x, int y, int w, int h);
|
||||
void video_dbox_area(int x, int y, int w, int h);
|
||||
void video_wipe_c_area(unsigned char ch, int x, int y, int w, int h);
|
||||
|
||||
void video_wipe_a_area(unsigned char attr, int x, int y, int w, int h);
|
||||
void video_wipe_ca_area(unsigned char ch, char attr, int x, int y, int w, int h);
|
||||
void video_puts_axy(const char *s, char attr, int x, int y);
|
||||
void video_putc_rxy(char ch, int x, int y);
|
||||
void video_putc_xy(char ch, int x, int y);
|
||||
unsigned char video_set_attr_xy(unsigned char attr, int x, int y);
|
||||
void video_copy(unsigned short *buffer);
|
||||
void video_write(unsigned short *buffer);
|
||||
|
||||
#define VGA_ATTR_CLR_RED 0x4
|
||||
#define VGA_ATTR_CLR_GRN 0x2
|
||||
#define VGA_ATTR_CLR_BLU 0x1
|
||||
#define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN)
|
||||
#define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
|
||||
#define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED)
|
||||
#define VGA_ATTR_CLR_BLK 0
|
||||
#define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU)
|
||||
|
||||
#define VGA_ATTR_BNK 0x80
|
||||
#define VGA_ATTR_ITN 0x08
|
||||
|
||||
#define VGA_ATTR_BG_MSK 0x70
|
||||
#define VGA_ATTR_FG_MSK 0x07
|
||||
|
||||
#define VGA_ATTR_BG_GET(v) (((v) & VGA_ATTR_BG_MSK)>>4)
|
||||
#define VGA_ATTR_BG_SET(v, c) (((c) & VGA_ATTR_FG_MSK)<<4) | (v & ~VGA_ATTR_BG_MSK))
|
||||
|
||||
#define VGA_ATTR_FG_GET(v) ((v) & VGA_ATTR_FG_MSK)
|
||||
#define VGA_ATTR_FG_SET(v, c) ((c) & VGA_ATTR_FG_MSK) | (v & ~VGA_ATTR_FG_MSK))
|
||||
|
||||
#define VGA_ATTR_FG_BG_SET(v, b, f) (VGA_ATTR_BG_SET(v, b) | VGA_ATTR_FG_SET(v, cf))
|
||||
|
||||
#define VGA_ATTR_INVERT(A) ((((A)&0x7)<<4)|(((A)&0x70)>>4) |((A)&0x88))
|
||||
|
||||
#endif /* _VIDEO_H */
|
||||
#endif /* CONFIG_VIDEO */
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* hacked for MIP405
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "mip405.h"
|
||||
#include "../common/common_util.h"
|
||||
|
||||
|
||||
extern void print_mip405_info(void);
|
||||
extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int do_mip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
|
||||
ulong led_on;
|
||||
|
||||
if (strcmp(argv[1], "info") == 0)
|
||||
{
|
||||
print_mip405_info();
|
||||
return 0;
|
||||
}
|
||||
if (strcmp(argv[1], "led") == 0)
|
||||
{
|
||||
led_on = (ulong)simple_strtoul(argv[2], NULL, 10);
|
||||
user_led0(led_on);
|
||||
return 0;
|
||||
}
|
||||
return (do_mplcommon(cmdtp, flag, argc, argv));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
@ -0,0 +1,675 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*
|
||||
* TODO: clean-up
|
||||
*/
|
||||
|
||||
/*
|
||||
* How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
|
||||
*
|
||||
* As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
|
||||
* used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
|
||||
* parameters from the datasheet are:
|
||||
* Tclk = 7.5ns (CL = 2)
|
||||
* Trp = 15ns
|
||||
* Trc = 60ns
|
||||
* Trcd = 15ns
|
||||
* Trfc = 66ns
|
||||
*
|
||||
* If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
|
||||
* period is 10ns and the parameters needed for the Timing Register are:
|
||||
* CASL = CL = 2 clock cycles
|
||||
* PTA = Trp = 15ns / 10ns = 2 clock cycles
|
||||
* CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
|
||||
* LDF = 2 clock cycles (but can be extended to meet board-level timing)
|
||||
* RFTA = Trfc = 66ns / 10ns= 7 clock cycles
|
||||
* RCD = Trcd = 15ns / 10ns= 2 clock cycles
|
||||
*
|
||||
* The actual bit settings in the register would be:
|
||||
*
|
||||
* CASL = 0b01
|
||||
* PTA = 0b01
|
||||
* CTP = 0b10
|
||||
* LDF = 0b01
|
||||
* RFTA = 0b011
|
||||
* RCD = 0b01
|
||||
*
|
||||
* If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
|
||||
* instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
|
||||
* defined as Trc rather than Trfc.
|
||||
* When using DIMM modules, most but not all of the required timing parameters can be read
|
||||
* from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
|
||||
* are not available from the EEPROM
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "mip405.h"
|
||||
#include <asm/processor.h>
|
||||
#include <405gp_i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include "../common/common_util.h"
|
||||
#include <i2c.h>
|
||||
extern block_dev_desc_t * scsi_get_dev(int dev);
|
||||
extern block_dev_desc_t * ide_get_dev(int dev);
|
||||
|
||||
#undef SDRAM_DEBUG
|
||||
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
|
||||
/* stdlib.h causes some compatibility problems; should fixe these! -- wd */
|
||||
#ifndef __ldiv_t_defined
|
||||
typedef struct {
|
||||
long int quot; /* Quotient */
|
||||
long int rem; /* Remainder */
|
||||
} ldiv_t;
|
||||
extern ldiv_t ldiv (long int __numer, long int __denom);
|
||||
# define __ldiv_t_defined 1
|
||||
#endif
|
||||
|
||||
|
||||
#define PLD_PART_REG PER_PLD_ADDR + 0
|
||||
#define PLD_VERS_REG PER_PLD_ADDR + 1
|
||||
#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
|
||||
#define PLD_IRQ_REG PER_PLD_ADDR + 3
|
||||
#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
|
||||
#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
|
||||
|
||||
#define MEGA_BYTE (1024*1024)
|
||||
|
||||
typedef struct {
|
||||
unsigned char boardtype; /* Board revision and Population Options */
|
||||
unsigned char cal; /* cas Latency (will be programmend as cal-1) */
|
||||
unsigned char trp; /* datain27 in clocks */
|
||||
unsigned char trcd; /* datain29 in clocks */
|
||||
unsigned char tras; /* datain30 in clocks */
|
||||
unsigned char tctp; /* tras - trcd in clocks */
|
||||
unsigned char am; /* Address Mod (will be programmed as am-1) */
|
||||
unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
|
||||
unsigned char ecc; /* if true, ecc is enabled */
|
||||
} sdram_t;
|
||||
|
||||
const sdram_t sdram_table[] = {
|
||||
{ 0x0f, /* Rev A, 128MByte -1 Board */
|
||||
3, /* Case Latenty = 3 */
|
||||
3, /* trp 20ns / 7.5 ns datain[27] */
|
||||
3, /* trcd 20ns /7.5 ns (datain[29]) */
|
||||
6, /* tras 44ns /7.5 ns (datain[30]) */
|
||||
4, /* tcpt 44 - 20ns = 24ns */
|
||||
3, /* Address Mode = 3 */
|
||||
5, /* size value */
|
||||
1}, /* ECC enabled */
|
||||
{ 0x07, /* Rev A, 64MByte -2 Board */
|
||||
3, /* Case Latenty = 3 */
|
||||
3, /* trp 20ns / 7.5 ns datain[27] */
|
||||
3, /* trcd 20ns /7.5 ns (datain[29]) */
|
||||
6, /* tras 44ns /7.5 ns (datain[30]) */
|
||||
4, /* tcpt 44 - 20ns = 24ns */
|
||||
2, /* Address Mode = 2 */
|
||||
4, /* size value */
|
||||
1}, /* ECC enabled */
|
||||
{ 0xff, /* terminator */
|
||||
0xff,
|
||||
0xff,
|
||||
0xff,
|
||||
0xff,
|
||||
0xff,
|
||||
0xff,
|
||||
0xff }
|
||||
};
|
||||
|
||||
void SDRAM_err (const char *s)
|
||||
{
|
||||
#ifndef SDRAM_DEBUG
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = 9600;
|
||||
serial_init ();
|
||||
#endif
|
||||
serial_puts ("\n");
|
||||
serial_puts (s);
|
||||
serial_puts ("\n enable SDRAM_DEBUG for more info\n");
|
||||
for (;;);
|
||||
}
|
||||
|
||||
|
||||
unsigned char get_board_revcfg (void)
|
||||
{
|
||||
out8 (PER_BOARD_ADDR, 0);
|
||||
return (in8 (PER_BOARD_ADDR));
|
||||
}
|
||||
|
||||
|
||||
#ifdef SDRAM_DEBUG
|
||||
|
||||
void write_hex (unsigned char i)
|
||||
{
|
||||
char cc;
|
||||
|
||||
cc = i >> 4;
|
||||
cc &= 0xf;
|
||||
if (cc > 9)
|
||||
serial_putc (cc + 55);
|
||||
else
|
||||
serial_putc (cc + 48);
|
||||
cc = i & 0xf;
|
||||
if (cc > 9)
|
||||
serial_putc (cc + 55);
|
||||
else
|
||||
serial_putc (cc + 48);
|
||||
}
|
||||
|
||||
void write_4hex (unsigned long val)
|
||||
{
|
||||
write_hex ((unsigned char) (val >> 24));
|
||||
write_hex ((unsigned char) (val >> 16));
|
||||
write_hex ((unsigned char) (val >> 8));
|
||||
write_hex ((unsigned char) val);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
int init_sdram (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
unsigned long tmp, baseaddr;
|
||||
unsigned short i;
|
||||
unsigned char trp_clocks,
|
||||
trcd_clocks,
|
||||
tras_clocks,
|
||||
trc_clocks,
|
||||
tctp_clocks;
|
||||
unsigned char cal_val;
|
||||
unsigned char bc;
|
||||
unsigned long pbcr, sdram_tim, sdram_bank;
|
||||
unsigned long *p;
|
||||
|
||||
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
(void) get_clocks ();
|
||||
gd->baudrate = 9600;
|
||||
serial_init ();
|
||||
serial_puts ("\nInitializing SDRAM, Please stand by");
|
||||
mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
|
||||
pbcr = mfdcr (ebccfgd);
|
||||
if ((pbcr & 0x00002000) == 0) {
|
||||
/* MPS Boot, set up the flash */
|
||||
mtdcr (ebccfga, pb1ap);
|
||||
mtdcr (ebccfgd, FLASH_AP);
|
||||
mtdcr (ebccfga, pb1cr);
|
||||
mtdcr (ebccfgd, FLASH_CR);
|
||||
} else {
|
||||
/* Flash boot, set up the MPS */
|
||||
mtdcr (ebccfga, pb1ap);
|
||||
mtdcr (ebccfgd, MPS_AP);
|
||||
mtdcr (ebccfga, pb1cr);
|
||||
mtdcr (ebccfgd, MPS_CR);
|
||||
}
|
||||
/* set up UART0 (CS2) and UART1 (CS3) */
|
||||
mtdcr (ebccfga, pb2ap);
|
||||
mtdcr (ebccfgd, UART0_AP);
|
||||
mtdcr (ebccfga, pb2cr);
|
||||
mtdcr (ebccfgd, UART0_CR);
|
||||
mtdcr (ebccfga, pb3ap);
|
||||
mtdcr (ebccfgd, UART1_AP);
|
||||
mtdcr (ebccfga, pb3cr);
|
||||
mtdcr (ebccfgd, UART1_CR);
|
||||
|
||||
/* set up the pld */
|
||||
mtdcr (ebccfga, pb7ap);
|
||||
mtdcr (ebccfgd, PLD_AP);
|
||||
mtdcr (ebccfga, pb7cr);
|
||||
mtdcr (ebccfgd, PLD_CR);
|
||||
/* set up the board rev reg */
|
||||
mtdcr (ebccfga, pb5ap);
|
||||
mtdcr (ebccfgd, BOARD_AP);
|
||||
mtdcr (ebccfga, pb5cr);
|
||||
mtdcr (ebccfgd, BOARD_CR);
|
||||
|
||||
|
||||
#ifdef SDRAM_DEBUG
|
||||
out8 (PER_BOARD_ADDR, 0);
|
||||
bc = in8 (PER_BOARD_ADDR);
|
||||
serial_puts ("\nBoard Rev: ");
|
||||
write_hex (bc);
|
||||
serial_puts (" (PLD=");
|
||||
bc = in8 (PLD_BOARD_CFG_REG);
|
||||
write_hex (bc);
|
||||
serial_puts (")\n");
|
||||
#endif
|
||||
bc = get_board_revcfg ();
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("\nstart SDRAM Setup\n");
|
||||
serial_puts ("\nBoard Rev: ");
|
||||
write_hex (bc);
|
||||
serial_puts ("\n");
|
||||
#endif
|
||||
i = 0;
|
||||
baseaddr = CFG_SDRAM_BASE;
|
||||
while (sdram_table[i].sz != 0xff) {
|
||||
if (sdram_table[i].boardtype == bc)
|
||||
break;
|
||||
i++;
|
||||
}
|
||||
if (sdram_table[i].boardtype != bc)
|
||||
SDRAM_err ("No SDRAM table found for this board!!!\n");
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts (" found table ");
|
||||
write_hex (i);
|
||||
serial_puts (" \n");
|
||||
#endif
|
||||
cal_val = sdram_table[i].cal - 1; /* Cas Latency */
|
||||
trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
|
||||
trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
|
||||
tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
|
||||
/* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
|
||||
tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
|
||||
/* trc_clocks is sum of trp_clocks + tras_clocks */
|
||||
trc_clocks = trp_clocks + tras_clocks;
|
||||
/* get SDRAM timing register */
|
||||
mtdcr (memcfga, mem_sdtr1);
|
||||
sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
|
||||
/* insert CASL value */
|
||||
sdram_tim |= ((unsigned long) (cal_val)) << 23;
|
||||
/* insert PTA value */
|
||||
sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
|
||||
/* insert CTP value */
|
||||
sdram_tim |=
|
||||
((unsigned long) (trc_clocks - trp_clocks -
|
||||
trcd_clocks)) << 16;
|
||||
/* insert LDF (always 01) */
|
||||
sdram_tim |= ((unsigned long) 0x01) << 14;
|
||||
/* insert RFTA value */
|
||||
sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
|
||||
/* insert RCD value */
|
||||
sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
|
||||
|
||||
tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
|
||||
/* insert SZ value; */
|
||||
tmp |= ((unsigned long) sdram_table[i].sz << 17);
|
||||
/* get SDRAM bank 0 register */
|
||||
mtdcr (memcfga, mem_mb0cf);
|
||||
sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
|
||||
sdram_bank |= (baseaddr | tmp | 0x01);
|
||||
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("sdtr: ");
|
||||
write_4hex (sdram_tim);
|
||||
serial_puts ("\n");
|
||||
#endif
|
||||
|
||||
/* write SDRAM timing register */
|
||||
mtdcr (memcfga, mem_sdtr1);
|
||||
mtdcr (memcfgd, sdram_tim);
|
||||
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("mb0cf: ");
|
||||
write_4hex (sdram_bank);
|
||||
serial_puts ("\n");
|
||||
#endif
|
||||
|
||||
/* write SDRAM bank 0 register */
|
||||
mtdcr (memcfga, mem_mb0cf);
|
||||
mtdcr (memcfgd, sdram_bank);
|
||||
|
||||
if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
|
||||
/* get SDRAM refresh interval register */
|
||||
mtdcr (memcfga, mem_rtr);
|
||||
tmp = mfdcr (memcfgd) & ~0x3FF80000;
|
||||
tmp |= 0x07F00000;
|
||||
} else {
|
||||
/* get SDRAM refresh interval register */
|
||||
mtdcr (memcfga, mem_rtr);
|
||||
tmp = mfdcr (memcfgd) & ~0x3FF80000;
|
||||
tmp |= 0x05F00000;
|
||||
}
|
||||
/* write SDRAM refresh interval register */
|
||||
mtdcr (memcfga, mem_rtr);
|
||||
mtdcr (memcfgd, tmp);
|
||||
/* enable ECC if used */
|
||||
#if 1
|
||||
if (sdram_table[i].ecc) {
|
||||
/* disable checking for all banks */
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("disable ECC.. ");
|
||||
#endif
|
||||
mtdcr (memcfga, mem_ecccf);
|
||||
tmp = mfdcr (memcfgd);
|
||||
tmp &= 0xff0fffff; /* disable all banks */
|
||||
mtdcr (memcfga, mem_ecccf);
|
||||
/* set up SDRAM Controller with ECC enabled */
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("setup SDRAM Controller.. ");
|
||||
#endif
|
||||
mtdcr (memcfgd, tmp);
|
||||
mtdcr (memcfga, mem_mcopt1);
|
||||
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
|
||||
mtdcr (memcfga, mem_mcopt1);
|
||||
mtdcr (memcfgd, tmp);
|
||||
udelay (600);
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("fill the memory..\n");
|
||||
#endif
|
||||
serial_puts (".");
|
||||
/* now, fill all the memory */
|
||||
tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
|
||||
p = (unsigned long) 0;
|
||||
while ((unsigned long) p < tmp) {
|
||||
*p++ = 0L;
|
||||
if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
|
||||
serial_puts (".");
|
||||
|
||||
|
||||
}
|
||||
/* enable bank 0 */
|
||||
serial_puts (".");
|
||||
#ifdef SDRAM_DEBUG
|
||||
serial_puts ("enable ECC\n");
|
||||
#endif
|
||||
udelay (400);
|
||||
mtdcr (memcfga, mem_ecccf);
|
||||
tmp = mfdcr (memcfgd);
|
||||
tmp |= 0x00800000; /* enable bank 0 */
|
||||
mtdcr (memcfgd, tmp);
|
||||
udelay (400);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
|
||||
mtdcr (memcfga, mem_mcopt1);
|
||||
tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
|
||||
mtdcr (memcfga, mem_mcopt1);
|
||||
mtdcr (memcfgd, tmp);
|
||||
udelay (400);
|
||||
}
|
||||
serial_puts ("\n");
|
||||
return (0);
|
||||
}
|
||||
|
||||
int board_pre_init (void)
|
||||
{
|
||||
init_sdram ();
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Interrupt controller setup for the PIP405 board.
|
||||
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
|
||||
| IRQ 16 405GP internally generated; active low; level sensitive
|
||||
| IRQ 17-24 RESERVED
|
||||
| IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
|
||||
| IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
|
||||
| IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
|
||||
| IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
|
||||
| IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
|
||||
| IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
|
||||
| IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
|
||||
| Note for MIP405 board:
|
||||
| An interrupt taken for the SouthBridge (IRQ 25) indicates that
|
||||
| the Interrupt Controller in the South Bridge has caused the
|
||||
| interrupt. The IC must be read to determine which device
|
||||
| caused the interrupt.
|
||||
|
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr (uicer, 0x00000000); /* disable all ints */
|
||||
mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
|
||||
mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
|
||||
mtdcr (uictr, 0x10000000); /* set int trigger levels */
|
||||
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Get some PLD Registers
|
||||
*/
|
||||
|
||||
unsigned short get_pld_parvers (void)
|
||||
{
|
||||
unsigned short result;
|
||||
unsigned char rc;
|
||||
|
||||
rc = in8 (PLD_PART_REG);
|
||||
result = (unsigned short) rc << 8;
|
||||
rc = in8 (PLD_VERS_REG);
|
||||
result |= rc;
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void user_led0 (unsigned char on)
|
||||
{
|
||||
if (on)
|
||||
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
|
||||
else
|
||||
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
|
||||
}
|
||||
|
||||
|
||||
void ide_set_reset (int idereset)
|
||||
{
|
||||
/* if reset = 1 IDE reset will be asserted */
|
||||
if (idereset)
|
||||
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
|
||||
else {
|
||||
udelay (10000);
|
||||
out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
unsigned char s[50];
|
||||
unsigned char bc, var, rc;
|
||||
int i;
|
||||
backup_t *b = (backup_t *) s;
|
||||
|
||||
puts ("Board: ");
|
||||
|
||||
bc = get_board_revcfg ();
|
||||
var = ~bc;
|
||||
var &= 0xf;
|
||||
rc = 0;
|
||||
for (i = 0; i < 4; i++) {
|
||||
rc <<= 1;
|
||||
rc += (var & 0x1);
|
||||
var >>= 1;
|
||||
}
|
||||
rc++;
|
||||
i = getenv_r ("serial#", s, 32);
|
||||
if ((i == 0) || strncmp (s, "MIP405", 6)) {
|
||||
get_backup_values (b);
|
||||
if (strncmp (b->signature, "MPL\0", 4) != 0) {
|
||||
puts ("### No HW ID - assuming MIP405");
|
||||
printf ("-%d Rev %c", rc, 'A' + ((bc >> 4) & 0xf));
|
||||
} else {
|
||||
b->serial_name[6] = 0;
|
||||
printf ("%s-%d Rev %c SN: %s", b->serial_name, rc,
|
||||
'A' + ((bc >> 4) & 0xf), &b->serial_name[7]);
|
||||
}
|
||||
} else {
|
||||
s[6] = 0;
|
||||
printf ("%s-%d Rev %c SN: %s", s, rc, 'A' + ((bc >> 4) & 0xf),
|
||||
&s[7]);
|
||||
}
|
||||
bc = in8 (PLD_EXT_CONF_REG);
|
||||
printf (" Boot Config: 0x%x\n", bc);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/*
|
||||
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
|
||||
the necessary info for SDRAM controller configuration
|
||||
*/
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
static int test_dram (unsigned long ramsize);
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
|
||||
unsigned long bank_reg[4], tmp, bank_size;
|
||||
int i, ds;
|
||||
unsigned long TotalSize;
|
||||
|
||||
ds = 0;
|
||||
/* since the DRAM controller is allready set up, calculate the size with the
|
||||
bank registers */
|
||||
mtdcr (memcfga, mem_mb0cf);
|
||||
bank_reg[0] = mfdcr (memcfgd);
|
||||
mtdcr (memcfga, mem_mb1cf);
|
||||
bank_reg[1] = mfdcr (memcfgd);
|
||||
mtdcr (memcfga, mem_mb2cf);
|
||||
bank_reg[2] = mfdcr (memcfgd);
|
||||
mtdcr (memcfga, mem_mb3cf);
|
||||
bank_reg[3] = mfdcr (memcfgd);
|
||||
TotalSize = 0;
|
||||
for (i = 0; i < 4; i++) {
|
||||
if ((bank_reg[i] & 0x1) == 0x1) {
|
||||
tmp = (bank_reg[i] >> 17) & 0x7;
|
||||
bank_size = 4 << tmp;
|
||||
TotalSize += bank_size;
|
||||
} else
|
||||
ds = 1;
|
||||
}
|
||||
mtdcr (memcfga, mem_ecccf);
|
||||
tmp = mfdcr (memcfgd);
|
||||
|
||||
if (!tmp)
|
||||
printf ("No ");
|
||||
printf ("ECC ");
|
||||
|
||||
test_dram (TotalSize * MEGA_BYTE);
|
||||
return (TotalSize * MEGA_BYTE);
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
extern int mem_test (unsigned long start, unsigned long ramsize,
|
||||
int quiet);
|
||||
|
||||
static int test_dram (unsigned long ramsize)
|
||||
{
|
||||
#ifdef SDRAM_DEBUG
|
||||
mem_test (0L, ramsize, 1);
|
||||
#endif
|
||||
/* not yet implemented */
|
||||
return (1);
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
void print_mip405_rev (void)
|
||||
{
|
||||
unsigned char part, vers, cfg, rev;
|
||||
|
||||
cfg = get_board_revcfg ();
|
||||
vers = cfg;
|
||||
vers &= 0xf;
|
||||
rev = (((vers & 0x1) ? 0x8 : 0) |
|
||||
((vers & 0x2) ? 0x4 : 0) |
|
||||
((vers & 0x4) ? 0x2 : 0) | ((vers & 0x8) ? 0x1 : 0));
|
||||
|
||||
part = in8 (PLD_PART_REG);
|
||||
vers = in8 (PLD_VERS_REG);
|
||||
printf ("Rev: MIP405-%d Rev %c PLD%d Vers %d\n",
|
||||
(16 - rev), ((cfg >> 4) & 0xf) + 'A', part, vers);
|
||||
}
|
||||
|
||||
|
||||
int last_stage_init (void)
|
||||
{
|
||||
if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
|
||||
printf ("Error writing to the PHY\n");
|
||||
}
|
||||
print_mip405_rev ();
|
||||
show_stdio_dev ();
|
||||
check_env ();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* some helping routines
|
||||
*/
|
||||
|
||||
int overwrite_console (void)
|
||||
{
|
||||
return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************
|
||||
* Print MIP405 Info
|
||||
************************************************************************/
|
||||
void print_mip405_info (void)
|
||||
{
|
||||
unsigned char part, vers, cfg, irq_reg, com_mode, ext;
|
||||
|
||||
part = in8 (PLD_PART_REG);
|
||||
vers = in8 (PLD_VERS_REG);
|
||||
cfg = in8 (PLD_BOARD_CFG_REG);
|
||||
irq_reg = in8 (PLD_IRQ_REG);
|
||||
com_mode = in8 (PLD_COM_MODE_REG);
|
||||
ext = in8 (PLD_EXT_CONF_REG);
|
||||
|
||||
printf ("PLD Part %d version %d\n", part, vers);
|
||||
printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
|
||||
printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
|
||||
(cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
|
||||
printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
|
||||
printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
|
||||
printf ("Test ist %x\n", com_mode);
|
||||
printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
|
||||
(ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
|
||||
(ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
|
||||
(ext >> 6) & 0x1, (ext >> 7) & 0x1);
|
||||
printf ("SER1 uses handshakes %s\n",
|
||||
(ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
|
||||
printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
|
||||
printf ("IRQs:\n");
|
||||
printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
|
||||
printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
|
||||
printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
|
||||
printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
|
||||
printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
|
||||
printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* hacked for PIP405
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include "pip405.h"
|
||||
#include "../common/common_util.h"
|
||||
|
||||
|
||||
extern void print_pip405_info(void);
|
||||
extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
|
||||
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
int do_pip405(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
|
||||
ulong led_on,led_nr;
|
||||
|
||||
if (strcmp(argv[1], "info") == 0)
|
||||
{
|
||||
print_pip405_info();
|
||||
return 0;
|
||||
}
|
||||
if (strcmp(argv[1], "led") == 0)
|
||||
{
|
||||
led_nr = (ulong)simple_strtoul(argv[2], NULL, 10);
|
||||
led_on = (ulong)simple_strtoul(argv[3], NULL, 10);
|
||||
if(!led_nr)
|
||||
user_led0(led_on);
|
||||
else
|
||||
user_led1(led_on);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return (do_mplcommon(cmdtp, flag, argc, argv));
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
Loading…
Reference in New Issue