Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
Tom Rini
commit
7bcee5f7ee
|
|
@ -464,6 +464,10 @@ Andre Schwarz <andre.schwarz@matrix-vision.de>
|
|||
mvblm7 MPC8343
|
||||
mvsmr MPC5200
|
||||
|
||||
Inderpal Singh <inderpal.singh@linaro.org>
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||||
|
||||
Arndale ARM ARMV7 (EXYNOS5250 SoC)
|
||||
|
||||
Jon Smirl <jonsmirl@gmail.com>
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||||
|
||||
pcm030 MPC5200
|
||||
|
|
|
|||
2
Makefile
2
Makefile
|
|
@ -867,7 +867,7 @@ clean:
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|||
$(obj)tools/gdb/{astest,gdbcont,gdbsend} \
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||||
$(obj)tools/gen_eth_addr $(obj)tools/img2srec \
|
||||
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
|
||||
$(obj)tools/mk{smdk5250,}spl \
|
||||
$(obj)tools/mk{$(BOARD),}spl \
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||||
$(obj)tools/mxsboot \
|
||||
$(obj)tools/ncb $(obj)tools/ubsha1 \
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||||
$(obj)tools/kernel-doc/docproc \
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|
|
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|||
|
|
@ -290,10 +290,19 @@ static inline unsigned int s5p_gpio_part_max(int nr)
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return EXYNOS5_GPIO_PART2_MAX;
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||||
} else if (cpu_is_exynos4()) {
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if (nr < EXYNOS4_GPIO_PART1_MAX)
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return 0;
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||||
else
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||||
return EXYNOS4_GPIO_PART1_MAX;
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||||
if (proid_is_exynos4412()) {
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if (nr < EXYNOS4X12_GPIO_PART1_MAX)
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return 0;
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else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
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return EXYNOS4X12_GPIO_PART1_MAX;
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||||
else
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||||
return EXYNOS4X12_GPIO_PART2_MAX;
|
||||
} else {
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||||
if (nr < EXYNOS4_GPIO_PART1_MAX)
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return 0;
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||||
else
|
||||
return EXYNOS4_GPIO_PART1_MAX;
|
||||
}
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||||
}
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||||
return 0;
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||||
|
|
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|||
|
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@ -8,6 +8,8 @@
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|||
#ifndef __ASM_ARCH_MMC_H_
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#define __ASM_ARCH_MMC_H_
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#define S5P_MMC_DEV_OFFSET 0x10000
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#define SDHCI_CONTROL2 0x80
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#define SDHCI_CONTROL3 0x84
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#define SDHCI_CONTROL4 0x8C
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|
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@ -55,7 +57,9 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width);
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|||
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static inline unsigned int s5p_mmc_init(int index, int bus_width)
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{
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unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
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unsigned int base = samsung_get_base_mmc() +
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(S5P_MMC_DEV_OFFSET * index);
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return s5p_sdhci_init(base, index, bus_width);
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||||
}
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||||
#endif
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|
|
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|
|
@ -8,6 +8,8 @@
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#ifndef __ASM_ARCH_MMC_H_
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||||
#define __ASM_ARCH_MMC_H_
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#define S5P_MMC_DEV_OFFSET 0x100000
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#define SDHCI_CONTROL2 0x80
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#define SDHCI_CONTROL3 0x84
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#define SDHCI_CONTROL4 0x8C
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|
@ -55,7 +57,9 @@ int s5p_sdhci_init(u32 regbase, int index, int bus_width);
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|||
|
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static inline unsigned int s5p_mmc_init(int index, int bus_width)
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{
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unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
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||||
unsigned int base = samsung_get_base_mmc() +
|
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(S5P_MMC_DEV_OFFSET * index);
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|
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return s5p_sdhci_init(base, index, bus_width);
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}
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#endif
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|
|
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@ -0,0 +1,34 @@
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#
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||||
# Copyright (C) 2013 Samsung Electronics
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#
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||||
# SPDX-License-Identifier: GPL-2.0+
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||||
#
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|
||||
include $(TOPDIR)/config.mk
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||||
LIB = $(obj)lib$(BOARD).o
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||||
|
||||
COBJS += arndale_spl.o
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||||
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||||
ifndef CONFIG_SPL_BUILD
|
||||
COBJS += arndale.o
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endif
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||||
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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||||
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
|
||||
|
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ALL := $(obj).depend $(LIB)
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||||
|
||||
all: $(ALL)
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(call cmd_link_o_target, $(OBJS))
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||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
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||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Samsung Electronics
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/pinmux.h>
|
||||
#include <asm/arch/dwmmc.h>
|
||||
#include <asm/arch/power.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
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||||
{
|
||||
int i;
|
||||
u32 addr;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||
addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
|
||||
gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
set_ps_hold_ctrl();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
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||||
int i;
|
||||
u32 addr, size;
|
||||
|
||||
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
||||
addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
|
||||
size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
|
||||
|
||||
gd->bd->bi_dram[i].start = addr;
|
||||
gd->bd->bi_dram[i].size = size;
|
||||
}
|
||||
}
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||||
|
||||
#ifdef CONFIG_GENERIC_MMC
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
/* dwmmc initializattion for available channels */
|
||||
ret = exynos_dwmmc_init(gd->fdt_blob);
|
||||
if (ret)
|
||||
debug("dwmmc init failed\n");
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int board_uart_init(void)
|
||||
{
|
||||
int err = 0, uart_id;
|
||||
|
||||
for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
|
||||
err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
|
||||
if (err) {
|
||||
debug("UART%d not configured\n",
|
||||
(uart_id - PERIPH_ID_UART0));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_EARLY_INIT_F
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
err = board_uart_init();
|
||||
if (err) {
|
||||
debug("UART init failed\n");
|
||||
return err;
|
||||
}
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DISPLAY_BOARDINFO
|
||||
int checkboard(void)
|
||||
{
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||||
printf("\nBoard: Arndale\n");
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||||
|
||||
return 0;
|
||||
}
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||||
#endif
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|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright (c) 2012 The Chromium OS Authors.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
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||||
#include <asm/arch/spl.h>
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||||
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||||
#define SIGNATURE 0xdeadbeef
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||||
|
||||
/* Parameters of early board initialization in SPL */
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||||
static struct spl_machine_param machine_param
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||||
__attribute__((section(".machine_param"))) = {
|
||||
.signature = SIGNATURE,
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||||
.version = 1,
|
||||
.params = "vmubfasirM",
|
||||
.size = sizeof(machine_param),
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|
||||
.mem_iv_size = 0x1f,
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.mem_type = DDR_MODE_DDR3,
|
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||||
/*
|
||||
* Set uboot_size to 0x100000 bytes.
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||||
*
|
||||
* This is an overly conservative value chosen to accommodate all
|
||||
* possible U-Boot image. You are advised to set this value to a
|
||||
* smaller realistic size via scripts that modifies the .machine_param
|
||||
* section of output U-Boot image.
|
||||
*/
|
||||
.uboot_size = 0x100000,
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||||
.boot_source = BOOT_MODE_OM,
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.frequency_mhz = 800,
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.arm_freq_mhz = 1000,
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.serial_base = 0x12c30000,
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.i2c_base = 0x12c60000,
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.mem_manuf = MEM_MANUF_SAMSUNG,
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};
|
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struct spl_machine_param *spl_get_machine_params(void)
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{
|
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if (machine_param.signature != SIGNATURE) {
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||||
/* Will hang if SIGNATURE dont match */
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
return &machine_param;
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* SAMSUNG Arndale board device tree source
|
||||
*
|
||||
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos5250.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SAMSUNG Arndale board based on EXYNOS5250";
|
||||
compatible = "samsung,arndale", "samsung,exynos5250";
|
||||
|
||||
aliases {
|
||||
serial0 = "/serial@12C20000";
|
||||
console = "/serial@12C20000";
|
||||
};
|
||||
|
||||
mmc@12200000 {
|
||||
samsung,bus-width = <8>;
|
||||
samsung,timing = <1 3 3>;
|
||||
};
|
||||
|
||||
mmc@12210000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc@12220000 {
|
||||
samsung,bus-width = <4>;
|
||||
samsung,timing = <1 2 3>;
|
||||
};
|
||||
|
||||
mmc@12230000 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2010 Samsung Electronics
|
||||
# Kyungmin Park <kyungmin.park@samsung.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
# On S5PC100 we use the 128 MiB OneDRAM bank at
|
||||
#
|
||||
# 0x30000000 to 0x35000000 (80MiB)
|
||||
# 0x38000000 to 0x40000000 (128MiB)
|
||||
#
|
||||
# On S5PC110 we use the 128 MiB OneDRAM bank at
|
||||
#
|
||||
# 0x30000000 to 0x35000000 (80MiB)
|
||||
# 0x40000000 to 0x50000000 (256MiB)
|
||||
#
|
||||
CONFIG_SYS_TEXT_BASE = 0x34800000
|
||||
|
|
@ -72,7 +72,7 @@ int checkboard(void)
|
|||
#ifdef CONFIG_GENERIC_MMC
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
int i, ret, ret_sd = 0;
|
||||
|
||||
/* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
|
||||
s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
|
||||
|
|
@ -95,7 +95,36 @@ int board_mmc_init(bd_t *bis)
|
|||
s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
|
||||
}
|
||||
|
||||
return s5p_mmc_init(0, 4);
|
||||
ret = s5p_mmc_init(0, 4);
|
||||
if (ret)
|
||||
error("MMC: Failed to init MMC:0.\n");
|
||||
|
||||
/*
|
||||
* SD card (T_FLASH) detect and init
|
||||
* T_FLASH_DETECT: EINT28: GPH3[4] input mode
|
||||
*/
|
||||
s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
|
||||
s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
|
||||
|
||||
if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
|
||||
for (i = 0; i < 7; i++) {
|
||||
if (i == 2)
|
||||
continue;
|
||||
|
||||
/* GPG2[0:6] special function 2 */
|
||||
s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
|
||||
/* GPG2[0:6] pull disable */
|
||||
s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
|
||||
/* GPG2[0:6] drv 4x */
|
||||
s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
|
||||
}
|
||||
|
||||
ret_sd = s5p_mmc_init(2, 4);
|
||||
if (ret_sd)
|
||||
error("MMC: Failed to init SD card (MMC:2).\n");
|
||||
}
|
||||
|
||||
return ret & ret_sd;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
#
|
||||
# Copyright (C) 2008 # Samsung Elecgtronics
|
||||
# Kyungmin Park <kyungmin.park@samsung.com>
|
||||
#
|
||||
|
||||
# On S5PC100 we use the 128 MiB OneDRAM bank at
|
||||
#
|
||||
# 0x30000000 to 0x35000000 (80MiB)
|
||||
# 0x38000000 to 0x40000000 (128MiB)
|
||||
#
|
||||
# On S5PC110 we use the 128 MiB OneDRAM bank at
|
||||
#
|
||||
# 0x30000000 to 0x35000000 (80MiB)
|
||||
# 0x40000000 to 0x48000000 (128MiB)
|
||||
#
|
||||
CONFIG_SYS_TEXT_BASE = 0x34800000
|
||||
|
|
@ -327,6 +327,7 @@ omap5_uevm arm armv7 omap5_uevm ti oma
|
|||
dra7xx_evm arm armv7 dra7xx ti omap5
|
||||
s5p_goni arm armv7 goni samsung s5pc1xx
|
||||
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
|
||||
arndale arm armv7 arndale samsung exynos
|
||||
origen arm armv7 origen samsung exynos
|
||||
s5pc210_universal arm armv7 universal_c210 samsung exynos
|
||||
snow arm armv7 smdk5250 samsung exynos
|
||||
|
|
|
|||
|
|
@ -14,6 +14,198 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static const char max77686_buck_addr[] = {
|
||||
0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38
|
||||
};
|
||||
|
||||
static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
|
||||
{
|
||||
unsigned int hex = 0;
|
||||
|
||||
switch (ldo) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
case 15:
|
||||
hex = (uV - 800000) / 25000;
|
||||
break;
|
||||
default:
|
||||
hex = (uV - 800000) / 50000;
|
||||
}
|
||||
|
||||
if (hex >= 0 && hex <= MAX77686_LDO_VOLT_MAX_HEX)
|
||||
return hex;
|
||||
|
||||
debug("%s: %ld is wrong voltage value for LDO%d\n", __func__, uV, ldo);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
|
||||
{
|
||||
unsigned int val, ret, hex, adr;
|
||||
|
||||
if (ldo < 1 && ldo > 26) {
|
||||
printf("%s: %d is wrong ldo number\n", __func__, ldo);
|
||||
return -1;
|
||||
}
|
||||
|
||||
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
|
||||
hex = max77686_ldo_volt2hex(ldo, uV);
|
||||
|
||||
if (!hex)
|
||||
return -1;
|
||||
|
||||
ret = pmic_reg_read(p, adr, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val &= ~MAX77686_LDO_VOLT_MASK;
|
||||
val |= hex;
|
||||
ret |= pmic_reg_write(p, adr, val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
|
||||
{
|
||||
unsigned int val, ret, adr, mode;
|
||||
|
||||
if (ldo < 1 && 26 < ldo) {
|
||||
printf("%s: %d is wrong ldo number\n", __func__, ldo);
|
||||
return -1;
|
||||
}
|
||||
|
||||
adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
|
||||
|
||||
/* mode */
|
||||
switch (opmode) {
|
||||
case OPMODE_OFF:
|
||||
mode = MAX77686_LDO_MODE_OFF;
|
||||
break;
|
||||
case OPMODE_STANDBY:
|
||||
switch (ldo) {
|
||||
case 2:
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
case 10:
|
||||
case 11:
|
||||
case 12:
|
||||
case 14:
|
||||
case 15:
|
||||
case 16:
|
||||
mode = MAX77686_LDO_MODE_STANDBY;
|
||||
break;
|
||||
default:
|
||||
mode = 0xff;
|
||||
}
|
||||
break;
|
||||
case OPMODE_LPM:
|
||||
mode = MAX77686_LDO_MODE_LPM;
|
||||
break;
|
||||
case OPMODE_ON:
|
||||
mode = MAX77686_LDO_MODE_ON;
|
||||
break;
|
||||
default:
|
||||
mode = 0xff;
|
||||
}
|
||||
|
||||
if (mode == 0xff) {
|
||||
printf("%s: %d is not supported on LDO%d\n",
|
||||
__func__, opmode, ldo);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret = pmic_reg_read(p, adr, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val &= ~MAX77686_LDO_MODE_MASK;
|
||||
val |= mode;
|
||||
ret |= pmic_reg_write(p, adr, val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
|
||||
{
|
||||
unsigned int val, ret, mask, adr, size, mode, mode_shift;
|
||||
|
||||
size = ARRAY_SIZE(max77686_buck_addr);
|
||||
if (buck >= size) {
|
||||
printf("%s: %d is wrong buck number\n", __func__, buck);
|
||||
return -1;
|
||||
}
|
||||
|
||||
adr = max77686_buck_addr[buck];
|
||||
|
||||
/* mask */
|
||||
switch (buck) {
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
mode_shift = MAX77686_BUCK_MODE_SHIFT_2;
|
||||
break;
|
||||
default:
|
||||
mode_shift = MAX77686_BUCK_MODE_SHIFT_1;
|
||||
}
|
||||
|
||||
mask = MAX77686_BUCK_MODE_MASK << mode_shift;
|
||||
|
||||
/* mode */
|
||||
switch (opmode) {
|
||||
case OPMODE_OFF:
|
||||
mode = MAX77686_BUCK_MODE_OFF;
|
||||
break;
|
||||
case OPMODE_STANDBY:
|
||||
switch (buck) {
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
mode = MAX77686_BUCK_MODE_STANDBY << mode_shift;
|
||||
break;
|
||||
default:
|
||||
mode = 0xff;
|
||||
}
|
||||
break;
|
||||
case OPMODE_LPM:
|
||||
switch (buck) {
|
||||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
mode = MAX77686_BUCK_MODE_LPM << mode_shift;
|
||||
break;
|
||||
default:
|
||||
mode = 0xff;
|
||||
}
|
||||
break;
|
||||
case OPMODE_ON:
|
||||
mode = MAX77686_BUCK_MODE_ON << mode_shift;
|
||||
break;
|
||||
default:
|
||||
mode = 0xff;
|
||||
}
|
||||
|
||||
if (mode == 0xff) {
|
||||
printf("%s: %d is not supported on BUCK%d\n",
|
||||
__func__, opmode, buck);
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret = pmic_reg_read(p, adr, &val);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
val &= ~mask;
|
||||
val |= mode;
|
||||
ret |= pmic_reg_write(p, adr, val);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int pmic_init(unsigned char bus)
|
||||
{
|
||||
static const char name[] = "MAX77686_PMIC";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,255 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Samsung Electronics
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Configuration settings for the SAMSUNG Arndale board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_ARNDALE_H
|
||||
#define __CONFIG_ARNDALE_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* S5P Family */
|
||||
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
|
||||
#define CONFIG_EXYNOS5250
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
/* Enable fdt support for Exynos5250 */
|
||||
#define CONFIG_ARCH_DEVICE_TREE exynos5250
|
||||
#define CONFIG_OF_CONTROL
|
||||
#define CONFIG_OF_SEPARATE
|
||||
|
||||
/* Allow tracing to be enabled */
|
||||
#define CONFIG_TRACE
|
||||
#define CONFIG_CMD_TRACE
|
||||
#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
|
||||
#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
|
||||
#define CONFIG_TRACE_EARLY
|
||||
#define CONFIG_TRACE_EARLY_ADDR 0x50000000
|
||||
|
||||
/* Keep L2 Cache Disabled */
|
||||
#define CONFIG_SYS_DCACHE_OFF
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
#define CONFIG_SYS_TEXT_BASE 0x43E00000
|
||||
|
||||
/* input clock of PLL: SMDK5250 has 24MHz input clock */
|
||||
#define CONFIG_SYS_CLK_FREQ 24000000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/* Power Down Modes */
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
#define S5P_CHECK_DIDLE 0xBAD00000
|
||||
#define S5P_CHECK_LPA 0xABAD0000
|
||||
|
||||
/* Offset for inform registers */
|
||||
#define INFORM0_OFFSET 0x800
|
||||
#define INFORM1_OFFSET 0x804
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
|
||||
|
||||
/* select serial console configuration */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
|
||||
#define CONFIG_SILENT_CONSOLE
|
||||
|
||||
/* Console configuration */
|
||||
#define CONFIG_CONSOLE_MUX
|
||||
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||
#define EXYNOS_DEVICE_SETTINGS \
|
||||
"stdin=serial\0" \
|
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0"
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
EXYNOS_DEVICE_SETTINGS
|
||||
|
||||
/* SD/MMC configuration */
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_SDHCI
|
||||
#define CONFIG_S5P_SDHCI
|
||||
#define CONFIG_DWMMC
|
||||
#define CONFIG_EXYNOS_DWMMC
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT
|
||||
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||
|
||||
/* PWM */
|
||||
#define CONFIG_PWM
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Command definition*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_HASH
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
/* USB */
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_EXYNOS
|
||||
#define CONFIG_USB_STORAGE
|
||||
|
||||
/* MMC SPL */
|
||||
#define CONFIG_SPL
|
||||
#define COPY_BL2_FNPTR_ADDR 0x02020030
|
||||
|
||||
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||
|
||||
/* specific .lds file */
|
||||
#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
|
||||
#define CONFIG_SPL_TEXT_BASE 0x02023400
|
||||
#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
#define CONFIG_SYS_PROMPT "ARNDALE # "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
/* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
#define CONFIG_RD_LVL
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 8
|
||||
#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
|
||||
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
|
||||
#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
|
||||
#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
|
||||
#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
|
||||
#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
|
||||
/* FLASH and environment organization */
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#undef CONFIG_CMD_IMLS
|
||||
#define CONFIG_IDENT_STRING " for ARNDALE"
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SECURE_BL1_ONLY
|
||||
|
||||
/* Secure FW size configuration */
|
||||
#ifdef CONFIG_SECURE_BL1_ONLY
|
||||
#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
|
||||
#else
|
||||
#define CONFIG_SEC_FW_SIZE 0
|
||||
#endif
|
||||
|
||||
/* Configuration of BL1, BL2, ENV Blocks on mmc */
|
||||
#define CONFIG_RES_BLOCK_SIZE (512)
|
||||
#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
|
||||
#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
|
||||
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
|
||||
|
||||
#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
|
||||
#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
|
||||
|
||||
/* U-boot copy size from boot Media to DRAM.*/
|
||||
#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
|
||||
#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
|
||||
|
||||
#define CONFIG_SPI_BOOTING
|
||||
#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
|
||||
#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_EFI_PARTITION
|
||||
#define CONFIG_CMD_PART
|
||||
#define CONFIG_PARTITION_UUIDS
|
||||
|
||||
|
||||
#define CONFIG_IRAM_STACK 0x02050000
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_INIT_BOARD
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_MAX_I2C_NUM 8
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x0
|
||||
#define CONFIG_I2C_EDID
|
||||
|
||||
/* PMIC */
|
||||
#define CONFIG_PMIC
|
||||
#define CONFIG_PMIC_I2C
|
||||
#define CONFIG_PMIC_MAX77686
|
||||
|
||||
#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
|
||||
|
||||
/* Ethernet Controllor Driver */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_BASE 0x5000000
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
#define CONFIG_ENV_SROM_BANK 1
|
||||
#endif /*CONFIG_CMD_NET*/
|
||||
|
||||
/* Enable PXE Support */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_PXE
|
||||
#define CONFIG_MENU
|
||||
#endif
|
||||
|
||||
/* Enable devicetree support */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/* Enable Time Command */
|
||||
#define CONFIG_CMD_TIME
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
@ -13,7 +13,7 @@
|
|||
#define CONFIG_SAMSUNG /* in a SAMSUNG core */
|
||||
#define CONFIG_S5P /* S5P Family */
|
||||
#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
|
||||
#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
|
||||
#define CONFIG_EXYNOS5250
|
||||
|
||||
#include <asm/arch/cpu.h> /* get chip and board defs */
|
||||
|
||||
|
|
|
|||
|
|
@ -29,6 +29,9 @@
|
|||
/* DRAM Base */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x30000000
|
||||
|
||||
/* Text Base */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x34800000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
|
|
|||
|
|
@ -34,6 +34,9 @@
|
|||
/* DRAM Base */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x30000000
|
||||
|
||||
/* Text Base */
|
||||
#define CONFIG_SYS_TEXT_BASE 0x34800000
|
||||
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
|
|
|||
|
|
@ -139,6 +139,32 @@ enum {
|
|||
EN_LDO = (0x3 << 6),
|
||||
};
|
||||
|
||||
enum {
|
||||
OPMODE_OFF = 0,
|
||||
OPMODE_STANDBY,
|
||||
OPMODE_LPM,
|
||||
OPMODE_ON,
|
||||
};
|
||||
|
||||
int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
|
||||
int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
|
||||
int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
|
||||
|
||||
#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
|
||||
#define MAX77686_LDO_VOLT_MASK 0x3f
|
||||
#define MAX77686_LDO_MODE_MASK 0xc0
|
||||
#define MAX77686_LDO_MODE_OFF (0x00 << 0x06)
|
||||
#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
|
||||
#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
|
||||
#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
|
||||
#define MAX77686_BUCK_MODE_MASK 0x03
|
||||
#define MAX77686_BUCK_MODE_SHIFT_1 0x00
|
||||
#define MAX77686_BUCK_MODE_SHIFT_2 0x04
|
||||
#define MAX77686_BUCK_MODE_OFF 0x00
|
||||
#define MAX77686_BUCK_MODE_STANDBY 0x01
|
||||
#define MAX77686_BUCK_MODE_LPM 0x02
|
||||
#define MAX77686_BUCK_MODE_ON 0x03
|
||||
|
||||
/* Buck1 1 volt value */
|
||||
#define MAX77686_BUCK1OUT_1V 0x5
|
||||
/* Buck1 1.05 volt value */
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
|
|||
BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
|
||||
BIN_FILES-y += mkenvimage$(SFX)
|
||||
BIN_FILES-y += mkimage$(SFX)
|
||||
BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
|
||||
BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
|
||||
BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
|
||||
BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
|
||||
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
|
||||
|
|
@ -87,6 +87,7 @@ NOPED_OBJ_FILES-y += ublimage.o
|
|||
OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
|
||||
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
|
||||
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
|
||||
OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o
|
||||
OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
|
||||
OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
|
||||
OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
|
||||
|
|
|
|||
Loading…
Reference in New Issue