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ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0 

DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.

Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.

NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Nishanth Menon 2015-08-13 09:51:00 -05:00 committed by Tom Rini
parent 0358923409
commit 76cff2b108
5 changed files with 19 additions and 0 deletions
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9
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -11,6 +11,7 @@
*/
#include <asm/omap_common.h>
#include <asm/io.h>
struct prcm_regs const omap5_es1_prcm = {
/* cm1.ckgen */
@ -379,6 +380,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.ctrl_core_sma_sw_0 = 0x4A0023FC,
.ctrl_core_sma_sw_1 = 0x4A002534,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
.control_core_mac_id_1_lo = 0x4A00251C,
@ -994,3 +996,10 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l3main1_tptc1_clkctrl = 0x4a008778,
.cm_l3main1_tptc2_clkctrl = 0x4a008780,
};
void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
{
u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
(*ctrl)->ctrl_core_sma_sw_0;
clrsetbits_le32(reg, clear_bits, set_bits);
}

4
arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
View File

@ -49,6 +49,10 @@
#define ISOLATE_IO 1
#define DEISOLATE_IO 0
/* CTRL_CORE_SMA_SW_1 */
#define RGMII2_ID_MODE_N_MASK (1 << 26)
#define RGMII1_ID_MODE_N_MASK (1 << 25)
/* PRM_IO_PMCTRL */
#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0
#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0)

2
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -235,6 +235,8 @@ struct ctrl_ioregs {
u32 ctrl_ddr_ctrl_ext_0;
};
void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
#endif /* __ASSEMBLY__ */
/* Boot parameters */

1
arch/arm/include/asm/omap_common.h
View File

@ -466,6 +466,7 @@ struct omap_sys_ctrl_regs {
u32 control_padconf_wkup_base;
u32 iodelay_config_base;
u32 ctrl_core_sma_sw_0;
u32 ctrl_core_sma_sw_1;
};
struct dpll_params {

3
board/ti/dra7xx/evm.c
View File

@ -104,6 +104,9 @@ void recalibrate_iodelay(void)
npads = ARRAY_SIZE(dra74x_core_padconf_array);
iodelay = dra742_es2_0_iodelay_cfg_array;
niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
/* Setup port1 and port2 for rgmii with 'no-id' mode */
clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
RGMII1_ID_MODE_N_MASK);
break;
}
__recalibrate_iodelay(pads, npads, iodelay, niodelays);