sbc35_a9g20: update board to the new AT91 organization
Cc: Albin Tonnerre <tonnerrealbin@gmail.com> Cc: Gregory Hermant <gregory.hermant@calao-systems.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Reinhard Meyer <u-boot@emk-elektronik.de> Removed SBC35 from MAKEALL
This commit is contained in:
Thomas Petazzoni
Albert ARIBAUD
parent
0cb77bfa7a
commit
6785c7c84a
1
MAKEALL
1
MAKEALL
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@ -446,7 +446,6 @@ LIST_ARMV7=" \
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LIST_at91="$(boards_by_soc at91)\
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at91sam9m10g45ek \
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pm9g45 \
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SBC35_A9G20 \
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TNY_A9260 \
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TNY_A9G20 \
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"
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7
Makefile
7
Makefile
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@ -827,13 +827,6 @@ pm9g45_config : unconfig
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@mkdir -p $(obj)include
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@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
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SBC35_A9G20_NANDFLASH_config \
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SBC35_A9G20_EEPROM_config \
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SBC35_A9G20_config : unconfig
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@mkdir -p $(obj)include
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@echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h
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@$(MKCONFIG) -n $@ -a sbc35_a9g20 arm arm926ejs sbc35_a9g20 calao at91
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TNY_A9G20_NANDFLASH_config \
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TNY_A9G20_EEPROM_config \
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TNY_A9G20_config \
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@ -26,15 +26,14 @@
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*/
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#include <common.h>
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#include <asm/arch/at91sam9260.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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@ -50,33 +49,36 @@ DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_CMD_NAND
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static void sbc35_a9g20_nand_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
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struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
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csa = readl(&matrix->ebicsa);
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csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
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writel(csa, &matrix->ebicsa);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
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AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
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&smc->cs[3].setup);
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writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
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AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
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&smc->cs[3].pulse);
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writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
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&smc->cs[3].cycle);
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writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
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AT91_SMC_MODE_EXNW_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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AT91_SMC_MODE_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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AT91_SMC_MODE_DBW_8 |
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#endif
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AT91_SMC_TDF_(2));
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AT91_SMC_MODE_TDF_CYCLE(2),
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&smc->cs[3].mode);
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
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writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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@ -89,10 +91,13 @@ static void sbc35_a9g20_nand_hw_init(void)
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#ifdef CONFIG_MACB
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static void sbc35_a9g20_macb_hw_init(void)
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{
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unsigned long rstc;
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
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unsigned long erstl;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
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/* Enable EMAC clock */
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writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
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/*
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* Disable pull-up on:
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@ -111,24 +116,23 @@ static void sbc35_a9g20_macb_hw_init(void)
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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&pioa->pudr);
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rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
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erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
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AT91_RSTC_MR_URSTEN, &rstc->mr);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
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;
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
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&rstc->mr);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA14) |
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@ -137,7 +141,7 @@ static void sbc35_a9g20_macb_hw_init(void)
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pin_to_mask(AT91_PIN_PA25) |
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pin_to_mask(AT91_PIN_PA26) |
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pin_to_mask(AT91_PIN_PA28),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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&pioa->puer);
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at91_macb_hw_init();
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}
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@ -150,9 +154,9 @@ int board_init(void)
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gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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at91_serial_hw_init();
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at91_seriald_hw_init();
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sbc35_a9g20_nand_hw_init();
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 4 | 1 << 5);
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@ -166,11 +170,9 @@ int board_init(void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
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return -1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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@ -184,7 +186,7 @@ int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
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rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
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#endif
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return rc;
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}
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@ -102,6 +102,8 @@ at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel
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at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1
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snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260
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snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20
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sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH
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sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM
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cpu9260 arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260
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cpu9260_nand arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,NANDBOOT
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cpu9260_128M arm arm926ejs cpu9260 eukrea at91 cpu9260:CPU9260,CPU9260_128M
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@ -26,54 +26,49 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT91_LEGACY
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/* SoC type is defined in boards.cfg */
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#include <asm/hardware.h>
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#include <asm/sizes.h>
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#if defined(CONFIG_SBC35_A9G20_NANDFLASH) || defined(CONFIG_SBC35_A9G20_EEPROM)
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#define CONFIG_SBC35_A9G20
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#endif
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#define CONFIG_AT91SAM9G20
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#if defined(CONFIG_SBC35_A9G20_NANDFLASH)
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#if defined(CONFIG_SYS_USE_NANDFLASH)
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#define CONFIG_ENV_IS_IN_NAND
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#else
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#define CONFIG_ENV_IS_IN_EEPROM
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#endif
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12.000 MHz crystal */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_ARCH_CPU_INIT
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/*
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* Hardware drivers
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*/
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#define CONFIG_AT91_GPIO 1
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/* GPIO */
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#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
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#define CONFIG_AT91_GPIO
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/* Serial */
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#define CONFIG_ATMEL_USART
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#define CONFIG_USART0
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#undef CONFIG_USART1
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#undef CONFIG_USART2
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#undef CONFIG_USART3
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#define CONFIG_USART_BASE ATMEL_BASE_DBGU
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#define CONFIG_USART_ID ATMEL_ID_SYS
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_BOOTDELAY 3
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE 1
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#define CONFIG_BOOTP_BOOTPATH 1
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#define CONFIG_BOOTP_GATEWAY 1
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#define CONFIG_BOOTP_HOSTNAME 1
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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@ -86,14 +81,16 @@
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#undef CONFIG_CMD_LOADS
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#undef CONFIG_CMD_SOURCE
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#define CONFIG_CMD_PING 1
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#define CONFIG_CMD_DHCP 1
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#define CONFIG_CMD_USB 1
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_USB
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/* SDRAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define PHYS_SDRAM 0x20000000
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#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
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#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
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#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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/* SPI EEPROM */
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#define CONFIG_SPI
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@ -117,7 +114,7 @@
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#define CONFIG_NAND_ATMEL
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8 1
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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@ -129,27 +126,27 @@
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#define CONFIG_SYS_NO_FLASH 1
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/* Ethernet */
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#define CONFIG_MACB 1
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#define CONFIG_RMII 1
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#define CONFIG_NET_MULTI 1
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_NET_MULTI
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_RESET_PHY_R 1
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#define CONFIG_MACB_SEARCH_PHY 1
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#define CONFIG_RESET_PHY_R
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#define CONFIG_MACB_SEARCH_PHY
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/* USB */
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_OHCI_NEW 1
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#define CONFIG_DOS_PARTITION 1
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#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_STORAGE 1
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#define CONFIG_CMD_FAT 1
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_FAT
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#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
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#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END 0x23e00000
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/* Env in EEPROM, bootstrap + u-boot in NAND*/
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@ -172,8 +169,6 @@
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"120M(rootfs),-(other) " \
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"rw rootfstype=jffs2"
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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