From 616396f1dc1a4f4512797e661324fa320e8427c4 Mon Sep 17 00:00:00 2001
From: Holger Hans Peter Freyther <holger@freyther.de>
Date: Wed, 19 Nov 2014 23:52:55 +0100
Subject: [PATCH] Revert 6678cebc09226f9d34fb7e5e0631d0009689918b

For the sysmoBTS we want to easily see the ARM and DSP speed
and the speed of the RAM as well. Invoking bdinfo is annoying
the reason the call was removed is not very clear.

Fixes: SYS#375
---
 arch/arm/mach-davinci/cpu.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index 74c3d5d936..c9621fa9da 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -206,6 +206,38 @@ int set_cpu_clk_info(void)
 	return 0;
 }
 
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+	/* REVISIT fetch and display CPU ID and revision information
+	 * too ... that will matter as more revisions appear.
+	 */
+#if defined(CONFIG_SOC_DM365)
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, ARM_PLLDIV));
+#else
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+#endif
+
+#ifdef DSP_PLLDIV
+	printf(", DSP %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
+#endif
+
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+#if defined(CONFIG_SOC_DM365)
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DDR_PLLDIV)
+				/ 2);
+#else
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
+				/ 2);
+#endif
+	return 0;
+}
+#endif
+
 #endif /* !CONFIG_SOC_DA8XX */
 
 /*