ARM:AM33XX: Added support for AM33xx
This patch adds basic support for AM33xx which is based on ARMV7 Cortex A8 CPU. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Chandan Nath
Albert ARIBAUD
parent
40b95c8956
commit
5655108a82
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@ -0,0 +1,44 @@
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#
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# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed "as is" WITHOUT ANY WARRANTY of any
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# kind, whether express or implied; without even the implied warranty
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# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(SOC).o
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SOBJS := lowlevel_init.o
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COBJS += sys_info.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
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all: $(obj).depend $(LIB)
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$(LIB): $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,72 @@
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/*
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* lowlevel_init.S
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*
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* AM33XX low level initialization.
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* Initial Code by:
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <asm/arch/hardware.h>
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_mark1:
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.word mark1
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_lowlevel_init1:
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.word lowlevel_init
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_s_init_start:
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.word s_init_start
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
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/*****************************************************************************
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* lowlevel_init: - Platform low level init.
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****************************************************************************/
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.globl lowlevel_init
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lowlevel_init:
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/* The link register is saved in ip by start.S */
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mov r6, ip
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/* check if we are already running from RAM */
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ldr r2, _lowlevel_init1
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ldr r3, _TEXT_BASE
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sub r4, r2, r3
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sub r0, pc, r4
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ldr sp, SRAM_STACK
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mark1:
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ldr r5, _mark1
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sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
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sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
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mov r10, #0x0 /* r10 has in_ddr used by s_init() */
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ands r0, r0, #0xC0000000
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/* MSB 2 bits <> 0 then we are in ocmc or DDR */
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cmp r0, #0x80000000
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bne s_init_start
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mov r10, #0x01
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b s_init_start
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s_init_start:
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mov r0, r10 /* passing in_ddr in r0 */
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bl s_init
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/* back to arch calling code */
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mov pc, r6
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/* the literal pools origin */
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.ltorg
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SRAM_STACK:
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/* Place stack at the top */
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.word LOW_LEVEL_SRAM_STACK
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@ -0,0 +1,130 @@
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/*
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* sys_info.c
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*
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* System information functions
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* Derived from Beagle Board and 3430 SDP code by
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* Richard Woodruff <r-woodruff2@ti.com>
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* Syed Mohammed Khasim <khasim@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
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/**
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* get_cpu_rev(void) - extract rev info
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*/
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u32 get_cpu_rev(void)
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{
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u32 id;
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u32 rev;
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id = readl(DEVICE_ID);
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rev = (id >> 28) & 0xff;
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return rev;
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}
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/**
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* get_cpu_type(void) - extract cpu info
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*/
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u32 get_cpu_type(void)
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{
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u32 id = 0;
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u32 partnum;
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id = readl(DEVICE_ID);
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partnum = (id >> 12) & 0xffff;
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return partnum;
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}
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/**
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* get_board_rev() - setup to pass kernel board revision information
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* returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
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*/
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u32 get_board_rev(void)
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{
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return BOARD_REV_ID;
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}
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/**
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* get_device_type(): tell if GP/HS/EMU/TST
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*/
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u32 get_device_type(void)
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{
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int mode;
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mode = readl(&cstat->statusreg) & (DEVICE_MASK);
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return mode >>= 8;
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}
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/**
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* get_sysboot_value(void) - return SYS_BOOT[4:0]
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*/
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u32 get_sysboot_value(void)
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{
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int mode;
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mode = readl(&cstat->statusreg) & (SYSBOOT_MASK);
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return mode;
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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/**
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* Print CPU information
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*/
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int print_cpuinfo(void)
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{
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char *cpu_s, *sec_s;
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int arm_freq, ddr_freq;
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switch (get_cpu_type()) {
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case AM335X:
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cpu_s = "AM335X";
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break;
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default:
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cpu_s = "Unknown cpu type";
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break;
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}
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switch (get_device_type()) {
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case TST_DEVICE:
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sec_s = "TST";
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break;
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case EMU_DEVICE:
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sec_s = "EMU";
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break;
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case HS_DEVICE:
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sec_s = "HS";
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break;
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case GP_DEVICE:
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sec_s = "GP";
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break;
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default:
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sec_s = "?";
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}
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printf("AM%s-%s rev %d\n",
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cpu_s, sec_s, get_cpu_rev());
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/* TODO: Print ARM and DDR frequencies */
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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@ -0,0 +1,218 @@
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/*
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* cpu.h
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*
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* AM33xx specific header file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _AM33XX_CPU_H
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#define _AM33XX_CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#include <asm/arch/hardware.h>
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#define BIT(x) (1 << x)
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#define CL_BIT(x) (0 << x)
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/* Timer register bits */
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#define TCLR_ST BIT(0) /* Start=1 Stop=0 */
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#define TCLR_AR BIT(1) /* Auto reload */
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#define TCLR_PRE BIT(5) /* Pre-scaler enable */
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#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
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#define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
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/* device type */
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#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* cpu-id for AM33XX family */
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#define AM335X 0xB944
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#define DEVICE_ID 0x44E10600
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/* This gives the status of the boot mode pins on the evm */
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#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
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| BIT(3) | BIT(4))
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/* Reset control */
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#ifdef CONFIG_AM335X
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#define PRM_RSTCTRL 0x44E00F00
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#endif
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#define PRM_RSTCTRL_RESET 0x01
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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/* Encapsulating core pll registers */
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struct cm_wkuppll {
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unsigned int wkclkstctrl; /* offset 0x00 */
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unsigned int wkctrlclkctrl; /* offset 0x04 */
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unsigned int resv1[1];
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unsigned int wkl4wkclkctrl; /* offset 0x0c */
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unsigned int resv2[4];
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unsigned int idlestdpllmpu; /* offset 0x20 */
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unsigned int resv3[2];
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unsigned int clkseldpllmpu; /* offset 0x2c */
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unsigned int resv4[1];
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unsigned int idlestdpllddr; /* offset 0x34 */
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unsigned int resv5[2];
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unsigned int clkseldpllddr; /* offset 0x40 */
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unsigned int resv6[4];
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unsigned int clkseldplldisp; /* offset 0x54 */
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unsigned int resv7[1];
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unsigned int idlestdpllcore; /* offset 0x5c */
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unsigned int resv8[2];
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unsigned int clkseldpllcore; /* offset 0x68 */
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unsigned int resv9[1];
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unsigned int idlestdpllper; /* offset 0x70 */
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unsigned int resv10[3];
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unsigned int divm4dpllcore; /* offset 0x80 */
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unsigned int divm5dpllcore; /* offset 0x84 */
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unsigned int clkmoddpllmpu; /* offset 0x88 */
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unsigned int clkmoddpllper; /* offset 0x8c */
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unsigned int clkmoddpllcore; /* offset 0x90 */
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unsigned int clkmoddpllddr; /* offset 0x94 */
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unsigned int clkmoddplldisp; /* offset 0x98 */
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unsigned int clkseldpllper; /* offset 0x9c */
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unsigned int divm2dpllddr; /* offset 0xA0 */
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unsigned int divm2dplldisp; /* offset 0xA4 */
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unsigned int divm2dpllmpu; /* offset 0xA8 */
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unsigned int divm2dpllper; /* offset 0xAC */
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unsigned int resv11[1];
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unsigned int wkup_uart0ctrl; /* offset 0xB4 */
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unsigned int resv12[8];
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unsigned int divm6dpllcore; /* offset 0xD8 */
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};
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/**
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* Encapsulating peripheral functional clocks
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* pll registers
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*/
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struct cm_perpll {
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unsigned int l4lsclkstctrl; /* offset 0x00 */
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unsigned int l3sclkstctrl; /* offset 0x04 */
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unsigned int l4fwclkstctrl; /* offset 0x08 */
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unsigned int l3clkstctrl; /* offset 0x0c */
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unsigned int resv1[6];
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unsigned int emifclkctrl; /* offset 0x28 */
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unsigned int ocmcramclkctrl; /* offset 0x2c */
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unsigned int resv2[12];
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unsigned int l4lsclkctrl; /* offset 0x60 */
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unsigned int l4fwclkctrl; /* offset 0x64 */
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unsigned int resv3[6];
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unsigned int timer2clkctrl; /* offset 0x80 */
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unsigned int resv4[19];
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unsigned int emiffwclkctrl; /* offset 0xD0 */
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unsigned int resv5[2];
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unsigned int l3instrclkctrl; /* offset 0xDC */
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unsigned int l3clkctrl; /* Offset 0xE0 */
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unsigned int resv6[14];
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unsigned int l4hsclkstctrl; /* offset 0x11C */
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unsigned int l4hsclkctrl; /* offset 0x120 */
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};
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/* Encapsulating Display pll registers */
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struct cm_dpll {
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unsigned int resv1[2];
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unsigned int clktimer2clk; /* offset 0x08 */
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};
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/* Watchdog timer registers */
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struct wd_timer {
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unsigned int resv1[4];
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unsigned int wdtwdsc; /* offset 0x010 */
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unsigned int wdtwdst; /* offset 0x014 */
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unsigned int wdtwisr; /* offset 0x018 */
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unsigned int wdtwier; /* offset 0x01C */
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unsigned int wdtwwer; /* offset 0x020 */
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unsigned int wdtwclr; /* offset 0x024 */
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unsigned int wdtwcrr; /* offset 0x028 */
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unsigned int wdtwldr; /* offset 0x02C */
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unsigned int wdtwtgr; /* offset 0x030 */
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unsigned int wdtwwps; /* offset 0x034 */
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unsigned int resv2[3];
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unsigned int wdtwdly; /* offset 0x044 */
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unsigned int wdtwspr; /* offset 0x048 */
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unsigned int resv3[1];
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unsigned int wdtwqeoi; /* offset 0x050 */
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unsigned int wdtwqstar; /* offset 0x054 */
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unsigned int wdtwqsta; /* offset 0x058 */
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unsigned int wdtwqens; /* offset 0x05C */
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unsigned int wdtwqenc; /* offset 0x060 */
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unsigned int resv4[39];
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unsigned int wdt_unfr; /* offset 0x100 */
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};
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/* Timer Registers */
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struct timer_reg {
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unsigned int resv1[4];
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unsigned int tiocpcfgreg; /* offset 0x10 */
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unsigned int resv2[9];
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unsigned int tclrreg; /* offset 0x38 */
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unsigned int tcrrreg; /* offset 0x3C */
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unsigned int tldrreg; /* offset 0x40 */
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unsigned int resv3[4];
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unsigned int tsicrreg; /* offset 0x54 */
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};
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/* Timer 32 bit registers */
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struct gptimer {
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unsigned int tidr; /* offset 0x00 */
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unsigned int res1[0xc];
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unsigned int tiocp_cfg; /* offset 0x10 */
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unsigned int res2[0xc];
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unsigned int tier; /* offset 0x20 */
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unsigned int tistatr; /* offset 0x24 */
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unsigned int tistat; /* offset 0x28 */
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unsigned int tisr; /* offset 0x2c */
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unsigned int tcicr; /* offset 0x30 */
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unsigned int twer; /* offset 0x34 */
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unsigned int tclr; /* offset 0x38 */
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unsigned int tcrr; /* offset 0x3c */
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unsigned int tldr; /* offset 0x40 */
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unsigned int ttgr; /* offset 0x44 */
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unsigned int twpc; /* offset 0x48 */
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unsigned int tmar; /* offset 0x4c */
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unsigned int tcar1; /* offset 0x50 */
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unsigned int tscir; /* offset 0x54 */
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unsigned int tcar2; /* offset 0x58 */
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};
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/* UART Registers */
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struct uart_sys {
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unsigned int resv1[21];
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unsigned int uartsyscfg; /* offset 0x54 */
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unsigned int uartsyssts; /* offset 0x58 */
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};
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/* VTP Registers */
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struct vtp_reg {
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unsigned int vtp0ctrlreg;
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};
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/* Control Status Register */
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struct ctrl_stat {
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unsigned int resv1[16];
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unsigned int statusreg; /* ofset 0x40 */
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};
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void init_timer(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#endif /* _AM33XX_CPU_H */
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@ -0,0 +1,81 @@
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/*
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* hardware.h
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*
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* hardware specific header
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||||
*
|
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __AM33XX_HARDWARE_H
|
||||
#define __AM33XX_HARDWARE_H
|
||||
|
||||
/* Module base addresses */
|
||||
#define LOW_LEVEL_SRAM_STACK 0x4030B7FC
|
||||
#define UART0_BASE 0x44E09000
|
||||
|
||||
/* DM Timer base addresses */
|
||||
#define DM_TIMER0_BASE 0x4802C000
|
||||
#define DM_TIMER1_BASE 0x4802E000
|
||||
#define DM_TIMER2_BASE 0x48040000
|
||||
#define DM_TIMER3_BASE 0x48042000
|
||||
#define DM_TIMER4_BASE 0x48044000
|
||||
#define DM_TIMER5_BASE 0x48046000
|
||||
#define DM_TIMER6_BASE 0x48048000
|
||||
#define DM_TIMER7_BASE 0x4804A000
|
||||
|
||||
/* GPIO Base address */
|
||||
#define GPIO0_BASE 0x48032000
|
||||
#define GPIO1_BASE 0x4804C000
|
||||
#define GPIO2_BASE 0x481AC000
|
||||
|
||||
/* BCH Error Location Module */
|
||||
#define ELM_BASE 0x48080000
|
||||
|
||||
/* Watchdog Timer */
|
||||
#define WDT_BASE 0x44E35000
|
||||
|
||||
/* Control Module Base Address */
|
||||
#define CTRL_BASE 0x44E10000
|
||||
|
||||
/* PRCM Base Address */
|
||||
#define PRCM_BASE 0x44E00000
|
||||
|
||||
/* EMIF Base address */
|
||||
#define EMIF4_0_CFG_BASE 0x4C000000
|
||||
#define EMIF4_1_CFG_BASE 0x4D000000
|
||||
#define DMM_BASE 0x4E000000
|
||||
|
||||
/* PLL related registers */
|
||||
#define CM_PER 0x44E00000
|
||||
#define CM_WKUP 0x44E00400
|
||||
#define CM_DPLL 0x44E00500
|
||||
#define CM_DEVICE 0x44E00700
|
||||
#define CM_CEFUSE 0x44E00A00
|
||||
#define PRM_DEVICE 0x44E00F00
|
||||
|
||||
/* VTP Base address */
|
||||
#define VTP0_CTRL_ADDR 0x44E10E0C
|
||||
|
||||
/* DDR Base address */
|
||||
#define DDR_CTRL_ADDR 0x44E10E04
|
||||
#define DDR_CONTROL_BASE_ADDR 0x44E11404
|
||||
#define DDR_PHY_BASE_ADDR 0x44E12000
|
||||
#define DDR_PHY_BASE_ADDR2 0x44E120A4
|
||||
|
||||
/* UART */
|
||||
#define DEFAULT_UART_BASE UART0_BASE
|
||||
|
||||
#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
|
||||
#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
|
||||
|
||||
#endif /* __AM33XX_HARDWARE_H */
|
||||
Loading…
Reference in New Issue