board/ti/dra7xx: add support for parallel NAND
This patch adds support for x16 NAND device (MT29F2G16AAD) connected to GPMC chip-select[0] on DRA7xx EVM. As GPMC pins are shared by multiple devices, so in addition to this patch following board settings are required for NAND device detection [1]: SW5.9 (GPMC_WPN) = OFF (logic-1) SW5.1 (NAND_BOOTn) = ON (logic-0) /* Active-low */ SW5.2 (NOR_BOOTn) = OFF (logic-1) SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations SW2.1 (SYSBOOT[0]) = ON (logic-1) /* selects NAND Boot */ SW2.2 (SYSBOOT[1]) = OFF (logic-0) /* selects NAND Boot */ SW2.3 (SYSBOOT[2]) = OFF (logic-0) /* selects NAND Boot */ SW2.4 (SYSBOOT[3]) = OFF (logic-0) /* selects NAND Boot */ SW2.5 (SYSBOOT[4]) = ON (logic-1) /* selects NAND Boot */ SW2.6 (SYSBOOT[5]) = ON (logic-1) /* selects NAND Boot */ SW2.7 (SYSBOOT[6]) = OFF (logic-0) /* reserved */ SW2.8 (SYSBOOT[7]) = OFF (logic-0) /* reserved */ SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Addr/Data Muxed */ SW3.5 (SYSBOOT[12])= ON (logic-1) /* device type: Addr/Data Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Following changes are required in board.cfg to enable NAND on J6-EVM:
This commit is contained in:
pekon gupta
Tom Rini
parent
e53ad4b445
commit
54a97d2849
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@ -68,6 +68,33 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
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{VIN2A_D21, (IEN | M3)},
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{VIN2A_D22, (IEN | M3)},
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{VIN2A_D23, (IEN | M3)},
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#ifdef CONFIG_NAND
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/* NAND / NOR pin-mux */
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{GPMC_AD0 , M0 | IEN | PDIS}, /* GPMC_AD0 */
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{GPMC_AD1 , M0 | IEN | PDIS}, /* GPMC_AD1 */
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{GPMC_AD2 , M0 | IEN | PDIS}, /* GPMC_AD2 */
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{GPMC_AD3 , M0 | IEN | PDIS}, /* GPMC_AD3 */
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{GPMC_AD4 , M0 | IEN | PDIS}, /* GPMC_AD4 */
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{GPMC_AD5 , M0 | IEN | PDIS}, /* GPMC_AD5 */
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{GPMC_AD6 , M0 | IEN | PDIS}, /* GPMC_AD6 */
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{GPMC_AD7 , M0 | IEN | PDIS}, /* GPMC_AD7 */
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{GPMC_AD8 , M0 | IEN | PDIS}, /* GPMC_AD8 */
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{GPMC_AD9 , M0 | IEN | PDIS}, /* GPMC_AD9 */
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{GPMC_AD10, M0 | IEN | PDIS}, /* GPMC_AD10 */
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{GPMC_AD11, M0 | IEN | PDIS}, /* GPMC_AD11 */
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{GPMC_AD12, M0 | IEN | PDIS}, /* GPMC_AD12 */
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{GPMC_AD13, M0 | IEN | PDIS}, /* GPMC_AD13 */
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{GPMC_AD14, M0 | IEN | PDIS}, /* GPMC_AD14 */
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{GPMC_AD15, M0 | IEN | PDIS}, /* GPMC_AD15 */
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{GPMC_CS0, M0 | IDIS | PEN | PTU}, /* GPMC chip-select */
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{GPMC_ADVN_ALE, M0 | IDIS | PEN | PTD}, /* GPMC Addr latch */
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{GPMC_OEN_REN, M0 | IDIS | PEN | PTU}, /* GPMC Read enable */
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{GPMC_WEN, M0 | IDIS | PEN | PTU}, /* GPMC Write enable_n */
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{GPMC_BEN0, M0 | IDIS | PEN | PTD}, /* GPMC Byte/Column En */
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{GPMC_WAIT0, M0 | IEN | PEN | PTU}, /* GPMC Wait/Ready */
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/* GPMC_WPN (Write Protect) is controlled by DIP Switch SW10(12) */
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#else
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/* QSPI pin-mux */
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{GPMC_A13, (IEN | PDIS | M1)}, /* QSPI1_RTCLK */
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{GPMC_A14, (IEN | PDIS | M1)}, /* QSPI1_D[3] */
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{GPMC_A15, (IEN | PDIS | M1)}, /* QSPI1_D[2] */
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@ -78,6 +105,7 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
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{GPMC_A4, (IEN | PDIS | M1)}, /* QSPI1_CS3 */
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{GPMC_CS2, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS0 */
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{GPMC_CS3, (IEN | PTU | PDIS | M1)}, /* QSPI1_CS1*/
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#endif /* CONFIG_NAND */
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{USB2_DRVVBUS, (M0 | IEN | FSC) },
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};
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#endif /* _MUX_DATA_DRA7XX_H_ */
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@ -143,4 +143,54 @@
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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/* NAND support */
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#ifdef CONFIG_NAND
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/* NAND: device related configs */
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
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#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
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CONFIG_SYS_NAND_PAGE_SIZE)
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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/* NAND: driver related configs */
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_NAND_OMAP_ELM
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
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10, 11, 12, 13, 14, 15, 16, 17, \
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18, 19, 20, 21, 22, 23, 24, 25, \
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26, 27, 28, 29, 30, 31, 32, 33, \
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34, 35, 36, 37, 38, 39, 40, 41, \
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42, 43, 44, 45, 46, 47, 48, 49, \
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50, 51, 52, 53, 54, 55, 56, 57, }
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 14
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#define MTDIDS_DEFAULT "nand0=nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
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"128k(NAND.SPL)," \
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"128k(NAND.SPL.backup1)," \
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"128k(NAND.SPL.backup2)," \
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"128k(NAND.SPL.backup3)," \
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"256k(NAND.u-boot-spl-os)," \
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"1m(NAND.u-boot)," \
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"128k(NAND.u-boot-env)," \
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"128k(NAND.u-boot-env.backup1)," \
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"8m(NAND.kernel)," \
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"-(NAND.rootfs)"
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
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/* NAND: SPL related configs */
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#ifdef CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_AM33XX_BCH
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#endif
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/* NAND: SPL falcon mode configs */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_CMD_SPL_NAND_OFS 0x00080000 /* os-boot params*/
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#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
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#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
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#endif
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#endif /* !CONFIG_NAND */
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#endif /* __CONFIG_DRA7XX_EVM_H */
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