powerpc/p2041rdb: Add p2041rdb board support
P2041RDB Specification: ----------------------- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Mingkai Hu
Kumar Gala
parent
c518fc0281
commit
4f1d1b7d1e
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#
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# Copyright 2011 Freescale Semiconductor, Inc.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += $(BOARD).o
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COBJS-y += cpld.o
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COBJS-y += ddr.o
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COBJS-y += law.o
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COBJS-y += tlb.o
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COBJS-$(CONFIG_PCI) += pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS))
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clean:
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rm -f $(OBJS) $(SOBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,171 @@
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/**
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* Copyright 2011 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This file provides support for the board-specific CPLD used on some Freescale
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* reference boards.
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*
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* The following macros need to be defined:
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*
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* CPLD_BASE - The virtual address of the base of the CPLD register map
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*
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include "cpld.h"
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static u8 __cpld_read(unsigned int reg)
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{
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void *p = (void *)CPLD_BASE;
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return in_8(p + reg);
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}
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u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
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static void __cpld_write(unsigned int reg, u8 value)
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{
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void *p = (void *)CPLD_BASE;
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out_8(p + reg, value);
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}
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void cpld_write(unsigned int reg, u8 value)
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__attribute__((weak, alias("__cpld_write")));
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/*
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* Reset the board. This honors the por_cfg registers.
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*/
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void __cpld_reset(void)
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{
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CPLD_WRITE(system_rst, 1);
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}
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void cpld_reset(void) __attribute__((weak, alias("__cpld_reset")));
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/**
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* Set the boot bank to the alternate bank
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*/
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void __cpld_set_altbank(void)
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{
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CPLD_WRITE(fbank_sel, 1);
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}
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void cpld_set_altbank(void)
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__attribute__((weak, alias("__cpld_set_altbank")));
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/**
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* Set the boot bank to the default bank
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*/
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void __cpld_clear_altbank(void)
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{
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CPLD_WRITE(fbank_sel, 0);
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}
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void cpld_clear_altbank(void)
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__attribute__((weak, alias("__cpld_clear_altbank")));
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#ifdef DEBUG
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static void cpld_dump_regs(void)
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{
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printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
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printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
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printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver));
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printf("system_rst = 0x%02x\n", CPLD_READ(system_rst));
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printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg));
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printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on));
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printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg));
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printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe));
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printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel));
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printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk));
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printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk));
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printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel));
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printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux));
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printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2)));
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putc('\n');
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}
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#endif
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int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int rc = 0;
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unsigned int i;
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if (argc <= 1)
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return cmd_usage(cmdtp);
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if (strcmp(argv[1], "reset") == 0) {
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if (strcmp(argv[2], "altbank") == 0)
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cpld_set_altbank();
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else
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cpld_clear_altbank();
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cpld_reset();
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} else if (strcmp(argv[1], "watchdog") == 0) {
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static char *period[8] = {"1ms", "10ms", "30ms", "disable",
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"100ms", "1s", "10s", "60s"};
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for (i = 0; i < ARRAY_SIZE(period); i++) {
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if (strcmp(argv[2], period[i]) == 0)
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CPLD_WRITE(wd_cfg, i);
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}
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} else if (strcmp(argv[1], "lane_mux") == 0) {
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u32 lane = simple_strtoul(argv[2], NULL, 16);
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u8 val = (u8)simple_strtoul(argv[3], NULL, 16);
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u8 reg = CPLD_READ(serdes_mux);
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switch (lane) {
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case 0x6:
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reg &= ~SERDES_MUX_LANE_6_MASK;
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reg |= val << SERDES_MUX_LANE_6_SHIFT;
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break;
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case 0xa:
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reg &= ~SERDES_MUX_LANE_A_MASK;
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reg |= val << SERDES_MUX_LANE_A_SHIFT;
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break;
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case 0xc:
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reg &= ~SERDES_MUX_LANE_C_MASK;
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reg |= val << SERDES_MUX_LANE_C_SHIFT;
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break;
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case 0xd:
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reg &= ~SERDES_MUX_LANE_D_MASK;
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reg |= val << SERDES_MUX_LANE_D_SHIFT;
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break;
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default:
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printf("Invalid value\n");
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break;
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}
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CPLD_WRITE(serdes_mux, reg);
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#ifdef DEBUG
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} else if (strcmp(argv[1], "dump") == 0) {
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cpld_dump_regs();
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#endif
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} else
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rc = cmd_usage(cmdtp);
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return rc;
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}
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U_BOOT_CMD(
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cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd,
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"Reset the board or pin mulexing selection using the CPLD sequencer",
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"reset - hard reset to default bank\n"
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"cpld_cmd reset altbank - reset to alternate bank\n"
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"cpld_cmd watchdog <watchdog_period> - set the watchdog period\n"
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" period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n"
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"cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n"
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" lane 6: 0 -> slot1 (Default)\n"
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" 1 -> SGMII\n"
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" lane a: 0 -> slot2 (Default)\n"
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" 1 -> AURORA\n"
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" lane c: 0 -> slot2 (Default)\n"
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" 1 -> SATA0\n"
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" lane d: 0 -> slot2 (Default)\n"
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" 1 -> SATA1\n"
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#ifdef DEBUG
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"cpld_cmd dump - display the CPLD registers\n"
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#endif
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);
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/**
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* Copyright 2011 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
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*/
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typedef struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */
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u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
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u8 por_cfg; /* 0x6 - POR Control Register */
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u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
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u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
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u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
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u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
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u8 fbank_sel; /* 0xb - Flash bank selection */
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u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
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u8 sw[1]; /* 0xd - SW2 Status */
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} __attribute__ ((packed)) cpld_data_t;
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#define SERDES_MUX_LANE_6_MASK 0x2
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#define SERDES_MUX_LANE_6_SHIFT 1
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#define SERDES_MUX_LANE_A_MASK 0x1
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#define SERDES_MUX_LANE_A_SHIFT 0
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#define SERDES_MUX_LANE_C_MASK 0x4
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#define SERDES_MUX_LANE_C_SHIFT 2
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#define SERDES_MUX_LANE_D_MASK 0x8
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#define SERDES_MUX_LANE_D_SHIFT 3
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/* Pointer to the CPLD register set */
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#define cpld ((cpld_data_t *)CPLD_BASE)
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/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
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#define CPLD_SW(x) (cpld->sw[(x) - 2])
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
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#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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typedef struct {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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} board_specific_parameters_t;
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/*
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* ranges for parameters:
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* wr_data_delay = 0-6
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* clk adjust = 0-8
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* cpo 2-0x1E (30)
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*/
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const board_specific_parameters_t board_specific_parameters[] = {
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/*
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* memory controller 0
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* lo| hi| num| clk| wrlvl | cpo |wrdata|2T
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* mhz| mhz|ranks|adjst| start | delay|
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*/
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{ 1017, 1116, 2, 4, 6, 0xff, 2, 0},
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&board_specific_parameters[0];
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u32 num_params = ARRAY_SIZE(board_specific_parameters);
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u32 i;
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ulong ddr_freq;
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high &&
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pdimm[0].n_ranks == pbsp->n_ranks) {
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->twoT_en = pbsp->force_2T;
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break;
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}
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pbsp++;
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}
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if (i == num_params) {
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printf("Warning: board specific timing not found "
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"for data rate %lu MT/s!\n", ddr_freq);
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/* Write leveling override */
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/* Rtt and Rtt_WR override */
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 60 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing....");
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if (fsl_use_spd()) {
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puts("using SPD\n");
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dram_size = fsl_ddr_sdram();
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} else {
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puts("no SPD and fixed parameters\n");
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return dram_size;
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}
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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@ -0,0 +1,37 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
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#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
|
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
|
||||
SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_portals.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
|
||||
extern void pci_of_setup(void *blob, bd_t *bd);
|
||||
|
||||
#include "cpld.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
u8 sw;
|
||||
struct cpu_type *cpu = gd->cpu;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
unsigned int i;
|
||||
|
||||
printf("Board: %sRDB, ", cpu->name);
|
||||
printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
|
||||
CPLD_READ(cpld_ver_sub));
|
||||
|
||||
sw = CPLD_READ(fbank_sel);
|
||||
printf("vBank: %d\n", sw & 0x1);
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
puts("36-bit Addressing\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Display the RCW, so that no one gets confused as to what RCW
|
||||
* we're actually using for this boot.
|
||||
*/
|
||||
puts("Reset Configuration Word (RCW):");
|
||||
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
|
||||
u32 rcw = in_be32(&gur->rcwsr[i]);
|
||||
|
||||
if ((i % 4) == 0)
|
||||
printf("\n %08x:", i * 4);
|
||||
printf(" %08x", rcw);
|
||||
}
|
||||
puts("\n");
|
||||
|
||||
/*
|
||||
* Display the actual SERDES reference clocks as configured by the
|
||||
* dip switches on the board. Note that the SWx registers could
|
||||
* technically be set to force the reference clocks to match the
|
||||
* values that the SERDES expects (or vice versa). For now, however,
|
||||
* we just display both values and hope the user notices when they
|
||||
* don't match.
|
||||
*/
|
||||
puts("SERDES Reference Clocks: ");
|
||||
sw = in_8(&CPLD_SW(2)) >> 2;
|
||||
for (i = 0; i < 2; i++) {
|
||||
static const char * const freq[] = {"0", "100", "125"};
|
||||
unsigned int clock = (sw >> (2 * i)) & 3;
|
||||
|
||||
printf("Bank%u=%sMhz ", i+1, freq[clock]);
|
||||
}
|
||||
puts("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
|
||||
setbits_be32(&gur->ddrclkdr, 0x000f000f);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
||||
|
||||
set_liodns();
|
||||
setup_portals();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const char *serdes_clock_to_string(u32 clock)
|
||||
{
|
||||
switch (clock) {
|
||||
case SRDS_PLLCR0_RFCK_SEL_100:
|
||||
return "100";
|
||||
case SRDS_PLLCR0_RFCK_SEL_125:
|
||||
return "125";
|
||||
case SRDS_PLLCR0_RFCK_SEL_156_25:
|
||||
return "156.25";
|
||||
default:
|
||||
return "150";
|
||||
}
|
||||
}
|
||||
|
||||
#define NUM_SRDS_BANKS 2
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
u32 actual[NUM_SRDS_BANKS];
|
||||
unsigned int i;
|
||||
u8 sw;
|
||||
|
||||
sw = in_8(&CPLD_SW(2)) >> 2;
|
||||
for (i = 0; i < NUM_SRDS_BANKS; i++) {
|
||||
unsigned int clock = (sw >> (2 * i)) & 3;
|
||||
switch (clock) {
|
||||
case 1:
|
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
|
||||
break;
|
||||
case 2:
|
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
|
||||
break;
|
||||
default:
|
||||
printf("Warning: SDREFCLK%u switch setting of '11' is "
|
||||
"unsupported\n", i + 1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_SRDS_BANKS; i++) {
|
||||
u32 expected = in_be32(®s->bank[i].pllcr0);
|
||||
expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
|
||||
if (expected != actual[i]) {
|
||||
printf("Warning: SERDES bank %u expects reference clock"
|
||||
" %sMHz, but actual is %sMHz\n", i + 1,
|
||||
serdes_clock_to_string(expected),
|
||||
serdes_clock_to_string(actual[i]));
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
pci_of_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
fdt_fixup_liodn(blob);
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
FT_FSL_PCI_SETUP;
|
||||
}
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
|
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
|
||||
* SRAM is at 0xfff00000, it covered the 0xfffff000.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_1M, 1),
|
||||
#else
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/* *I*G* - Flash, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
|
||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* Bman/Qman */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 9, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
|
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 11, BOOKE_PAGESZ_1M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
|
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 12, BOOKE_PAGESZ_1M, 1),
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 13, BOOKE_PAGESZ_4M, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -597,6 +597,9 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca
|
|||
P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND
|
||||
P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
|
||||
P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
|
||||
P2041RDB powerpc mpc85xx p2041rdb freescale
|
||||
P2041RDB_SDCARD powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
||||
P2041RDB_SPIFLASH powerpc mpc85xx p2041rdb freescale - P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
|
||||
P3041DS powerpc mpc85xx corenet_ds freescale
|
||||
P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
|
||||
P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
|
||||
|
|
|
|||
|
|
@ -0,0 +1,123 @@
|
|||
Overview
|
||||
=========
|
||||
The P2041 Processor combines four Power Architecture processor cores
|
||||
with high-performance datapath acceleration architecture(DPAA), CoreNet
|
||||
fabric infrastructure, as well as network and peripheral bus interfaces
|
||||
required for networking, telecom/datacom, wireless infrastructure, and
|
||||
military/aerospace applications.
|
||||
|
||||
P2041RDB board is a quad core platform supporting the P2041 processor
|
||||
of QorIQ DPAA series.
|
||||
|
||||
Boot from NOR flash
|
||||
===================
|
||||
1. Build image
|
||||
make P2041RDB_config
|
||||
make all
|
||||
|
||||
2. Program image
|
||||
=> tftp 1000000 u-boot.bin
|
||||
=> protect off all
|
||||
=> erase eff80000 efffffff
|
||||
=> cp.b 1000000 eff80000 80000
|
||||
|
||||
3. Program RCW
|
||||
=> tftp 1000000 rcw.bin
|
||||
=> protect off all
|
||||
=> erase e8000000 e801ffff
|
||||
=> cp.b 1000000 e8000000 50
|
||||
|
||||
4. Program FMAN Firmware ucode
|
||||
=> tftp 1000000 ucode.bin
|
||||
=> protect off all
|
||||
=> erase ef000000 ef0fffff
|
||||
=> cp.b 1000000 ef000000 2000
|
||||
|
||||
5. Change DIP-switch
|
||||
SW1[1-5] = 10110
|
||||
Note: 1 stands for 'on', 0 stands for 'off'
|
||||
|
||||
Boot from SDCard
|
||||
===================
|
||||
1. Build image
|
||||
make P2041RDB_SDCARD_config
|
||||
make all
|
||||
|
||||
2. Generate PBL imge
|
||||
Use PE tool to produce a image used to be programed to
|
||||
SDCard which contains RCW and U-Boot image.
|
||||
|
||||
3. Program the PBL image to SDCard
|
||||
=> tftp 1000000 pbl_sd.bin
|
||||
=> mmcinfo
|
||||
=> mmc write 1000000 8 441
|
||||
|
||||
4. Program FMAN Firmware ucode
|
||||
=> tftp 1000000 ucode.bin
|
||||
=> mmc write 1000000 46a 10
|
||||
|
||||
5. Change DIP-switch
|
||||
SW1[1-5] = 01100
|
||||
Note: 1 stands for 'on', 0 stands for 'off'
|
||||
|
||||
Boot from SPI flash
|
||||
===================
|
||||
1. Build image
|
||||
make P2041RDB_SPIFLASH_config
|
||||
make all
|
||||
|
||||
2. Generate PBL imge
|
||||
Use PE tool to produce a image used to be programed to
|
||||
SPI flash which contains RCW and U-Boot image.
|
||||
|
||||
3. Program the PBL image to SPI flash
|
||||
=> tftp 1000000 pbl_spi.bin
|
||||
=> spi probe 0
|
||||
=> sf erase 0 100000
|
||||
=> sf write 1000000 0 $filesize
|
||||
|
||||
4. Program FMAN Firmware ucode
|
||||
=> tftp 1000000 ucode.bin
|
||||
=> sf erase 110000 10000
|
||||
=> sf write 1000000 110000 $filesize
|
||||
|
||||
5. Change DIP-switch
|
||||
SW1[1-5] = 10100
|
||||
Note: 1 stands for 'on', 0 stands for 'off'
|
||||
|
||||
CPLD command
|
||||
============
|
||||
The CPLD is used to control the power sequence and some serdes lane
|
||||
mux function.
|
||||
|
||||
cpld reset - hard reset to default bank
|
||||
cpld reset altbank - reset to alternate bank
|
||||
cpld lane_mux <lane> <mux_value> - set multiplexed lane pin
|
||||
lane 6: 0 -> slot1 (Default)
|
||||
1 -> SGMII
|
||||
lane a: 0 -> slot2 (Default)
|
||||
1 -> AURORA
|
||||
lane c: 0 -> slot2 (Default)
|
||||
1 -> SATA0
|
||||
lane d: 0 -> slot2 (Default)
|
||||
1 -> SATA1
|
||||
|
||||
Using the Device Tree Source File
|
||||
=================================
|
||||
To create the DTB (Device Tree Binary) image file, use a command
|
||||
similar to this:
|
||||
dtc -O dtb -b 0 -p 1024 p2041rdb.dts > p2041rdb.dtb
|
||||
|
||||
Or use the following command:
|
||||
{linux-2.6}/make p2041rdb.dtb ARCH=powerpc
|
||||
|
||||
then the dtb file will be generated under the following directory:
|
||||
{linux-2.6}/arch/powerpc/boot/p2041rdb.dtb
|
||||
|
||||
Booting Linux
|
||||
=============
|
||||
Place a linux uImage in the TFTP disk area.
|
||||
tftp 1000000 uImage
|
||||
tftp 2000000 rootfs.ext2.gz.uboot
|
||||
tftp 3000000 p2041rdb.dtb
|
||||
bootm 1000000 2000000 3000000
|
||||
|
|
@ -0,0 +1,624 @@
|
|||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* P2041 RDB board configuration file
|
||||
*
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_P2041RDB
|
||||
#define CONFIG_PHYS_64BIT
|
||||
#define CONFIG_PPC_P2041
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_E500MC /* BOOKE e500mc family */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
|
||||
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
||||
#define CONFIG_MP /* support multiple processors */
|
||||
|
||||
#ifndef CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0xeff80000
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||
#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
|
||||
#define CONFIG_PCI /* Enable PCI/PCIE */
|
||||
#define CONFIG_PCIE1 /* PCIE controler 1 */
|
||||
#define CONFIG_PCIE2 /* PCIE controler 2 */
|
||||
#define CONFIG_PCIE3 /* PCIE controler 3 */
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_SYS_SRIO
|
||||
#define CONFIG_SRIO1 /* SRIO port 1 */
|
||||
#define CONFIG_SRIO2 /* SRIO port 2 */
|
||||
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#else
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SPI_BUS 0
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 10000000
|
||||
#define CONFIG_ENV_SPI_MODE 0
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||
#define CONFIG_ENV_IS_IN_MMC
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_OFFSET (512 * 1097)
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
|
||||
- CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x00400000
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
|
||||
CONFIG_RAMBOOT_TEXT_BASE)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
|
||||
#endif
|
||||
#define CONFIG_SYS_L3_SIZE (1024 << 10)
|
||||
#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
|
||||
#endif
|
||||
/* PQII uses CONFIG_SYS_IMMR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
#endif
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
#define CONFIG_FSL_DDR3
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x52
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
|
||||
/* Set the local bus clock 1/8 of platform clock */
|
||||
#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
|
||||
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
|
||||
|
||||
#define CONFIG_FSL_CPLD
|
||||
#define CPLD_BASE 0xffdf0000 /* CPLD registers */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CPLD_BASE_PHYS 0xfffdf0000ull
|
||||
#else
|
||||
#define CPLD_BASE_PHYS CPLD_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
|
||||
#define PIXIS_LBMAP_SWITCH 7
|
||||
#define PIXIS_LBMAP_MASK 0xf0
|
||||
#define PIXIS_LBMAP_SHIFT 4
|
||||
#define PIXIS_LBMAP_ALTBANK 0x40
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
|
||||
#define CONFIG_MISC_INIT_R
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
/* new uImage format support */
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_I2C_CMD_TREE
|
||||
#define CONFIG_SYS_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_I2C2_OFFSET 0x118100
|
||||
|
||||
/*
|
||||
* RapidIO
|
||||
*/
|
||||
#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
|
||||
|
||||
#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
#define CONFIG_FSL_ESPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_SPEED 10000000
|
||||
#define CONFIG_SF_DEFAULT_MODE 0
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* Qman/Bman */
|
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
|
||||
#else
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
|
||||
#endif
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
#define CONFIG_SYS_FMAN_FW
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
||||
* env, so we got 0x110000.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 545KB (1089 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
|
||||
*/
|
||||
#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130)
|
||||
#elif defined(CONFIG_NAND)
|
||||
#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000
|
||||
#endif
|
||||
#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH)
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_E1000
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
|
||||
#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
|
||||
#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
|
||||
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
|
||||
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
|
||||
|
||||
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
|
||||
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
|
||||
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
|
||||
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
|
||||
|
||||
#define CONFIG_SYS_TBIPA_VALUE 8
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_ERRATA
|
||||
#define CONFIG_CMD_GREPENV
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_NET
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_CMD_EXT2
|
||||
|
||||
#define CONFIG_MMC
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define __USB_PHY_TYPE utmi
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
||||
"bank_intlv=cs0_cs1\0" \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
|
||||
"usb_dr_mode=host\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"c=ffe\0"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue