Add PCI support for MPC8250 Boards (PM825 module)
This commit is contained in:
wdenk
parent
44e5c5c4f1
commit
4d75a504d0
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@ -2,6 +2,8 @@
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Changes since U-Boot 0.2.2:
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======================================================================
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* Add PCI support for MPC8250 Boards (PM825 module)
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* Patch by Stefan Roese, 25 Mar 2003:
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- PCI405 update.
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@ -24,6 +24,7 @@
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <pci.h>
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/*
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* I/O Port configuration table
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@ -349,3 +350,12 @@ void doc_init (void)
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doc_probe (CFG_DOC_BASE);
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}
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#endif
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struct pci_controller hose;
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extern void pci_mpc8250_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc8250_init(&hose);
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}
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@ -50,6 +50,7 @@ static void print_num(const char *, ulong);
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#ifndef CONFIG_ARM /* PowerPC and other */
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#ifdef CONFIG_PPC
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static void print_str(const char *, const char *);
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int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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@ -110,6 +111,34 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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return 0;
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}
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#else /* MIPS */
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int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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DECLARE_GLOBAL_DATA_PTR;
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int i;
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bd_t *bd = gd->bd;
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print_num ("boot_params", (ulong)bd->bi_boot_params);
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print_num ("memstart", (ulong)bd->bi_memstart);
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print_num ("memsize", (ulong)bd->bi_memsize);
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print_num ("flashstart", (ulong)bd->bi_flashstart);
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print_num ("flashsize", (ulong)bd->bi_flashsize);
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print_num ("flashoffset", (ulong)bd->bi_flashoffset);
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printf ("ethaddr =");
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for (i=0; i<6; ++i) {
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printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
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}
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printf ("\nip_addr = ");
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print_IPaddr (bd->bi_ip_addr);
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printf ("\nbaudrate = %d bps\n", bd->bi_baudrate);
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return 0;
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}
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#endif /* MIPS */
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#else /* ARM */
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int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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@ -150,12 +179,12 @@ static void print_num(const char *name, ulong value)
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printf ("%-12s= 0x%08lX\n", name, value);
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}
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#ifndef CONFIG_ARM
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#ifdef CONFIG_PPC
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static void print_str(const char *name, const char *str)
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{
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printf ("%-12s= %6s MHz\n", name, str);
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}
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#endif /* CONFIG_ARM */
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#endif /* CONFIG_PPC */
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#endif /* CFG_CMD_BDI */
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@ -28,7 +28,7 @@ LIB = lib$(CPU).a
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START = start.o kgdb.o
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OBJS = traps.o serial_smc.o serial_scc.o cpu.o cpu_init.o speed.o \
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interrupts.o ether_scc.o ether_fcc.o i2c.o commproc.o \
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bedbug_603e.o status_led.o
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bedbug_603e.o status_led.o pci.o
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all: .depend $(START) $(LIB)
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@ -0,0 +1,244 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CONFIG_PCI
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#include <pci.h>
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#include <asm/m8260_pci.h>
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/*
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* Local->PCI map (from CPU) controlled by
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* MPC826x master window
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*
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* 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
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*
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* 0x80000000 - 0x8FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
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* 0x90000000 - 0x9FFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
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* 0xA0000000 - 0xAFFFFFFF 32-bit PCI IO (Outbound ATU #3)
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*
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* PCI->Local map (from PCI)
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* MPC826x slave window controlled by
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*
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* 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
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*/
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/*
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* Slave window that allows PCI masters to access MPC826x local memory.
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* This window is set up using the first set of Inbound ATU registers
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*/
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#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
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#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
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#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
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PICMR_PREFETCH_EN)
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/*
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* This is the window that allows the CPU to access PCI address space.
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* It will be setup with the SIU PCIBR0 register. All three PCI master
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* windows, which allow the CPU to access PCI prefetch, non prefetch,
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* and IO space (see below), must all fit within this window.
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*/
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#define PCI_MSTR_LOCAL 0x80000000 /* Local base */
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#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
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/*
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* Master window that allows the CPU to access PCI Memory (prefetch).
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* This window will be setup with the first set of Outbound ATU registers
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* in the bridge.
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*/
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#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
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#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
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#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
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#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
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#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
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/*
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* Master window that allows the CPU to access PCI Memory (non-prefetch).
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* This window will be setup with the second set of Outbound ATU registers
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* in the bridge.
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*/
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#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
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#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
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#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
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#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256MB */
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#define POCMR1_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE)
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/*
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* Master window that allows the CPU to access PCI IO space.
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* This window will be setup with the third set of Outbound ATU registers
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* in the bridge.
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*/
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#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
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#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
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#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
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#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
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#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
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/* PCI bus configuration registers.
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*/
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#define PCI_CLASS_BRIDGE_CTLR 0x06
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static inline void pci_outl(u32 addr, u32 data)
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{
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*(volatile u32 *) addr = cpu_to_le32(data);
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}
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void pci_mpc8250_init(struct pci_controller *hose)
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{
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u16 tempShort;
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u32 immr_addr = CFG_IMMR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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pci_dev_t host_devno = PCI_BDF(0, 0, 0);
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pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
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CFG_IMMR + PCI_CFG_DATA_REG);
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/*
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* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
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* and local bus for PCI (SIUMCR [LBPC]).
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*/
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immap->im_siu_conf.sc_siumcr = 0x00640000;
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/* Make PCI lowest priority */
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/* Each 4 bits is a device bus request and the MS 4bits
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is highest priority */
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/* Bus 4bit value
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--- ----------
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CPM high 0b0000
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CPM middle 0b0001
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CPM low 0b0010
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PCI reguest 0b0011
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Reserved 0b0100
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Reserved 0b0101
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Internal Core 0b0110
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External Master 1 0b0111
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External Master 2 0b1000
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External Master 3 0b1001
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The rest are reserved */
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immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
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/* Park bus on core while modifying PCI Bus accesses */
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immap->im_siu_conf.sc_ppc_acr = 0x6;
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/*
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* Set up master window that allows the CPU to access PCI space. This
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* window is set up using the first SIU PCIBR registers.
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*/
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*(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
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*(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
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PCI_MSTR_LOCAL | PCIBR_ENABLE;
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/* Release PCI RST (by default the PCI RST signal is held low) */
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pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
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/* give it some time */
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udelay(1000);
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/*
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* Set up master window that allows the CPU to access PCI Memory (prefetch)
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* space. This window is set up using the first set of Outbound ATU registers.
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*/
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pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12); /* PCI base */
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pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
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pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB); /* Size & attribute */
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/*
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* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
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* space. This window is set up using the second set of Outbound ATU registers.
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*/
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pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
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pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
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pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB); /* Size & attribute */
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/*
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* Set up master window that allows the CPU to access PCI IO space. This window
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* is set up using the third set of Outbound ATU registers.
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*/
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pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12); /* PCI base */
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pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12); /* Local base */
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pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB); /* Size & attribute */
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/*
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* Set up slave window that allows PCI masters to access MPC826x local memory.
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* This window is set up using the first set of Inbound ATU registers
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*/
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pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12); /* Local base */
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pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12); /* PCI base */
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pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB); /* Size & attribute */
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/* See above for description - puts PCI request as highest priority */
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immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
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/* Park the bus on the PCI */
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immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
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/* Host mode - specify the bridge as a host-PCI bridge */
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pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
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PCI_CLASS_BRIDGE_CTLR);
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/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
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pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
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pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
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tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* System memory space */
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pci_set_region(hose->regions + 0,
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CFG_SDRAM_BASE,
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CFG_SDRAM_BASE,
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0x4000000,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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PCI_MSTR_MEM_BUS,
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PCI_MSTR_MEM_LOCAL,
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PCI_MSTR_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region(hose->regions + 2,
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PCI_MSTR_IO_BUS,
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PCI_MSTR_IO_LOCAL,
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PCI_MSTR_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCI */
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@ -21,6 +21,18 @@
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#define cfg_read(val, addr, type, op) *val = op((type)(addr))
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
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#ifdef CONFIG_PM826
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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out_le32(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000); \
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sync(); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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return 0; \
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}
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#else
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#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
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static int \
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indirect_##rw##_config_##size(struct pci_controller *hose, \
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@ -30,6 +42,7 @@ indirect_##rw##_config_##size(struct pci_controller *hose, \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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return 0; \
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}
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#endif
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#define INDIRECT_PCI_OP_ERRATA6(rw, size, type, op, mask) \
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static int \
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@ -25,19 +25,17 @@
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#define _U_BOOT_H_ 1
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typedef struct bd_info {
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int bi_baudrate; /* serial console baudrate */
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unsigned long bi_ip_addr; /* IP Address */
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unsigned char bi_enetaddr[6]; /* Ethernet adress */
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struct environment_s *bi_env;
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ulong bi_arch_number; /* unique id for this board */
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ulong bi_boot_params; /* where this board expects params */
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struct /* RAM configuration */
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{
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ulong start;
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ulong size;
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} bi_dram[CONFIG_NR_DRAM_BANKS];
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int bi_baudrate; /* serial console baudrate */
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unsigned long bi_ip_addr; /* IP Address */
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unsigned char bi_enetaddr[6]; /* Ethernet adress */
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unsigned long bi_arch_number; /* unique id for this board */
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unsigned long bi_boot_params; /* where this board expects params */
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unsigned long bi_memstart; /* start of DRAM memory */
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unsigned long bi_memsize; /* size of DRAM memory in bytes */
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unsigned long bi_flashstart; /* start of FLASH memory */
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unsigned long bi_flashsize; /* size of FLASH memory */
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unsigned long bi_flashoffset; /* reserved area for startup monitor */
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} bd_t;
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#define bi_env_data bi_env->data
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#define bi_env_crc bi_env->crc
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@ -0,0 +1,166 @@
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#ifndef _PPC_KERNEL_M8260_PCI_H
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#define _PPC_KERNEL_M8260_PCI_H
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#define M8265_PCIBR0 0x101ac
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#define M8265_PCIBR1 0x101b0
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#define M8265_PCIMSK0 0x101c4
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#define M8265_PCIMSK1 0x101c8
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/* Bit definitions for PCIBR registers */
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#define PCIBR_ENABLE 0x00000001
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/* Bit definitions for PCIMSK registers */
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#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */
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#define PCIMSK_64KB 0xFFFF0000
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#define PCIMSK_128KB 0xFFFE0000
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#define PCIMSK_256KB 0xFFFC0000
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#define PCIMSK_512KB 0xFFF80000
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#define PCIMSK_1MB 0xFFF00000
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#define PCIMSK_2MB 0xFFE00000
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#define PCIMSK_4MB 0xFFC00000
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#define PCIMSK_8MB 0xFF800000
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#define PCIMSK_16MB 0xFF000000
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#define PCIMSK_32MB 0xFE000000
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#define PCIMSK_64MB 0xFC000000
|
||||
#define PCIMSK_128MB 0xF8000000
|
||||
#define PCIMSK_256MB 0xF0000000
|
||||
#define PCIMSK_512MB 0xE0000000
|
||||
#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */
|
||||
|
||||
|
||||
#define M826X_SCCR_PCI_MODE_EN 0x100
|
||||
|
||||
|
||||
/*
|
||||
* Outbound ATU registers (3 sets). These registers control how 60x bus (local)
|
||||
* addresses are translated to PCI addresses when the MPC826x is a PCI bus
|
||||
* master (initiator).
|
||||
*/
|
||||
|
||||
#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
|
||||
#define POTAR_REG1 0x10818
|
||||
#define POTAR_REG2 0x10830
|
||||
|
||||
#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
|
||||
#define POBAR_REG1 0x10820
|
||||
#define POBAR_REG2 0x10838
|
||||
|
||||
#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
|
||||
#define POCMR_REG1 0x10828
|
||||
#define POCMR_REG2 0x10840
|
||||
|
||||
/* Bit definitions for POMCR registers */
|
||||
|
||||
#define POCMR_MASK_4KB 0x000FFFFF
|
||||
#define POCMR_MASK_8KB 0x000FFFFE
|
||||
#define POCMR_MASK_16KB 0x000FFFFC
|
||||
#define POCMR_MASK_32KB 0x000FFFF8
|
||||
#define POCMR_MASK_64KB 0x000FFFF0
|
||||
#define POCMR_MASK_128KB 0x000FFFE0
|
||||
#define POCMR_MASK_256KB 0x000FFFC0
|
||||
#define POCMR_MASK_512KB 0x000FFF80
|
||||
#define POCMR_MASK_1MB 0x000FFF00
|
||||
#define POCMR_MASK_2MB 0x000FFE00
|
||||
#define POCMR_MASK_4MB 0x000FFC00
|
||||
#define POCMR_MASK_8MB 0x000FF800
|
||||
#define POCMR_MASK_16MB 0x000FF000
|
||||
#define POCMR_MASK_32MB 0x000FE000
|
||||
#define POCMR_MASK_64MB 0x000FC000
|
||||
#define POCMR_MASK_128MB 0x000F8000
|
||||
#define POCMR_MASK_256MB 0x000F0000
|
||||
#define POCMR_MASK_512MB 0x000E0000
|
||||
#define POCMR_MASK_1GB 0x000C0000
|
||||
|
||||
#define POCMR_ENABLE 0x80000000
|
||||
#define POCMR_PCI_IO 0x40000000
|
||||
#define POCMR_PREFETCH_EN 0x20000000
|
||||
|
||||
/* Soft PCI reset */
|
||||
|
||||
#define PCI_GCR_REG 0x10880
|
||||
|
||||
/* Bit definitions for PCI_GCR registers */
|
||||
|
||||
#define PCIGCR_PCI_BUS_EN 0x1
|
||||
|
||||
/*
|
||||
* Inbound ATU registers (2 sets). These registers control how PCI addresses
|
||||
* are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
|
||||
*/
|
||||
|
||||
#define PITAR_REG1 0x108D0
|
||||
#define PIBAR_REG1 0x108D8
|
||||
#define PICMR_REG1 0x108E0
|
||||
#define PITAR_REG0 0x108E8
|
||||
#define PIBAR_REG0 0x108F0
|
||||
#define PICMR_REG0 0x108F8
|
||||
|
||||
/* Bit definitions for PCI Inbound Comparison Mask registers */
|
||||
|
||||
#define PICMR_MASK_4KB 0x000FFFFF
|
||||
#define PICMR_MASK_8KB 0x000FFFFE
|
||||
#define PICMR_MASK_16KB 0x000FFFFC
|
||||
#define PICMR_MASK_32KB 0x000FFFF8
|
||||
#define PICMR_MASK_64KB 0x000FFFF0
|
||||
#define PICMR_MASK_128KB 0x000FFFE0
|
||||
#define PICMR_MASK_256KB 0x000FFFC0
|
||||
#define PICMR_MASK_512KB 0x000FFF80
|
||||
#define PICMR_MASK_1MB 0x000FFF00
|
||||
#define PICMR_MASK_2MB 0x000FFE00
|
||||
#define PICMR_MASK_4MB 0x000FFC00
|
||||
#define PICMR_MASK_8MB 0x000FF800
|
||||
#define PICMR_MASK_16MB 0x000FF000
|
||||
#define PICMR_MASK_32MB 0x000FE000
|
||||
#define PICMR_MASK_64MB 0x000FC000
|
||||
#define PICMR_MASK_128MB 0x000F8000
|
||||
#define PICMR_MASK_256MB 0x000F0000
|
||||
#define PICMR_MASK_512MB 0x000E0000
|
||||
#define PICMR_MASK_1GB 0x000C0000
|
||||
|
||||
#define PICMR_ENABLE 0x80000000
|
||||
#define PICMR_NO_SNOOP_EN 0x40000000
|
||||
#define PICMR_PREFETCH_EN 0x20000000
|
||||
|
||||
/* PCI error Registers */
|
||||
|
||||
#define PCI_ERROR_STATUS_REG 0x10884
|
||||
#define PCI_ERROR_MASK_REG 0x10888
|
||||
#define PCI_ERROR_CONTROL_REG 0x1088C
|
||||
#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
|
||||
#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
|
||||
#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
|
||||
|
||||
/* PCI error Register bit defines */
|
||||
|
||||
#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
|
||||
#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
|
||||
#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
|
||||
#define PCI_ERROR_PCI_NO_RSP 0x00000008
|
||||
#define PCI_ERROR_PCI_TAR_ABT 0x00000010
|
||||
#define PCI_ERROR_PCI_SERR 0x00000020
|
||||
#define PCI_ERROR_PCI_PERR_RD 0x00000040
|
||||
#define PCI_ERROR_PCI_PERR_WR 0x00000080
|
||||
#define PCI_ERROR_I2O_OFQO 0x00000100
|
||||
#define PCI_ERROR_I2O_IPQO 0x00000200
|
||||
#define PCI_ERROR_IRA 0x00000400
|
||||
#define PCI_ERROR_NMI 0x00000800
|
||||
#define PCI_ERROR_I2O_DBMC 0x00001000
|
||||
|
||||
/*
|
||||
* Register pair used to generate configuration cycles on the PCI bus
|
||||
* and access the MPC826x's own PCI configuration registers.
|
||||
*/
|
||||
|
||||
#define PCI_CFG_ADDR_REG 0x10900
|
||||
#define PCI_CFG_DATA_REG 0x10904
|
||||
|
||||
/* Bus parking decides where the bus control sits when idle */
|
||||
/* If modifying memory controllers for PCI park on the core */
|
||||
|
||||
#define PPC_ACR_BUS_PARK_CORE 0x6
|
||||
#define PPC_ACR_BUS_PARK_PCI 0x3
|
||||
|
||||
#endif /* _PPC_KERNEL_M8260_PCI_H */
|
||||
|
|
@ -303,6 +303,10 @@
|
|||
# define CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_EEPRO100
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue