From 3c03f4928e96dce4c6cd14fb630dacad13a141ae Mon Sep 17 00:00:00 2001 From: "J. Tang" Date: Thu, 9 Feb 2017 21:54:13 -0500 Subject: [PATCH 1/4] x86: Force 32-bit jumps in interrupt handlers Depending upon the compiler used, IRQ entries could vary in sizes. With GCC 5.x, the code generator will use short jumps for some IRQ entries but near jumps for others. For example, GCC 5.4.0 generates the following: $ objdump -d interrupt.o 00000207 : 207: 6a 12 push $0x12 209: eb 85 jmp 190 0000020b : 20b: 6a 13 push $0x13 20d: eb 81 jmp 190 0000020f : 20f: 6a 14 push $0x14 211: e9 7a ff ff ff jmp 190 00000216 : 216: 6a 15 push $0x15 218: e9 73 ff ff ff jmp 190 This causes a problem in cpu_init_interrupts(), because the IDT setup assumed same sizes for all IRQ entries. GCC 4.x always generated 32-bit jumps, so this previously was not a problem. The fix is to force 32-bit near jumps for all entries within the inline assembly. This works for GCC 5.x, and 4.x was already using that form of jumping. Signed-off-by: Jason Tang Reviewed-by: Bin Meng --- arch/x86/cpu/i386/interrupt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index a05830326b..ba576fef3c 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; ".type irq_"#x", @function\n" \ "irq_"#x":\n" \ "pushl $"#x"\n" \ - "jmp irq_common_entry\n" + "jmp.d32 irq_common_entry\n" static char *exceptions[] = { "Divide Error", From 7a96fd8ef002e85ccd8ae5907de9d45fc9002c36 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 17 Feb 2017 16:48:58 +0300 Subject: [PATCH 2/4] x86: Introduce INTEL_MID quirk option Intel Mobile Internet Device (MID) platforms have special treatment in some cases, such as CPU enumeration or boot parameters configuration. Besides that several drivers are specifically developed for the IP blocks found on Intel MID platforms. Those drivers will be dependent to this option. Here we introduce specific quirk option for such cases. It is supposed to be selected by Intel MID platform boards, for example, Intel Edison. Reviewed-by: Bin Meng Reviewed-by: Simon Glass Signed-off-by: Andy Shevchenko --- arch/x86/Kconfig | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5f9597b230..dfdd7564ea 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -80,6 +80,20 @@ config VENDOR_INTEL endchoice +# subarchitectures-specific options below +config INTEL_MID + bool "Intel MID platform support" + help + Select to build a U-Boot capable of supporting Intel MID + (Mobile Internet Device) platform systems which do not have + the PCI legacy interfaces. + + If you are building for a PC class system say N here. + + Intel MID platforms are based on an Intel processor and + chipset which consume less power than most of the x86 + derivatives. + # board-specific options below source "board/advantech/Kconfig" source "board/congatec/Kconfig" From 20bfac0599bd7eaad901287fe4a343f9fd6cf6ef Mon Sep 17 00:00:00 2001 From: Vincent Tinelli Date: Fri, 17 Feb 2017 16:48:59 +0300 Subject: [PATCH 3/4] x86: zImage: add Intel MID platforms support Intel MID platform boards have special treatment, such as boot parameter setting. Assign hardware_subarch accordingly if CONFIG_INTEL_MID is set. Reviewed-by: Bin Meng Reviewed-by: Simon Glass Signed-off-by: Vincent Tinelli Signed-off-by: Andy Shevchenko --- arch/x86/lib/zimage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index b6b0f2beb3..aafbeb01f9 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -246,6 +246,10 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, hdr->setup_move_size = 0x9100; } +#if defined(CONFIG_INTEL_MID) + hdr->hardware_subarch = X86_SUBARCH_INTEL_MID; +#endif + /* build command line at COMMAND_LINE_OFFSET */ build_command_line(cmd_line, auto_boot); } From 308c75e08deac2933fbc63a1e9521343e710279c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 17 Feb 2017 16:49:00 +0300 Subject: [PATCH 4/4] x86: Intel MID platforms has no microcode update There is no microcode update available for SoCs used on Intel MID platforms. Use conditional to bypass it. Reviewed-by: Bin Meng Reviewed-by: Simon Glass Signed-off-by: Andy Shevchenko --- arch/x86/cpu/mp_init.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index 988073cc79..cfd9bb447b 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -248,7 +248,8 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus) if (!stack) return -ENOMEM; params->stack_top = (u32)(stack + size); -#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) +#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP) && \ + !defined(CONFIG_INTEL_MID) params->microcode_ptr = ucode_base; debug("Microcode at %x\n", params->microcode_ptr); #endif