OMAP3: Enable SPL on omap3_logic
Previously, Omap3_logic assumed X-loader was present. With this patch, we can finally replace X-loader with an MLO generated by U-Boot. This requires ECC to be setup to match the Linux Kernel and the PBIAS confgured for the SD card. Signed-off-by: Derald D. Woods <woods.technical@gmail.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Adam Ford
Tom Rini
parent
7443a9c405
commit
49c7303f0e
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@ -26,10 +26,15 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-types.h>
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#include <linux/mtd/nand.h>
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#include "omap3logic.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CONTROL_WKUP_CTRL 0x48002a5c
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#define GPIO_IO_PWRDNZ (1 << 6)
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#define PBIASLITEVMODE1 (1 << 8)
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/*
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* two dimensional array of strucures containining board name and Linux
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* machine IDs; row it selected based on CPU column is slected based
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@ -73,6 +78,57 @@ static struct board_id {
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},
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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return serial_tstc() && serial_getc() == 'c';
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}
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/*
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* Routine: get_board_mem_timings
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* Description: If we use SPL then there is no x-loader nor config header
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* so we have to setup the DDR timings ourself on the first bank. This
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* provides the timing values back to the function that configures
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* the memory.
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*/
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void get_board_mem_timings(struct board_sdrc_timings *timings)
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{
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timings->mr = MICRON_V_MR_165;
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/* 256MB DDR */
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timings->mcfg = MICRON_V_MCFG_200(256 << 20);
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timings->ctrla = MICRON_V_ACTIMA_200;
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timings->ctrlb = MICRON_V_ACTIMB_200;
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timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
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}
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#endif
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/*
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* Routine: misc_init_r
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* Description: Configure board specific parts
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*/
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int misc_init_r(void)
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{
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t2_t *t2_base = (t2_t *)T2_BASE;
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u32 pbias_lite;
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/* set up dual-voltage GPIOs to 1.8V */
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pbias_lite = readl(&t2_base->pbias_lite);
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pbias_lite &= ~PBIASLITEVMODE1;
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pbias_lite |= PBIASLITEPWRDNZ1;
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writel(pbias_lite, &t2_base->pbias_lite);
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if (get_cpu_family() == CPU_OMAP36XX)
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writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
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CONTROL_WKUP_CTRL);
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twl4030_power_init();
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omap_die_id_display();
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putc('\n');
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return 0;
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}
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/*
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* BOARD_ID_GPIO - GPIO of pin with optional pulldown resistor on SOM LV
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*/
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@ -11,112 +11,113 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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/* High Level Configuration Options */
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define CONFIG_SYS_TEXT_BASE 0x80400000
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/*
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* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
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* 64 bytes before this address should be set aside for u-boot.img's
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* header. That is 0x800FFFC0--0x80100000 should not be used for any
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* other needs. We use this rather than the inherited defines from
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* ti_armv7_common.h for backwards compatibility.
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*/
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#define CONFIG_SYS_TEXT_BASE 0x80100000
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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#include <configs/ti_omap3_common.h>
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#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
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/*
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* Display CPU and Board information
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*/
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/* Display CPU and Board information */
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Clock Defines */
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#define V_OSCK 26000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
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#define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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/* Sector */
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/*
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* Hardware drivers
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*/
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/* Hardware drivers */
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/* GPIO banks */
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#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
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/*
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* select serial console configuration
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*/
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#define CONFIG_USB_OMAP3
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/* select serial console configuration */
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#undef CONFIG_CONS_INDEX
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
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#define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_OMAP_HSMMC
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#define CONFIG_DOS_PARTITION
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/* commands to include */
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_EXT2 /* EXT2 Support */
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#define CONFIG_CMD_FAT /* FAT support */
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#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
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"1920k(u-boot),128k(u-boot-env),"\
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"4m(kernel),-(fs)"
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#define CONFIG_CMD_I2C /* I2C serial bus support */
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#define CONFIG_CMD_MMC /* MMC support */
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#define CONFIG_CMD_NAND /* NAND support */
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_YAFFS2
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/*
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* I2C
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
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#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
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/* I2C */
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#define CONFIG_SYS_I2C_OMAP34XX
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
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#define EXPANSION_EEPROM_I2C_BUS 2 /* I2C Bus for AT24C64 */
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#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID
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/*
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* TWL4030
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*/
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/* TWL4030 */
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#define CONFIG_TWL4030_PWM
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/*
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* Board NAND Info.
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*/
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#define CONFIG_SYS_NAND_BASE NAND_BASE
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/* Board NAND Info. */
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#ifdef CONFIG_NAND
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_CMD_UBI /* UBI-formated MTD partition support */
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#define CONFIG_CMD_UBIFS /* Read-only UBI volume operations */
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#define CONFIG_RBTREE /* required by CONFIG_CMD_UBI */
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#define CONFIG_LZO /* required by CONFIG_CMD_UBIFS */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
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/* to access nand */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
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/* NAND devices */
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#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_PAGE_SIZE 2048
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
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#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
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13, 14, 16, 17, 18, 19, 20, 21, 22, \
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23, 24, 25, 26, 27, 28, 30, 31, 32, \
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33, 34, 35, 36, 37, 38, 39, 40, 41, \
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42, 44, 45, 46, 47, 48, 49, 50, 51, \
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52, 53, 54, 55, 56}
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 13
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#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
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#define CONFIG_BCH
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_MAX_ECCPOS 56
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
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#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
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#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
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#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO),"\
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"1920k(u-boot),128k(u-boot-env),"\
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"4m(kernel),-(fs)"
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#endif
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/* Environment information */
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"echo \"Defaulting to 4.3 LCD panel (display=15).\";" \
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"setenv display 15;" \
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"setenv preboot;" \
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"nand unlock;" \
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"saveenv;"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x81000000\0" \
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"bootfile=uImage\0" \
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"uimage=uImage\0" \
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"zimage=zImage\0" \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"mmcdev=0\0" \
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"mmcroot=/dev/mmcblk0p2 rw\0" \
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"mmcrootfstype=ext4 rootwait\0" \
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"autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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@ -168,79 +172,77 @@
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"setenv bootargs ${bootargs} omapfb.vrfb=y " \
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"omapfb.rotate=${rotation}; " \
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"fi\0" \
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"otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
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"optargs=ignore_loglevel early_printk no_console_suspend\0" \
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"addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"common_bootargs=setenv bootargs ${bootargs} display=${display} " \
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"${otherbootargs};" \
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"${optargs};" \
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"run addmtdparts; " \
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"run vrfb_arg\0" \
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"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
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"bootscript=echo 'Running bootscript from mmc ...'; " \
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"source ${loadaddr}\0" \
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"loaduimage=mmc rescan ${mmcdev}; " \
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"fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
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"loaduimage=mmc rescan; " \
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"fatload mmc ${mmcdev} ${loadaddr} ${uimage}\0" \
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"loadzimage=mmc rescan; " \
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"fatload mmc ${mmcdev} ${loadaddr} ${zimage}\0" \
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"ramdisksize=64000\0" \
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"ramdiskaddr=0x82000000\0" \
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"ramdiskimage=rootfs.ext2.gz.uboot\0" \
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"loadramdisk=mmc rescan; " \
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"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}\0" \
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"ramargs=run setconsole; setenv bootargs console=${console} " \
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"root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \
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"mmcramboot=echo 'Booting kernel from mmc w/ramdisk...'; " \
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"mmcargs=run setconsole; setenv bootargs console=${console} " \
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"${optargs} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"fdtaddr=0x86000000\0" \
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"loadfdtimage=mmc rescan; " \
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"fatload mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \
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"mmcbootz=echo Booting with DT from mmc${mmcdev} ...; " \
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"run mmcargs; " \
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"run common_bootargs; " \
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"run dump_bootargs; " \
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"run loadzimage; " \
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"run loadfdtimage; " \
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"bootz ${loadaddr} - ${fdtaddr}\0" \
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"mmcramboot=echo 'Booting uImage kernel from mmc w/ramdisk...'; " \
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"run ramargs; " \
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"run common_bootargs; " \
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"run dump_bootargs; " \
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"run loaduimage; " \
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"fatload mmc ${mmcdev} ${ramdiskaddr} ${ramdiskimage}; "\
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"run loadramdisk; " \
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"bootm ${loadaddr} ${ramdiskaddr}\0" \
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"ramboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
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"mmcrambootz=echo 'Booting zImage kernel from mmc w/ramdisk...'; " \
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"run ramargs; " \
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"run common_bootargs; " \
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"run dump_bootargs; " \
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"tftpboot ${loadaddr} ${bootfile}; "\
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"tftpboot ${ramdiskaddr} ${ramdiskimage}; "\
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"run loadzimage; " \
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"run loadramdisk; " \
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"run loadfdtimage; " \
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"bootz ${loadaddr} ${ramdiskaddr} ${fdtaddr}\0; " \
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"tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \
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"run ramargs; " \
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"run common_bootargs; " \
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"run dump_bootargs; " \
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"tftpboot ${loadaddr} ${uimage}; " \
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"tftpboot ${ramdiskaddr} ${ramdiskimage}; " \
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"bootm ${loadaddr} ${ramdiskaddr}\0"
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#define CONFIG_BOOTCOMMAND \
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"run autoboot"
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/* Miscellaneous configurable options */
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#define CONFIG_AUTO_COMPLETE
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
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#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
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0x01F00000) /* 31MB */
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/*
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* OMAP3 has 12 GP timers, they can be driven by the system clock
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* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
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* This rate is divided by a local divisor.
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*/
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#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
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#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
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#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
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/*
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* FLASH and environment organization
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*/
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/* FLASH and environment organization */
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/* **** PISMO SUPPORT *** */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_SYS_FLASH_BASE NAND_BASE
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#elif defined(CONFIG_CMD_ONENAND)
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@ -250,29 +252,32 @@
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/* Monitor at start of flash */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
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#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
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#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
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#if defined(CONFIG_CMD_NAND)
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#define CONFIG_NAND_OMAP_GPMC
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
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#endif
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#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
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#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
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#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
|
||||
#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
|
||||
|
||||
/*
|
||||
* SMSC922x Ethernet
|
||||
*/
|
||||
/* SMSC922x Ethernet */
|
||||
#if defined(CONFIG_CMD_NET)
|
||||
|
||||
#define CONFIG_SMC911X
|
||||
#define CONFIG_SMC911X_16_BIT
|
||||
#define CONFIG_SMC911X_BASE 0x08000000
|
||||
|
||||
#endif /* (CONFIG_CMD_NET) */
|
||||
|
||||
/* Defines for SPL */
|
||||
|
||||
#define CONFIG_SPL_OMAP3_ID_NAND
|
||||
|
||||
/* NAND: SPL falcon mode configs */
|
||||
#ifdef CONFIG_SPL_OS_BOOT
|
||||
#define CONFIG_CMD_SPL_NAND_OFS 0x240000
|
||||
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
|
||||
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue