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armv8: layerscape: Update early MMU for DDR after initialization 

In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2017-03-06 09:02:34 -08:00
parent 7f9b9f318f
commit 4961eafc25
13 changed files with 113 additions and 38 deletions
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76
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -753,3 +753,79 @@ void efi_add_known_memory(void)
}
}
#endif
/*
* Before DDR size is known, early MMU table have DDR mapped as device memory
* to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
* needs to be set for these mappings.
* If a special case configures DDR with holes in the mapping, the holes need
* to be marked as invalid. This is not implemented in this function.
*/
void update_early_mmu_table(void)
{
if (!gd->arch.tlb_addr)
return;
if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE,
gd->ram_size,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
} else {
mmu_change_region_attr(
CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
#ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
#error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
#endif
if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
CONFIG_SYS_DDR_BLOCK2_SIZE) {
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE,
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK3_BASE,
gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE -
CONFIG_SYS_DDR_BLOCK2_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
} else
#endif
{
mmu_change_region_attr(
CONFIG_SYS_DDR_BLOCK2_BASE,
gd->ram_size -
CONFIG_SYS_DDR_BLOCK1_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE |
PTE_BLOCK_NS |
PTE_TYPE_VALID);
}
}
}
__weak int dram_init(void)
{
gd->ram_size = initdram(0);
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}

12
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View File

@ -115,7 +115,11 @@ static struct mm_region early_map[] = {
},
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
@ -130,7 +134,7 @@ static struct mm_region early_map[] = {
},
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#elif defined(CONFIG_FSL_LSCH2)
@ -158,12 +162,16 @@ static struct mm_region early_map[] = {
},
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
#endif

2
arch/arm/include/asm/arch-fsl-layerscape/mmu.h
View File

@ -6,5 +6,5 @@
#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
#include <asm/arch-armv8/mmu.h>
void update_early_mmu_table(void);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */

5
board/freescale/ls1012afrdm/ls1012afrdm.c
View File

@ -12,6 +12,7 @@
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <environment.h>
@ -48,6 +49,10 @@ int dram_init(void)
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}

5
board/freescale/ls1012aqds/ls1012aqds.c
View File

@ -14,6 +14,7 @@
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@ -76,6 +77,10 @@ int dram_init(void)
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}

5
board/freescale/ls1012ardb/ls1012ardb.c
View File

@ -12,6 +12,7 @@
#ifdef CONFIG_FSL_LS_PPA
#include <asm/arch/ppa.h>
#endif
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <hwconfig.h>
#include <ahci.h>
@ -80,6 +81,10 @@ int dram_init(void)
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}

5
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@ -153,6 +154,10 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}

7
board/freescale/ls1043ardb/ls1043ardb.c
View File

@ -67,13 +67,6 @@ int checkboard(void)
return 0;
}
int dram_init(void)
{
gd->ram_size = initdram(0);
return 0;
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();

5
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -11,6 +11,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
@ -149,6 +150,10 @@ int dram_init(void)
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}

7
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -56,13 +56,6 @@ int checkboard(void)
return 0;
}
int dram_init(void)
{
gd->ram_size = initdram(0);
return 0;
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();

7
board/freescale/ls2080a/ls2080a.c
View File

@ -49,13 +49,6 @@ void detail_board_ddr_info(void)
#endif
}
int dram_init(void)
{
gd->ram_size = initdram(0);
return 0;
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{

7
board/freescale/ls2080aqds/ls2080aqds.c
View File

@ -254,13 +254,6 @@ void detail_board_ddr_info(void)
#endif
}
int dram_init(void)
{
gd->ram_size = initdram(0);
return 0;
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{

8
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -17,6 +17,7 @@
#include <environment.h>
#include <efi_loader.h>
#include <i2c.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
#include <fsl_sec.h>
@ -219,13 +220,6 @@ void detail_board_ddr_info(void)
#endif
}
int dram_init(void)
{
gd->ram_size = initdram(0);
return 0;
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{