imx: Add support for zmx25 board
zmx25 is a board based on imx25 SoC, 64 Megs of LPDDR, 32 Megs of NOR flash, an optional NAND flash. Signed-off-by: Matthias Weisser <weisserm@arcor.de>
This commit is contained in:
Matthias Weisser
Albert ARIBAUD
parent
95d185894b
commit
39f0023e81
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@ -904,6 +904,7 @@ Lei Wen <leiwen@marvell.com>
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Matthias Weisser <weisserm@arcor.de>
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jadecpu ARM926EJS (MB86R01 SoC)
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zmx25 ARM926EJS (imx25 SoC)
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Richard Woodruff <r-woodruff2@ti.com>
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@ -0,0 +1,64 @@
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/*
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* (C) Copyright 2011
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* Matthias Weisser <weisserm@arcor.de>
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*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Common asm macros for imx25
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_ARCH_MACRO_H__
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#define __ASM_ARM_ARCH_MACRO_H__
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#ifdef __ASSEMBLY__
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/asm-offsets.h>
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.macro init_aips
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write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
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write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
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write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
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write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
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.endm
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.macro init_max
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write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
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write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
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write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
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write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
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write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
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write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
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write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
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write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
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write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
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write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
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write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
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write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
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write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
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write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
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write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_ARCH_MACRO_H__ */
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@ -0,0 +1,51 @@
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#
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# (c) 2010 Graf-Syteco, Matthias Weisser
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# <weisserm@arcor.de>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += zmx25.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,110 @@
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/*
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* (C) Copyright 2011
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* Matthias Weisser <weisserm@arcor.de>
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*
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on U-Boot and RedBoot sources for several different i.mx
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* platforms.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/macro.h>
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#include <asm/arch/macro.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/asm-offsets.h>
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/*
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* clocks
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*/
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.macro init_clocks
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/* disable clock output */
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write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
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write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
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/*
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* enable all implemented clocks in all three
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* clock control registers
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*/
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write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
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write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
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write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
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/* Devide NAND clock by 32 */
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write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
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.endm
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/*
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* sdram controller init
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*/
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.macro init_lpddr
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ldr r0, =IMX_ESDRAMC_BASE
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ldr r2, =IMX_SDRAM_BANK0_BASE
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/*
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* reset SDRAM controller
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* then wait for initialization to complete
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*/
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ldr r1, =(1 << 1) | (1 << 2)
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str r1, [r0, #ESDRAMC_ESDMISC]
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1: ldr r3, [r0, #ESDRAMC_ESDMISC]
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tst r3, #(1 << 31)
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beq 1b
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ldr r1, =(1 << 2)
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str r1, [r0, #ESDRAMC_ESDMISC]
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ldr r1, =0x002a7420
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str r1, [r0, #ESDRAMC_ESDCFG0]
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/* control | precharge */
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ldr r1, =0x92216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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/* dram command encoded in address */
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str r1, [r2, #0x400]
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/* auto refresh */
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ldr r1, =0xa2216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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/* read dram twice to auto refresh */
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ldr r3, [r2]
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ldr r3, [r2]
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/* control | load mode */
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ldr r1, =0xb2216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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/* mode register of lpddram */
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strb r1, [r2, #0x33]
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/* extended mode register of lpddrram */
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ldr r2, =0x81000000
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strb r1, [r2]
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/* control | normal */
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ldr r1, =0x82216008
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str r1, [r0, #ESDRAMC_ESDCTL0]
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.endm
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.globl lowlevel_init
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lowlevel_init:
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init_aips
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init_max
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init_clocks
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init_lpddr
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mov pc, lr
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@ -0,0 +1,203 @@
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/*
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* (c) 2011 Graf-Syteco, Matthias Weisser
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* <weisserm@arcor.de>
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*
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* Based on tx25.c:
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* (C) Copyright 2009 DENX Software Engineering
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* Author: John Rigby <jrigby@gmail.com>
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*
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* Based on imx27lite.c:
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* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
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* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
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* And:
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* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <mxc_gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx25-pinmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init()
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{
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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struct iomuxc_pad_input_select *inputselect;
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u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
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u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
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u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
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u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
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u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
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u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
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icache_enable();
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
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/* Setup of core volatage selection pin to run at 1.4V */
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writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
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/* Setup of input daisy chains for SD card pins*/
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
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writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
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/* Setup of digital output for USB power and OC */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
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writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN);
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/* Setup of digital output control pins */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
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writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
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writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
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writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
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/* Switch both output drivers off */
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT);
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/* Setup of key input pin GPIO2[29]*/
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writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
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writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN);
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/* Setup of status LED outputs */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
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writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
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/* Switch both LEDs off */
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT);
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT);
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/* Setup of CAN1 and CAN2 signals */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
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writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
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/* Setup of input daisy chains for CAN signals*/
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writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
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writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
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/* Setup of I2C3 signals */
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writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
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writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
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/* Setup of input daisy chains for I2C3 signals*/
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writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
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writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
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/* board id for linux */
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gd->bd->bi_arch_number = MACH_TYPE_ZMX25;
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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return 0;
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}
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int board_late_init(void)
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{
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const char *e;
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#ifdef CONFIG_FEC_MXC
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struct iomuxc_mux_ctl *muxctl;
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struct iomuxc_pad_ctl *padctl;
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u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
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u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
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/*
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* fec pin init is generic
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*/
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mx25_fec_init_pins();
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/*
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* Set up LAN-RESET and FEC_RX_ERR
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*
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* LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
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* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
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*/
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muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
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padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
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writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
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writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
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/* assert PHY reset (low) */
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mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
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mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT);
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udelay(5000);
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/* deassert PHY reset */
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||||
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
|
||||
|
||||
udelay(5000);
|
||||
#endif
|
||||
|
||||
e = getenv("gs_base_board");
|
||||
if (e != NULL) {
|
||||
if (strcmp(e, "G283") == 0) {
|
||||
int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29));
|
||||
|
||||
if (key) {
|
||||
/* Switch on both LEDs to inidcate boot mode */
|
||||
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
|
||||
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
|
||||
|
||||
setenv("preboot", "run gs_slow_boot");
|
||||
} else
|
||||
setenv("preboot", "run gs_fast_boot");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
|
||||
PHYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dram_init_banksize(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size = gd->ram_size;
|
||||
}
|
||||
|
|
@ -131,6 +131,7 @@ rd6281a arm arm926ejs - Marvell
|
|||
sheevaplug arm arm926ejs - Marvell kirkwood
|
||||
dockstar arm arm926ejs - Seagate kirkwood
|
||||
jadecpu arm arm926ejs jadecpu syteco mb86r0x
|
||||
zmx25 arm arm926ejs zmx25 syteco mx25
|
||||
imx27lite arm arm926ejs imx27lite logicpd mx27
|
||||
magnesium arm arm926ejs imx27lite logicpd mx27
|
||||
nhk8815 arm arm926ejs nhk8815 st nomadik
|
||||
|
|
|
|||
|
|
@ -0,0 +1,180 @@
|
|||
/*
|
||||
* (c) 2011 Graf-Syteco, Matthias Weisser
|
||||
* <weisserm@arcor.de>
|
||||
*
|
||||
* Configuation settings for the zmx25 board
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
|
||||
#define CONFIG_MX25
|
||||
#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_TEXT_BASE 0xA0000000
|
||||
|
||||
/*
|
||||
* Environment settings
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"gs_fast_boot=setenv bootdelay 5\0" \
|
||||
"gs_slow_boot=setenv bootdelay 10\0" \
|
||||
"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
|
||||
"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
|
||||
"bootm 0x81000000; bootelf 0x81000000\0"
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
/*
|
||||
* Compressions
|
||||
*/
|
||||
#define CONFIG_LZO
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
#define CONFIG_MXC_GPIO
|
||||
|
||||
/*
|
||||
* Serial
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_SYS_MX25_UART2
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x00
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_CACHE
|
||||
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF
|
||||
|
||||
/*
|
||||
* Additional command
|
||||
*/
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
|
||||
#define CONFIG_USB_EHCI_MXC
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORT 2
|
||||
#define CONFIG_MXC_USB_PORTSC 0xC0000000
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
#endif /* CONFIG_CMD_USB */
|
||||
|
||||
/* SDRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
|
||||
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xA0000000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE (128 * 1024)
|
||||
|
||||
/*
|
||||
* CFI FLASH driver setup
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
|
||||
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_PROMPT "zmx25> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
#define CONFIG_PREBOOT ""
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_AUTOBOOT_KEYED
|
||||
#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
|
||||
#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue