x86: Rename PORT_RESET to IO_PORT_RESET

This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-03-11 22:06:59 -07:00 committed by Bin Meng
parent 50dd3da004
commit 2a605d4d88
3 changed files with 5 additions and 5 deletions

View File

@ -469,14 +469,14 @@ void flush_cache(unsigned long dummy1, unsigned long dummy2)
__weak void reset_cpu(ulong addr)
{
/* Do a hard reset through the chipset's reset control register */
outb(SYS_RST | RST_CPU, PORT_RESET);
outb(SYS_RST | RST_CPU, IO_PORT_RESET);
for (;;)
cpu_hlt();
}
void x86_full_reset(void)
{
outb(FULL_RST | SYS_RST | RST_CPU, PORT_RESET);
outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET);
}
int dcache_status(void)

View File

@ -102,8 +102,8 @@ int cpu_set_flex_ratio_to_tdp_nominal(void)
setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
/* Issue warm reset, will be "CPU only" due to soft reset data */
outb(0x0, PORT_RESET);
outb(SYS_RST | RST_CPU, PORT_RESET);
outb(0x0, IO_PORT_RESET);
outb(SYS_RST | RST_CPU, IO_PORT_RESET);
cpu_hlt();
/* Not reached */

View File

@ -36,7 +36,7 @@
*
* The naming follows Intel's naming.
*/
#define PORT_RESET 0xcf9
#define IO_PORT_RESET 0xcf9
enum {
SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */