From 2a5788adc4550a1dd91526e8ec8f9f27b9fc7c1f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 3 Feb 2014 15:45:03 -0600 Subject: [PATCH] ARM: DRA7: leave control module unlocked Locking control_core_mmr_lock1 register results in regions 0x00000100 to 0x0000079F locked out(includes key registers for bandgap etc). This means that any write accesses will fail to reflect results without a clear notification. So, leave the control module unlocked. TODO: SPL should reflect consistent behavior for entire Control module space which includes LOCK_1-5 regions left open -> if this is done, this should be implemented in a generic location independent of the current logic. Reported-by: Yan Liu Reported-by: Mugunthan V Signed-off-by: Nishanth Menon --- arch/arm/cpu/armv7/omap5/hw_data.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 562a25fa45..a7dd17e8b0 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -359,11 +359,10 @@ void recalibrate_io_delay(void) clrsetbits_le32((*prcm)->prm_io_pmctrl, (1 << 0), 0x0); - /* Lock the MMR_LOCK1 */ - writel(0x1A1C8144, (*ctrl)->control_core_mmr_lock1); - /* Lock the global lock to write to the MMRs */ writel(0x0000AAAB, (*ctrl)->iodelay_config_reg_8); + + /* Leave the control module unlocked */ } #endif /* CONFIG_SPL_BUILD */