armv8: fsl-lsch3: Update VID support
VID support in NXP layerscape Chassis-3 (lsch3) compilant SoCs like LS2088A, LS2080A differs from existing logic. -VDD voltage array is different -Registers are different -VDD calculation logic is different Add new function adjust_vdd() for LSCH3 compliant SoCs Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Arpit Goel <arpit.goel@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Priyanka Jain
York Sun
parent
27f133bbcf
commit
29ca713cc1
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@ -180,9 +180,9 @@ struct ccsr_gur {
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u32 gpporcr3;
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u32 gpporcr4;
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u8 res_030[0x60-0x30];
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#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
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#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
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#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
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#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
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#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
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#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
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u32 dcfg_fusesr; /* Fuse status register */
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u8 res_064[0x70-0x64];
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@ -284,10 +284,170 @@ static int set_voltage(int i2caddress, int vdd)
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return vdd_last;
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}
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#ifdef CONFIG_FSL_LSCH3
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int adjust_vdd(ulong vdd_override)
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{
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int re_enable = disable_interrupts();
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#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 fusesr;
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u8 vid, buf;
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int vdd_target, vdd_current, vdd_last;
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int ret, i2caddress;
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unsigned long vdd_string_override;
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char *vdd_string;
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static const uint16_t vdd[32] = {
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10500,
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0, /* reserved */
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9750,
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0, /* reserved */
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9500,
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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10000, /* 1.0000V */
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0, /* reserved */
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10250,
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0, /* reserved */
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10500,
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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0, /* reserved */
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};
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struct vdd_drive {
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u8 vid;
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unsigned voltage;
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};
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ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
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if (ret) {
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debug("VID: I2C failed to switch channel\n");
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ret = -1;
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goto exit;
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}
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ret = find_ir_chip_on_i2c();
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if (ret < 0) {
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printf("VID: Could not find voltage regulator on I2C.\n");
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ret = -1;
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goto exit;
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} else {
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i2caddress = ret;
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debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
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}
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/* check IR chip work on Intel mode*/
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ret = i2c_read(i2caddress,
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IR36021_INTEL_MODE_OOFSET,
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1, (void *)&buf, 1);
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if (ret) {
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printf("VID: failed to read IR chip mode.\n");
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ret = -1;
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goto exit;
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}
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if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
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printf("VID: IR Chip is not used in Intel mode.\n");
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ret = -1;
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goto exit;
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}
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/* get the voltage ID from fuse status register */
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fusesr = in_le32(&gur->dcfg_fusesr);
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vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
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FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
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if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
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vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
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FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
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}
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vdd_target = vdd[vid];
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/* check override variable for overriding VDD */
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vdd_string = getenv(CONFIG_VID_FLS_ENV);
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if (vdd_override == 0 && vdd_string &&
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!strict_strtoul(vdd_string, 10, &vdd_string_override))
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vdd_override = vdd_string_override;
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if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
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vdd_target = vdd_override * 10; /* convert to 1/10 mV */
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debug("VDD override is %lu\n", vdd_override);
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} else if (vdd_override != 0) {
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printf("Invalid value.\n");
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}
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/* divide and round up by 10 to get a value in mV */
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vdd_target = DIV_ROUND_UP(vdd_target, 10);
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if (vdd_target == 0) {
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debug("VID: VID not used\n");
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ret = 0;
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goto exit;
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} else if (vdd_target < VDD_MV_MIN || vdd_target > VDD_MV_MAX) {
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/* Check vdd_target is in valid range */
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printf("VID: Target VID %d mV is not in range.\n",
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vdd_target);
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ret = -1;
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goto exit;
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} else {
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debug("VID: vid = %d mV\n", vdd_target);
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}
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/*
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* Read voltage monitor to check real voltage.
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*/
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vdd_last = read_voltage(i2caddress);
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if (vdd_last < 0) {
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printf("VID: Couldn't read sensor abort VID adjustment\n");
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ret = -1;
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goto exit;
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}
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vdd_current = vdd_last;
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debug("VID: Core voltage is currently at %d mV\n", vdd_last);
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/*
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* Adjust voltage to at or one step above target.
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* As measurements are less precise than setting the values
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* we may run through dummy steps that cancel each other
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* when stepping up and then down.
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*/
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while (vdd_last > 0 &&
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vdd_last < vdd_target) {
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vdd_current += IR_VDD_STEP_UP;
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vdd_last = set_voltage(i2caddress, vdd_current);
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}
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while (vdd_last > 0 &&
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vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
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vdd_current -= IR_VDD_STEP_DOWN;
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vdd_last = set_voltage(i2caddress, vdd_current);
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}
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if (vdd_last > 0)
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printf("VID: Core voltage after adjustment is at %d mV\n",
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vdd_last);
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else
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ret = -1;
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exit:
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if (re_enable)
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enable_interrupts();
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i2c_multiplexer_select_vid_channel(I2C_MUX_CH_DEFAULT);
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return ret;
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}
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#else /* !CONFIG_FSL_LSCH3 */
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int adjust_vdd(ulong vdd_override)
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{
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int re_enable = disable_interrupts();
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#if defined(CONFIG_FSL_LSCH2)
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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#else
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ccsr_gur_t __iomem *gur =
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@ -364,11 +524,7 @@ int adjust_vdd(ulong vdd_override)
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}
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/* get the voltage ID from fuse status register */
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#ifdef CONFIG_FSL_LSCH3
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fusesr = in_le32(&gur->dcfg_fusesr);
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#else
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fusesr = in_be32(&gur->dcfg_fusesr);
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#endif
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/*
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* VID is used according to the table below
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* ---------------------------------------
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@ -393,13 +549,6 @@ int adjust_vdd(ulong vdd_override)
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vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
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FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
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}
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#elif defined(CONFIG_FSL_LSCH3)
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vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
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FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
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if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
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vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
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FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
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}
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#else
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vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
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FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
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@ -472,6 +621,7 @@ exit:
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return ret;
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}
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#endif
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static int print_vdd(void)
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{
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