diff --git a/arch/arm/cpu/armv7/mx7ulp/clock.c b/arch/arm/cpu/armv7/mx7ulp/clock.c index 1c072b8198..77b282addd 100644 --- a/arch/arm/cpu/armv7/mx7ulp/clock.c +++ b/arch/arm/cpu/armv7/mx7ulp/clock.c @@ -313,6 +313,16 @@ void clock_init(void) enable_usboh3_clk(1); } +#ifdef CONFIG_SECURE_BOOT +void hab_caam_clock_enable(unsigned char enable) +{ + if (enable) + pcc_clock_enable(PER_CLK_CAAM, true); + else + pcc_clock_enable(PER_CLK_CAAM, false); +} +#endif + /* * Dump some core clockes. */ diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c index 8713e9bf80..4fd4c3a32f 100644 --- a/arch/arm/cpu/armv7/mx7ulp/soc.c +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c @@ -7,9 +7,17 @@ #include #include #include +#include static char *get_reset_cause(char *); +#if defined(CONFIG_SECURE_BOOT) +struct imx_sec_config_fuse_t const imx_sec_config_fuse = { + .bank = 29, + .word = 6, +}; +#endif + u32 get_cpu_rev(void) { /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */ diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c index 7449487f0d..523d0e3b38 100644 --- a/arch/arm/imx-common/hab.c +++ b/arch/arm/imx-common/hab.c @@ -77,7 +77,8 @@ #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18 #define IS_HAB_ENABLED_BIT \ - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2) + (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ + (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) /* * +------------+ 0x0 (DDR_UIMAGE_START) - diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index ebf32c6c2c..170a9b3a7c 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -39,4 +39,5 @@ void enable_usboh3_clk(unsigned char enable); #endif void init_clk_usdhc(u32 index); void clock_init(void); +void hab_caam_clock_enable(unsigned char enable); #endif